diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index 5087bf69a..c0460c262 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -2922,13 +2922,13 @@ "fcmp s16, s17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -2941,13 +2941,13 @@ "fcmp d16, d17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -2960,13 +2960,13 @@ "fcmp s16, s17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -2979,13 +2979,13 @@ "fcmp d16, d17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json index 77a9d8502..4caafba40 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json @@ -13,7 +13,7 @@ }, "Instructions": { "vucomiss xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": [ "Map 1 0b00 0x2e 128-bit" ], @@ -21,12 +21,11 @@ "fcmp s16, s17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "vucomisd xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": [ "Map 1 0b01 0x2e 128-bit" ], @@ -34,12 +33,11 @@ "fcmp d16, d17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "vcomiss xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": [ "Map 1 0b00 0x2f 128-bit" ], @@ -47,12 +45,11 @@ "fcmp s16, s17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "vcomisd xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": [ "Map 1 0b01 0x2f 128-bit" ], @@ -60,8 +57,7 @@ "fcmp d16, d17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] } } diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index 32e489fd2..b5e2ebb39 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -528,10 +528,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -560,10 +560,10 @@ "addv s2, v2.4s", "mov w21, v2.s[0]", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -586,10 +586,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -618,10 +618,10 @@ "addp v2.2d, v2.2d, v2.2d", "mov x21, v2.d[0]", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -693,10 +693,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -721,10 +721,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json index 4135e6e52..b623bedc6 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json @@ -32,8 +32,8 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -62,8 +62,8 @@ "addv s2, v2.4s", "mov w21, v2.s[0]", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -86,8 +86,8 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -116,8 +116,8 @@ "addp v2.2d, v2.2d, v2.2d", "mov x21, v2.d[0]", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -136,8 +136,8 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -162,8 +162,8 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -622,7 +622,7 @@ ], "ExpectedArm64ASM": [ "bic w26, w5, w7", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -633,7 +633,7 @@ ], "ExpectedArm64ASM": [ "bic x26, x5, x7", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, @@ -648,8 +648,8 @@ "bic w20, w7, w20", "tst x5, #0xe0", "csel w4, w7, w20, ne", - "cset w20, ne", - "tst w4, w4", + "cset w20, eq", + "cmp w4, #0x0 (0)", "rmif x20, #63, #nzCv" ] }, @@ -664,8 +664,8 @@ "bic x20, x7, x20", "tst x5, #0xc0", "csel x4, x7, x20, ne", - "cset w20, ne", - "tst x4, x4", + "cset w20, eq", + "cmp x4, #0x0 (0)", "rmif x20, #63, #nzCv" ] }, @@ -730,7 +730,7 @@ "bic w22, w20, w22", "cmp w21, #0x1f (31)", "csel w4, w22, w20, ls", - "tst w4, w4" + "cmp w4, #0x0 (0)" ] }, "bextr rax, rbx, rcx": { @@ -750,7 +750,7 @@ "bic x22, x20, x22", "cmp x21, #0x3f (63)", "csel x4, x22, x20, ls", - "tst x4, x4" + "cmp x4, #0x0 (0)" ] } } diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index d13318cbb..236ae4764 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -12,52 +12,67 @@ }, "Instructions": { "lock add byte [rax], cl": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "0x00", "ExpectedArm64ASM": [ "ldaddalb w5, w20, [x4]", "eor w27, w20, w5", "lsl w0, w20, #24", "cmn w0, w5, lsl #24", - "add w26, w20, w5" + "add w26, w20, w5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add word [rax], cx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddalh w5, w20, [x4]", "eor w27, w20, w5", "lsl w0, w20, #16", "cmn w0, w5, lsl #16", - "add w26, w20, w5" + "add w26, w20, w5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add dword [rax], ecx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal w5, w20, [x4]", "eor w27, w20, w5", - "adds w26, w20, w5" + "adds w26, w20, w5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock or byte [rax], cl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x08", "ExpectedArm64ASM": [ "ldsetalb w5, w20, [x4]", "orr w26, w20, w5", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock or word [rax], cx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x09", "ExpectedArm64ASM": [ "ldsetalh w5, w20, [x4]", "orr w26, w20, w5", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock or dword [rax], ecx": { @@ -66,22 +81,22 @@ "ExpectedArm64ASM": [ "ldsetal w5, w20, [x4]", "orr w26, w20, w5", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock adc byte [rax], cl": { "ExpectedInstructionCount": 18, "Comment": "0x10", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "ldaddalb w20, w20, [x4]", "eor w27, w20, w5", "uxtb w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "add w23, w20, w22", "uxtb w26, w23", "cmp w26, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #24", "mrs x23, nzcv", "orr w22, w23, w22, lsl #29", @@ -97,15 +112,15 @@ "ExpectedInstructionCount": 18, "Comment": "0x11", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "ldaddalh w20, w20, [x4]", "eor w27, w20, w5", "uxth w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "add w23, w20, w22", "uxth w26, w23", "cmp w26, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #16", "mrs x23, nzcv", "orr w22, w23, w22, lsl #29", @@ -118,30 +133,36 @@ ] }, "lock adc dword [rax], ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "0x11", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "ldaddal w20, w20, [x4]", "eor w27, w20, w5", - "adcs w26, w20, w5" + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "adcs w26, w20, w5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock sbb byte [rax], cl": { "ExpectedInstructionCount": 20, "Comment": "0x18", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "neg w1, w20", "ldaddalb w1, w20, [x4]", "eor w27, w20, w5", "uxtb w20, w20", "uxtb w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxtb w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #24", "mrs x23, nzcv", "orr w22, w23, w22, lsl #29", @@ -157,17 +178,17 @@ "ExpectedInstructionCount": 20, "Comment": "0x19", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "neg w1, w20", "ldaddalh w1, w20, [x4]", "eor w27, w20, w5", "uxth w20, w20", "uxth w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxth w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #16", "mrs x23, nzcv", "orr w22, w23, w22, lsl #29", @@ -180,53 +201,56 @@ ] }, "lock sbb dword [rax], ecx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 5, "Comment": "0x19", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "neg w1, w20", "ldaddal w1, w20, [x4]", "eor w27, w20, w5", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sbcs w26, w20, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sbcs w26, w20, w5" ] }, "lock and byte [rax], cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "0x20", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclralb w1, w20, [x4]", "and w26, w20, w5", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and word [rax], cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "0x21", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclralh w1, w20, [x4]", "and w26, w20, w5", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and dword [rax], ecx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x21", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclral w1, w20, [x4]", - "ands w26, w20, w5" + "ands w26, w20, w5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock sub byte [rax], cl": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "0x28", "ExpectedArm64ASM": [ "neg w1, w5", @@ -234,14 +258,11 @@ "eor w27, w20, w5", "lsl w0, w20, #24", "cmp w0, w5, lsl #24", - "sub w26, w20, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w20, w5" ] }, "lock sub word [rax], cx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "0x28", "ExpectedArm64ASM": [ "neg w1, w5", @@ -249,41 +270,41 @@ "eor w27, w20, w5", "lsl w0, w20, #16", "cmp w0, w5, lsl #16", - "sub w26, w20, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w20, w5" ] }, "lock sub dword [rax], ecx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "0x29", "ExpectedArm64ASM": [ "neg w1, w5", "ldaddal w1, w20, [x4]", "eor w27, w20, w5", - "subs w26, w20, w5", + "subs w26, w20, w5" + ] + }, + "lock xor byte [rax], cl": { + "ExpectedInstructionCount": 6, + "Comment": "0x30", + "ExpectedArm64ASM": [ + "ldeoralb w5, w20, [x4]", + "eor w26, w20, w5", + "cmn wzr, w26, lsl #24", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, - "lock xor byte [rax], cl": { - "ExpectedInstructionCount": 3, - "Comment": "0x30", - "ExpectedArm64ASM": [ - "ldeoralb w5, w20, [x4]", - "eor w26, w20, w5", - "cmn wzr, w26, lsl #24" - ] - }, "lock xor word [rax], cx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x31", "ExpectedArm64ASM": [ "ldeoralh w5, w20, [x4]", "eor w26, w20, w5", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock xor dword [rax], ecx": { @@ -292,16 +313,19 @@ "ExpectedArm64ASM": [ "ldeoral w5, w20, [x4]", "eor w26, w20, w5", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock add qword [rax], rcx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal x5, x20, [x4]", "eor w27, w20, w5", - "adds x26, x20, x5" + "adds x26, x20, x5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xchg byte [rax], cl": { @@ -335,7 +359,7 @@ ] }, "xadd byte [rax], bl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -344,11 +368,14 @@ "lsl w0, w21, #24", "cmn w0, w20, lsl #24", "add w26, w21, w20", - "bfxil x7, x21, #0, #8" + "bfxil x7, x21, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xadd word [rax], bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -357,42 +384,54 @@ "lsl w0, w21, #16", "cmn w0, w20, lsl #16", "add w26, w21, w20", - "bfxil x7, x21, #0, #16" + "bfxil x7, x21, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xadd dword [rax], ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", "eor w27, w7, w20", - "adds w26, w7, w20" + "adds w26, w7, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xadd qword [rax], rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "ldaddal x7, x20, [x4]", "eor w27, w20, w7", "adds x26, x20, x7", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "mov x7, x20" ] }, "lock add byte [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalb w20, w27, [x4]", "lsl w0, w27, #24", "cmn w0, w20, lsl #24", - "add w26, w27, #0x1 (1)" + "add w26, w27, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add byte [rax], 0xFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -400,22 +439,28 @@ "mvn w27, w21", "lsl w0, w21, #24", "cmn w0, w20, lsl #24", - "add w26, w21, #0xff (255)" + "add w26, w21, #0xff (255)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add word [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddalh w20, w27, [x4]", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", - "add w26, w27, #0x100 (256)" + "add w26, w27, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add word [rax], 0xFFFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -423,113 +468,149 @@ "mvn w27, w21", "lsl w0, w21, #16", "cmn w0, w20, lsl #16", - "add w26, w21, w20" + "add w26, w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add dword [rax], 0x100": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddal w20, w27, [x4]", - "adds w26, w27, #0x100 (256)" + "adds w26, w27, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldaddal w20, w21, [x4]", "mvn w27, w21", - "adds w26, w21, w20" + "adds w26, w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add qword [rax], 0x100": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddal x20, x27, [x4]", - "adds x26, x27, #0x100 (256)" + "adds x26, x27, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add qword [rax], -2147483647": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "ldaddal x20, x27, [x4]", - "adds x26, x27, x20" + "adds x26, x27, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add word [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalh w20, w27, [x4]", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", - "add w26, w27, #0x1 (1)" + "add w26, w27, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add dword [rax], 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal w20, w27, [x4]", - "adds w26, w27, #0x1 (1)" + "adds w26, w27, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock add qword [rax], 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal x20, x27, [x4]", - "adds x26, x27, #0x1 (1)" + "adds x26, x27, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock or byte [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetalb w20, w20, [x4]", "orr w26, w20, #0x1", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock or byte [rax], 0xFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "mov w20, #0xff", "ldsetalb w20, w20, [x4]", "orr w26, w20, #0xff", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock or word [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldsetalh w20, w20, [x4]", "orr w26, w20, #0x100", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock or word [rax], 0xFFFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldsetalh w20, w20, [x4]", "orr w26, w20, #0xffff", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock or dword [rax], 0x100": { @@ -539,7 +620,7 @@ "mov w20, #0x100", "ldsetal w20, w20, [x4]", "orr w26, w20, #0x100", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock or dword [rax], 0xFFFFFFFF": { @@ -549,7 +630,7 @@ "mov w20, #0xffffffff", "ldsetal w20, w21, [x4]", "orr w26, w21, w20", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock or qword [rax], 0x100": { @@ -559,7 +640,7 @@ "mov w20, #0x100", "ldsetal x20, x20, [x4]", "orr x26, x20, #0x100", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock or qword [rax], -2147483647": { @@ -569,17 +650,20 @@ "mov x20, #0xffffffff80000001", "ldsetal x20, x20, [x4]", "orr x26, x20, #0xffffffff80000001", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock or word [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetalh w20, w20, [x4]", "orr w26, w20, #0x1", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock or dword [rax], 1": { @@ -589,7 +673,7 @@ "mov w20, #0x1", "ldsetal w20, w20, [x4]", "orr w26, w20, #0x1", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock or qword [rax], 1": { @@ -599,7 +683,7 @@ "mov w20, #0x1", "ldsetal x20, x20, [x4]", "orr x26, x20, #0x1", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock adc byte [rax], 1": { @@ -607,14 +691,14 @@ "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "ldaddalb w20, w27, [x4]", "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w27, w20", "uxtb w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -631,15 +715,15 @@ "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0xff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "ldaddalb w20, w20, [x4]", "mvn w27, w20", "mov w21, #0xff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "add w22, w20, w21", "uxtb w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -656,14 +740,14 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "ldaddalh w20, w27, [x4]", "mov w20, #0x100", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w27, w20", "uxth w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -680,15 +764,15 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "ldaddalh w20, w20, [x4]", "mvn w27, w20", "mov w21, #0xffff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "add w22, w20, w21", "uxth w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -701,44 +785,68 @@ ] }, "lock adc dword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "ldaddal w21, w27, [x4]", - "adcs w26, w27, w20" + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "adcs w26, w27, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock adc dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "ldaddal w21, w21, [x4]", "mvn w27, w21", - "adcs w26, w21, w20" + "mrs x22, nzcv", + "eor w22, w22, #0x20000000", + "msr nzcv, x22", + "adcs w26, w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock adc qword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "ldaddal x21, x27, [x4]", - "adcs x26, x27, x20" + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "adcs x26, x27, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock adc qword [rax], -2147483647": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "ldaddal x21, x27, [x4]", - "adcs x26, x27, x20" + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "adcs x26, x27, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock adc word [rax], 1": { @@ -746,14 +854,14 @@ "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "ldaddalh w20, w27, [x4]", "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w27, w20", "uxth w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -766,23 +874,35 @@ ] }, "lock adc dword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "ldaddal w21, w27, [x4]", - "adcs w26, w27, w20" + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "adcs w26, w27, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock adc qword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "ldaddal x21, x27, [x4]", - "adcs x26, x27, x20" + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", + "adcs x26, x27, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock sbb byte [rax], 1": { @@ -790,16 +910,16 @@ "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "neg w1, w20", "ldaddalb w1, w27, [x4]", "uxtb w20, w27", "mov w21, #0x1", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -816,17 +936,17 @@ "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0xff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "neg w1, w20", "ldaddalb w1, w20, [x4]", "mvn w27, w20", "uxtb w20, w20", "mov w21, #0xff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -843,16 +963,16 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "neg w1, w20", "ldaddalh w1, w27, [x4]", "uxth w20, w27", "mov w21, #0x100", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxth w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -869,17 +989,17 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "neg w1, w20", "ldaddalh w1, w20, [x4]", "mvn w27, w20", "uxth w20, w20", "mov w21, #0xffff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxth w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -892,72 +1012,48 @@ ] }, "lock sbb dword [rax], 0x100": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "neg w1, w21", "ldaddal w1, w27, [x4]", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sbcs w26, w27, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sbcs w26, w27, w20" ] }, "lock sbb dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "neg w1, w21", "ldaddal w1, w21, [x4]", "mvn w27, w21", - "mrs x22, nzcv", - "eor w22, w22, #0x20000000", - "msr nzcv, x22", - "sbcs w26, w21, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sbcs w26, w21, w20" ] }, "lock sbb qword [rax], 0x100": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "neg x1, x21", "ldaddal x1, x27, [x4]", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sbcs x26, x27, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sbcs x26, x27, x20" ] }, "lock sbb qword [rax], -2147483647": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "neg x1, x21", "ldaddal x1, x27, [x4]", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sbcs x26, x27, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sbcs x26, x27, x20" ] }, "lock sbb word [rax], 1": { @@ -965,16 +1061,16 @@ "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "neg w1, w20", "ldaddalh w1, w27, [x4]", "uxth w20, w27", "mov w21, #0x1", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxth w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -987,156 +1083,177 @@ ] }, "lock sbb dword [rax], 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "neg w1, w21", "ldaddal w1, w27, [x4]", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sbcs w26, w27, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sbcs w26, w27, w20" ] }, "lock sbb qword [rax], 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "neg x1, x21", "ldaddal x1, x27, [x4]", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", - "sbcs x26, x27, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sbcs x26, x27, x20" ] }, "lock and byte [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclralb w1, w20, [x4]", "and w26, w20, #0x1", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and byte [rax], 0xFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "mov w20, #0xff", "mvn w1, w20", "ldclralb w1, w20, [x4]", "and w26, w20, #0xff", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and word [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn w1, w20", "ldclralh w1, w20, [x4]", "and w26, w20, #0x100", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and word [rax], 0xFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0xffff", "mvn w1, w20", "ldclralh w1, w20, [x4]", "and w26, w20, #0xffff", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and dword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn w1, w20", "ldclral w1, w20, [x4]", - "ands w26, w20, #0x100" + "ands w26, w20, #0x100", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w1, w20", "ldclral w1, w21, [x4]", - "ands w26, w21, w20" + "ands w26, w21, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and qword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn x1, x20", "ldclral x1, x20, [x4]", - "ands x26, x20, #0x100" + "ands x26, x20, #0x100", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and qword [rax], -2147483647": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "mvn x1, x20", "ldclral x1, x20, [x4]", - "ands x26, x20, #0xffffffff80000001" + "ands x26, x20, #0xffffffff80000001", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and word [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclralh w1, w20, [x4]", "and w26, w20, #0x1", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and dword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclral w1, w20, [x4]", - "ands w26, w20, #0x1" + "ands w26, w20, #0x1", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock and qword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn x1, x20", "ldclral x1, x20, [x4]", - "ands x26, x20, #0x1" + "ands x26, x20, #0x1", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock sub byte [rax], 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -1144,14 +1261,11 @@ "ldaddalb w1, w27, [x4]", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", - "sub w26, w27, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w27, #0x1 (1)" ] }, "lock sub byte [rax], 0xFF": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -1160,14 +1274,11 @@ "mvn w27, w21", "lsl w0, w21, #24", "cmp w0, w20, lsl #24", - "sub w26, w21, #0xff (255)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w21, #0xff (255)" ] }, "lock sub word [rax], 0x100": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", @@ -1175,14 +1286,11 @@ "ldaddalh w1, w27, [x4]", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", - "sub w26, w27, #0x100 (256)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w27, #0x100 (256)" ] }, "lock sub word [rax], 0xFFFF": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -1191,67 +1299,52 @@ "mvn w27, w21", "lsl w0, w21, #16", "cmp w0, w20, lsl #16", - "sub w26, w21, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w21, w20" ] }, "lock sub dword [rax], 0x100": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg w1, w20", "ldaddal w1, w27, [x4]", - "subs w26, w27, #0x100 (256)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs w26, w27, #0x100 (256)" ] }, "lock sub dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "neg w1, w20", "ldaddal w1, w21, [x4]", "mvn w27, w21", - "subs w26, w21, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs w26, w21, w20" ] }, "lock sub qword [rax], 0x100": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg x1, x20", "ldaddal x1, x27, [x4]", - "subs x26, x27, #0x100 (256)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs x26, x27, #0x100 (256)" ] }, "lock sub qword [rax], -2147483647": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "neg x1, x20", "ldaddal x1, x27, [x4]", - "subs x26, x27, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs x26, x27, x20" ] }, "lock sub word [rax], 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -1259,76 +1352,79 @@ "ldaddalh w1, w27, [x4]", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", - "sub w26, w27, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w27, #0x1 (1)" ] }, "lock sub dword [rax], 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", "ldaddal w1, w27, [x4]", - "subs w26, w27, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs w26, w27, #0x1 (1)" ] }, "lock sub qword [rax], 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg x1, x20", "ldaddal x1, x27, [x4]", - "subs x26, x27, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs x26, x27, #0x1 (1)" ] }, "lock xor byte [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoralb w20, w20, [x4]", "eor w26, w20, #0x1", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock xor byte [rax], 0xFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "mov w20, #0xff", "ldeoralb w20, w20, [x4]", "eor w26, w20, #0xff", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock xor word [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldeoralh w20, w20, [x4]", "eor w26, w20, #0x100", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock xor word [rax], 0xFFFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldeoralh w20, w20, [x4]", "eor w26, w20, #0xffff", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock xor dword [rax], 0x100": { @@ -1338,7 +1434,7 @@ "mov w20, #0x100", "ldeoral w20, w20, [x4]", "eor w26, w20, #0x100", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock xor dword [rax], 0xFFFFFFFF": { @@ -1348,7 +1444,7 @@ "mov w20, #0xffffffff", "ldeoral w20, w21, [x4]", "eor w26, w21, w20", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock xor qword [rax], 0x100": { @@ -1358,7 +1454,7 @@ "mov w20, #0x100", "ldeoral x20, x20, [x4]", "eor x26, x20, #0x100", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock xor qword [rax], -2147483647": { @@ -1368,17 +1464,20 @@ "mov x20, #0xffffffff80000001", "ldeoral x20, x20, [x4]", "eor x26, x20, #0xffffffff80000001", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock xor word [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoralh w20, w20, [x4]", "eor w26, w20, #0x1", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "lock xor dword [rax], 1": { @@ -1388,7 +1487,7 @@ "mov w20, #0x1", "ldeoral w20, w20, [x4]", "eor w26, w20, #0x1", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock xor qword [rax], 1": { @@ -1398,7 +1497,7 @@ "mov w20, #0x1", "ldeoral x20, x20, [x4]", "eor x26, x20, #0x1", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock dec byte [rax]": { @@ -1450,7 +1549,7 @@ ] }, "lock neg byte [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ "ldaxrb w1, [x4]", @@ -1459,14 +1558,11 @@ "cbnz w3, #-0xc", "mov w27, w1", "cmp wzr, w27, lsl #24", - "neg w26, w27", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "neg w26, w27" ] }, "lock neg word [rax]": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxrh w1, [x4]", @@ -1475,14 +1571,11 @@ "cbnz w3, #-0xc", "mov w27, w1", "cmp wzr, w27, lsl #16", - "neg w26, w27", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "neg w26, w27" ] }, "lock neg dword [rax]": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr w1, [x4]", @@ -1490,14 +1583,11 @@ "stlxr w3, w2, [x4]", "cbnz w3, #-0xc", "mov w27, w1", - "negs w26, w27", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "negs w26, w27" ] }, "lock neg qword [rax]": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr x1, [x4]", @@ -1505,10 +1595,7 @@ "stlxr w3, x2, [x4]", "cbnz x3, #-0xc", "mov x27, x1", - "negs x26, x27", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "negs x26, x27" ] }, "lock dec word [rax]": { diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json index 69f3bd7d8..6489603b2 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json @@ -1024,7 +1024,7 @@ ] }, "Sekiro spill block": { - "ExpectedInstructionCount": 147, + "ExpectedInstructionCount": 148, "Comment": [ "This block of code came from the settings screen when it loaded", "It was originally at RIP: 0x14232cca0 and has been deobfuscated" @@ -1297,7 +1297,8 @@ "ldr x9, [x8]", "add x8, x8, #0x8 (8)", "ldr x7, [x8]", - "add x8, x8, #0x8 (8)" + "add x8, x8, #0x8 (8)", + "cfinv" ] } } diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index 3e12429de..bf7640b04 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -13,52 +13,57 @@ }, "Instructions": { "lock add byte [rax], cl": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x00", "ExpectedArm64ASM": [ "ldaddalb w5, w20, [x4]", "eor w27, w20, w5", "lsl w0, w20, #24", "cmn w0, w5, lsl #24", - "add w26, w20, w5" + "add w26, w20, w5", + "cfinv" ] }, "lock add word [rax], cx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddalh w5, w20, [x4]", "eor w27, w20, w5", "lsl w0, w20, #16", "cmn w0, w5, lsl #16", - "add w26, w20, w5" + "add w26, w20, w5", + "cfinv" ] }, "lock add dword [rax], ecx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal w5, w20, [x4]", "eor w27, w20, w5", - "adds w26, w20, w5" + "adds w26, w20, w5", + "cfinv" ] }, "lock or byte [rax], cl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x08", "ExpectedArm64ASM": [ "ldsetalb w5, w20, [x4]", "orr w26, w20, w5", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "lock or word [rax], cx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x09", "ExpectedArm64ASM": [ "ldsetalh w5, w20, [x4]", "orr w26, w20, w5", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock or dword [rax], ecx": { @@ -67,22 +72,22 @@ "ExpectedArm64ASM": [ "ldsetal w5, w20, [x4]", "orr w26, w20, w5", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock adc byte [rax], cl": { "ExpectedInstructionCount": 15, "Comment": "0x10", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "ldaddalb w20, w20, [x4]", "eor w27, w20, w5", "uxtb w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "add w23, w20, w22", "uxtb w26, w23", "cmp w26, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #24", "rmif x22, #63, #nzCv", "eor w21, w20, w21", @@ -95,15 +100,15 @@ "ExpectedInstructionCount": 15, "Comment": "0x11", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "ldaddalh w20, w20, [x4]", "eor w27, w20, w5", "uxth w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "add w23, w20, w22", "uxth w26, w23", "cmp w26, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #16", "rmif x22, #63, #nzCv", "eor w21, w20, w21", @@ -113,30 +118,32 @@ ] }, "lock adc dword [rax], ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "0x11", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "ldaddal w20, w20, [x4]", "eor w27, w20, w5", - "adcs w26, w20, w5" + "cfinv", + "adcs w26, w20, w5", + "cfinv" ] }, "lock sbb byte [rax], cl": { "ExpectedInstructionCount": 17, "Comment": "0x18", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "neg w1, w20", "ldaddalb w1, w20, [x4]", "eor w27, w20, w5", "uxtb w20, w20", "uxtb w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxtb w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #24", "rmif x22, #63, #nzCv", "eor w21, w20, w21", @@ -149,17 +156,17 @@ "ExpectedInstructionCount": 17, "Comment": "0x19", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "neg w1, w20", "ldaddalh w1, w20, [x4]", "eor w27, w20, w5", "uxth w20, w20", "uxth w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxth w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #16", "rmif x22, #63, #nzCv", "eor w21, w20, w21", @@ -169,49 +176,50 @@ ] }, "lock sbb dword [rax], ecx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "0x19", "ExpectedArm64ASM": [ - "adc w20, wzr, w5", + "cinc w20, w5, lo", "neg w1, w20", "ldaddal w1, w20, [x4]", "eor w27, w20, w5", - "cfinv", - "sbcs w26, w20, w5", - "cfinv" + "sbcs w26, w20, w5" ] }, "lock and byte [rax], cl": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x20", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclralb w1, w20, [x4]", "and w26, w20, w5", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "lock and word [rax], cx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x21", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclralh w1, w20, [x4]", "and w26, w20, w5", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock and dword [rax], ecx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x21", "ExpectedArm64ASM": [ "mvn w1, w5", "ldclral w1, w20, [x4]", - "ands w26, w20, w5" + "ands w26, w20, w5", + "cfinv" ] }, "lock sub byte [rax], cl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x28", "ExpectedArm64ASM": [ "neg w1, w5", @@ -219,12 +227,11 @@ "eor w27, w20, w5", "lsl w0, w20, #24", "cmp w0, w5, lsl #24", - "sub w26, w20, w5", - "cfinv" + "sub w26, w20, w5" ] }, "lock sub word [rax], cx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x28", "ExpectedArm64ASM": [ "neg w1, w5", @@ -232,37 +239,37 @@ "eor w27, w20, w5", "lsl w0, w20, #16", "cmp w0, w5, lsl #16", - "sub w26, w20, w5", - "cfinv" + "sub w26, w20, w5" ] }, "lock sub dword [rax], ecx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x29", "ExpectedArm64ASM": [ "neg w1, w5", "ldaddal w1, w20, [x4]", "eor w27, w20, w5", - "subs w26, w20, w5", - "cfinv" + "subs w26, w20, w5" ] }, "lock xor byte [rax], cl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x30", "ExpectedArm64ASM": [ "ldeoralb w5, w20, [x4]", "eor w26, w20, w5", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "lock xor word [rax], cx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x31", "ExpectedArm64ASM": [ "ldeoralh w5, w20, [x4]", "eor w26, w20, w5", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock xor dword [rax], ecx": { @@ -271,20 +278,21 @@ "ExpectedArm64ASM": [ "ldeoral w5, w20, [x4]", "eor w26, w20, w5", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock add qword [rax], rcx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x01", "ExpectedArm64ASM": [ "ldaddal x5, x20, [x4]", "eor w27, w20, w5", - "adds x26, x20, x5" + "adds x26, x20, x5", + "cfinv" ] }, "xadd byte [rax], bl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -293,11 +301,12 @@ "lsl w0, w21, #24", "cmn w0, w20, lsl #24", "add w26, w21, w20", - "bfxil x7, x21, #0, #8" + "bfxil x7, x21, #0, #8", + "cfinv" ] }, "xadd word [rax], bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -306,42 +315,46 @@ "lsl w0, w21, #16", "cmn w0, w20, lsl #16", "add w26, w21, w20", - "bfxil x7, x21, #0, #16" + "bfxil x7, x21, #0, #16", + "cfinv" ] }, "xadd dword [rax], ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", "eor w27, w7, w20", - "adds w26, w7, w20" + "adds w26, w7, w20", + "cfinv" ] }, "xadd qword [rax], rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "ldaddal x7, x20, [x4]", "eor w27, w20, w7", "adds x26, x20, x7", + "cfinv", "mov x7, x20" ] }, "lock add byte [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalb w20, w27, [x4]", "lsl w0, w27, #24", "cmn w0, w20, lsl #24", - "add w26, w27, #0x1 (1)" + "add w26, w27, #0x1 (1)", + "cfinv" ] }, "lock add byte [rax], 0xFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -349,22 +362,24 @@ "mvn w27, w21", "lsl w0, w21, #24", "cmn w0, w20, lsl #24", - "add w26, w21, #0xff (255)" + "add w26, w21, #0xff (255)", + "cfinv" ] }, "lock add word [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddalh w20, w27, [x4]", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", - "add w26, w27, #0x100 (256)" + "add w26, w27, #0x100 (256)", + "cfinv" ] }, "lock add word [rax], 0xFFFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -372,113 +387,125 @@ "mvn w27, w21", "lsl w0, w21, #16", "cmn w0, w20, lsl #16", - "add w26, w21, w20" + "add w26, w21, w20", + "cfinv" ] }, "lock add dword [rax], 0x100": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddal w20, w27, [x4]", - "adds w26, w27, #0x100 (256)" + "adds w26, w27, #0x100 (256)", + "cfinv" ] }, "lock add dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldaddal w20, w21, [x4]", "mvn w27, w21", - "adds w26, w21, w20" + "adds w26, w21, w20", + "cfinv" ] }, "lock add qword [rax], 0x100": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldaddal x20, x27, [x4]", - "adds x26, x27, #0x100 (256)" + "adds x26, x27, #0x100 (256)", + "cfinv" ] }, "lock add qword [rax], -2147483647": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "ldaddal x20, x27, [x4]", - "adds x26, x27, x20" + "adds x26, x27, x20", + "cfinv" ] }, "lock add word [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalh w20, w27, [x4]", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", - "add w26, w27, #0x1 (1)" + "add w26, w27, #0x1 (1)", + "cfinv" ] }, "lock add dword [rax], 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal w20, w27, [x4]", - "adds w26, w27, #0x1 (1)" + "adds w26, w27, #0x1 (1)", + "cfinv" ] }, "lock add qword [rax], 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal x20, x27, [x4]", - "adds x26, x27, #0x1 (1)" + "adds x26, x27, #0x1 (1)", + "cfinv" ] }, "lock or byte [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetalb w20, w20, [x4]", "orr w26, w20, #0x1", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "lock or byte [rax], 0xFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "mov w20, #0xff", "ldsetalb w20, w20, [x4]", "orr w26, w20, #0xff", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "lock or word [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldsetalh w20, w20, [x4]", "orr w26, w20, #0x100", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock or word [rax], 0xFFFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldsetalh w20, w20, [x4]", "orr w26, w20, #0xffff", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock or dword [rax], 0x100": { @@ -488,7 +515,7 @@ "mov w20, #0x100", "ldsetal w20, w20, [x4]", "orr w26, w20, #0x100", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock or dword [rax], 0xFFFFFFFF": { @@ -498,7 +525,7 @@ "mov w20, #0xffffffff", "ldsetal w20, w21, [x4]", "orr w26, w21, w20", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock or qword [rax], 0x100": { @@ -508,7 +535,7 @@ "mov w20, #0x100", "ldsetal x20, x20, [x4]", "orr x26, x20, #0x100", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock or qword [rax], -2147483647": { @@ -518,17 +545,18 @@ "mov x20, #0xffffffff80000001", "ldsetal x20, x20, [x4]", "orr x26, x20, #0xffffffff80000001", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock or word [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldsetalh w20, w20, [x4]", "orr w26, w20, #0x1", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock or dword [rax], 1": { @@ -538,7 +566,7 @@ "mov w20, #0x1", "ldsetal w20, w20, [x4]", "orr w26, w20, #0x1", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock or qword [rax], 1": { @@ -548,7 +576,7 @@ "mov w20, #0x1", "ldsetal x20, x20, [x4]", "orr x26, x20, #0x1", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock adc byte [rax], 1": { @@ -556,14 +584,14 @@ "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "ldaddalb w20, w27, [x4]", "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w27, w20", "uxtb w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", "eor w20, w27, #0x1", @@ -577,15 +605,15 @@ "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0xff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "ldaddalb w20, w20, [x4]", "mvn w27, w20", "mov w21, #0xff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "add w22, w20, w21", "uxtb w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", "eor w21, w20, #0xff", @@ -599,14 +627,14 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "ldaddalh w20, w27, [x4]", "mov w20, #0x100", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w27, w20", "uxth w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", "eor w20, w27, #0x100", @@ -620,15 +648,15 @@ "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "ldaddalh w20, w20, [x4]", "mvn w27, w20", "mov w21, #0xffff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "add w22, w20, w21", "uxth w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "rmif x21, #63, #nzCv", "eor w21, w20, #0xffff", @@ -638,44 +666,52 @@ ] }, "lock adc dword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "ldaddal w21, w27, [x4]", - "adcs w26, w27, w20" + "cfinv", + "adcs w26, w27, w20", + "cfinv" ] }, "lock adc dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "ldaddal w21, w21, [x4]", "mvn w27, w21", - "adcs w26, w21, w20" + "cfinv", + "adcs w26, w21, w20", + "cfinv" ] }, "lock adc qword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "ldaddal x21, x27, [x4]", - "adcs x26, x27, x20" + "cfinv", + "adcs x26, x27, x20", + "cfinv" ] }, "lock adc qword [rax], -2147483647": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "ldaddal x21, x27, [x4]", - "adcs x26, x27, x20" + "cfinv", + "adcs x26, x27, x20", + "cfinv" ] }, "lock adc word [rax], 1": { @@ -683,14 +719,14 @@ "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "ldaddalh w20, w27, [x4]", "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w27, w20", "uxth w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", "eor w20, w27, #0x1", @@ -700,23 +736,27 @@ ] }, "lock adc dword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "ldaddal w21, w27, [x4]", - "adcs w26, w27, w20" + "cfinv", + "adcs w26, w27, w20", + "cfinv" ] }, "lock adc qword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "ldaddal x21, x27, [x4]", - "adcs x26, x27, x20" + "cfinv", + "adcs x26, x27, x20", + "cfinv" ] }, "lock sbb byte [rax], 1": { @@ -724,16 +764,16 @@ "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "neg w1, w20", "ldaddalb w1, w27, [x4]", "uxtb w20, w27", "mov w21, #0x1", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", "eor w21, w20, #0x1", @@ -747,17 +787,17 @@ "Comment": "GROUP1 0x80 /3", "ExpectedArm64ASM": [ "mov w20, #0xff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "neg w1, w20", "ldaddalb w1, w20, [x4]", "mvn w27, w20", "uxtb w20, w20", "mov w21, #0xff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", "eor w21, w20, #0xff", @@ -771,16 +811,16 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "neg w1, w20", "ldaddalh w1, w27, [x4]", "uxth w20, w27", "mov w21, #0x100", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxth w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "rmif x21, #63, #nzCv", "eor w21, w20, #0x100", @@ -794,17 +834,17 @@ "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "neg w1, w20", "ldaddalh w1, w20, [x4]", "mvn w27, w20", "uxth w20, w20", "mov w21, #0xffff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxth w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "rmif x21, #63, #nzCv", "eor w21, w20, #0xffff", @@ -814,56 +854,48 @@ ] }, "lock sbb dword [rax], 0x100": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "neg w1, w21", "ldaddal w1, w27, [x4]", - "cfinv", - "sbcs w26, w27, w20", - "cfinv" + "sbcs w26, w27, w20" ] }, "lock sbb dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "neg w1, w21", "ldaddal w1, w21, [x4]", "mvn w27, w21", - "cfinv", - "sbcs w26, w21, w20", - "cfinv" + "sbcs w26, w21, w20" ] }, "lock sbb qword [rax], 0x100": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "neg x1, x21", "ldaddal x1, x27, [x4]", - "cfinv", - "sbcs x26, x27, x20", - "cfinv" + "sbcs x26, x27, x20" ] }, "lock sbb qword [rax], -2147483647": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "neg x1, x21", "ldaddal x1, x27, [x4]", - "cfinv", - "sbcs x26, x27, x20", - "cfinv" + "sbcs x26, x27, x20" ] }, "lock sbb word [rax], 1": { @@ -871,16 +903,16 @@ "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "neg w1, w20", "ldaddalh w1, w27, [x4]", "uxth w20, w27", "mov w21, #0x1", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxth w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "rmif x21, #63, #nzCv", "eor w21, w20, #0x1", @@ -890,148 +922,155 @@ ] }, "lock sbb dword [rax], 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "neg w1, w21", "ldaddal w1, w27, [x4]", - "cfinv", - "sbcs w26, w27, w20", - "cfinv" + "sbcs w26, w27, w20" ] }, "lock sbb qword [rax], 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc x21, xzr, x20", + "cinc x21, x20, lo", "neg x1, x21", "ldaddal x1, x27, [x4]", - "cfinv", - "sbcs x26, x27, x20", - "cfinv" + "sbcs x26, x27, x20" ] }, "lock and byte [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclralb w1, w20, [x4]", "and w26, w20, #0x1", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "lock and byte [rax], 0xFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "mov w20, #0xff", "mvn w1, w20", "ldclralb w1, w20, [x4]", "and w26, w20, #0xff", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "lock and word [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn w1, w20", "ldclralh w1, w20, [x4]", "and w26, w20, #0x100", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock and word [rax], 0xFFFF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0xffff", "mvn w1, w20", "ldclralh w1, w20, [x4]", "and w26, w20, #0xffff", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock and dword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn w1, w20", "ldclral w1, w20, [x4]", - "ands w26, w20, #0x100" + "ands w26, w20, #0x100", + "cfinv" ] }, "lock and dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w1, w20", "ldclral w1, w21, [x4]", - "ands w26, w21, w20" + "ands w26, w21, w20", + "cfinv" ] }, "lock and qword [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov w20, #0x100", "mvn x1, x20", "ldclral x1, x20, [x4]", - "ands x26, x20, #0x100" + "ands x26, x20, #0x100", + "cfinv" ] }, "lock and qword [rax], -2147483647": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "mvn x1, x20", "ldclral x1, x20, [x4]", - "ands x26, x20, #0xffffffff80000001" + "ands x26, x20, #0xffffffff80000001", + "cfinv" ] }, "lock and word [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclralh w1, w20, [x4]", "and w26, w20, #0x1", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock and dword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn w1, w20", "ldclral w1, w20, [x4]", - "ands w26, w20, #0x1" + "ands w26, w20, #0x1", + "cfinv" ] }, "lock and qword [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0x1", "mvn x1, x20", "ldclral x1, x20, [x4]", - "ands x26, x20, #0x1" + "ands x26, x20, #0x1", + "cfinv" ] }, "lock sub byte [rax], 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -1039,12 +1078,11 @@ "ldaddalb w1, w27, [x4]", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", - "sub w26, w27, #0x1 (1)", - "cfinv" + "sub w26, w27, #0x1 (1)" ] }, "lock sub byte [rax], 0xFF": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -1053,12 +1091,11 @@ "mvn w27, w21", "lsl w0, w21, #24", "cmp w0, w20, lsl #24", - "sub w26, w21, #0xff (255)", - "cfinv" + "sub w26, w21, #0xff (255)" ] }, "lock sub word [rax], 0x100": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", @@ -1066,12 +1103,11 @@ "ldaddalh w1, w27, [x4]", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", - "sub w26, w27, #0x100 (256)", - "cfinv" + "sub w26, w27, #0x100 (256)" ] }, "lock sub word [rax], 0xFFFF": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -1080,57 +1116,52 @@ "mvn w27, w21", "lsl w0, w21, #16", "cmp w0, w20, lsl #16", - "sub w26, w21, w20", - "cfinv" + "sub w26, w21, w20" ] }, "lock sub dword [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg w1, w20", "ldaddal w1, w27, [x4]", - "subs w26, w27, #0x100 (256)", - "cfinv" + "subs w26, w27, #0x100 (256)" ] }, "lock sub dword [rax], 0xFFFFFFFF": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "neg w1, w20", "ldaddal w1, w21, [x4]", "mvn w27, w21", - "subs w26, w21, w20", - "cfinv" + "subs w26, w21, w20" ] }, "lock sub qword [rax], 0x100": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0x100", "neg x1, x20", "ldaddal x1, x27, [x4]", - "subs x26, x27, #0x100 (256)", - "cfinv" + "subs x26, x27, #0x100 (256)" ] }, "lock sub qword [rax], -2147483647": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov x20, #0xffffffff80000001", "neg x1, x20", "ldaddal x1, x27, [x4]", - "subs x26, x27, x20", - "cfinv" + "subs x26, x27, x20" ] }, "lock sub word [rax], 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -1138,70 +1169,71 @@ "ldaddalh w1, w27, [x4]", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", - "sub w26, w27, #0x1 (1)", - "cfinv" + "sub w26, w27, #0x1 (1)" ] }, "lock sub dword [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg w1, w20", "ldaddal w1, w27, [x4]", - "subs w26, w27, #0x1 (1)", - "cfinv" + "subs w26, w27, #0x1 (1)" ] }, "lock sub qword [rax], 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "neg x1, x20", "ldaddal x1, x27, [x4]", - "subs x26, x27, #0x1 (1)", - "cfinv" + "subs x26, x27, #0x1 (1)" ] }, "lock xor byte [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoralb w20, w20, [x4]", "eor w26, w20, #0x1", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "lock xor byte [rax], 0xFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "mov w20, #0xff", "ldeoralb w20, w20, [x4]", "eor w26, w20, #0xff", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "lock xor word [rax], 0x100": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0x100", "ldeoralh w20, w20, [x4]", "eor w26, w20, #0x100", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock xor word [rax], 0xFFFF": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "mov w20, #0xffff", "ldeoralh w20, w20, [x4]", "eor w26, w20, #0xffff", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock xor dword [rax], 0x100": { @@ -1211,7 +1243,7 @@ "mov w20, #0x100", "ldeoral w20, w20, [x4]", "eor w26, w20, #0x100", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock xor dword [rax], 0xFFFFFFFF": { @@ -1221,7 +1253,7 @@ "mov w20, #0xffffffff", "ldeoral w20, w21, [x4]", "eor w26, w21, w20", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock xor qword [rax], 0x100": { @@ -1231,7 +1263,7 @@ "mov w20, #0x100", "ldeoral x20, x20, [x4]", "eor x26, x20, #0x100", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock xor qword [rax], -2147483647": { @@ -1241,17 +1273,18 @@ "mov x20, #0xffffffff80000001", "ldeoral x20, x20, [x4]", "eor x26, x20, #0xffffffff80000001", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock xor word [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "ldeoralh w20, w20, [x4]", "eor w26, w20, #0x1", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "lock xor dword [rax], 1": { @@ -1261,7 +1294,7 @@ "mov w20, #0x1", "ldeoral w20, w20, [x4]", "eor w26, w20, #0x1", - "tst w26, w26" + "cmp w26, #0x0 (0)" ] }, "lock xor qword [rax], 1": { @@ -1271,7 +1304,7 @@ "mov w20, #0x1", "ldeoral x20, x20, [x4]", "eor x26, x20, #0x1", - "tst x26, x26" + "cmp x26, #0x0 (0)" ] }, "lock dec byte [rax]": { @@ -1319,7 +1352,7 @@ ] }, "lock neg byte [rax]": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ "ldaxrb w1, [x4]", @@ -1328,12 +1361,11 @@ "cbnz w3, #-0xc", "mov w27, w1", "cmp wzr, w27, lsl #24", - "neg w26, w27", - "cfinv" + "neg w26, w27" ] }, "lock neg word [rax]": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxrh w1, [x4]", @@ -1342,12 +1374,11 @@ "cbnz w3, #-0xc", "mov w27, w1", "cmp wzr, w27, lsl #16", - "neg w26, w27", - "cfinv" + "neg w26, w27" ] }, "lock neg dword [rax]": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr w1, [x4]", @@ -1355,12 +1386,11 @@ "stlxr w3, w2, [x4]", "cbnz w3, #-0xc", "mov w27, w1", - "negs w26, w27", - "cfinv" + "negs w26, w27" ] }, "lock neg qword [rax]": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf7 /3", "ExpectedArm64ASM": [ "ldaxr x1, [x4]", @@ -1368,8 +1398,7 @@ "stlxr w3, x2, [x4]", "cbnz x3, #-0xc", "mov x27, x1", - "negs x26, x27", - "cfinv" + "negs x26, x27" ] }, "lock dec word [rax]": { diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index 108529a49..81ffbf6ea 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -12,7 +12,7 @@ }, "Instructions": { "Chained add": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "x86Insts": [ "add rax, rbx", "adc rcx, rcx" @@ -21,27 +21,25 @@ "adds x4, x4, x7", "mov w27, #0x0", "adcs x26, x5, x5", + "cfinv", "mov x5, x26" ] }, "Chained sub": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "x86Insts": [ "sub rax, rbx", "sbb rcx, rdx" ], "ExpectedArm64ASM": [ "subs x4, x4, x7", - "cfinv", "eor w27, w5, w6", - "cfinv", "sbcs x26, x5, x6", - "cfinv", "mov x5, x26" ] }, "Inverted add": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "x86Insts": [ "add rax, rbx", "adc rcx, rdx", @@ -51,12 +49,11 @@ "adds x4, x4, x7", "eor w27, w5, w6", "adcs x26, x5, x6", - "mov x5, x26", - "cfinv" + "mov x5, x26" ] }, "Inverted sub": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "x86Insts": [ "sub rax, rbx", "sbb rcx, rcx", @@ -64,17 +61,14 @@ ], "ExpectedArm64ASM": [ "subs x4, x4, x7", - "cfinv", "mov w27, #0x0", - "cfinv", "sbcs x26, x5, x5", - "cfinv", "mov x5, x26", "cfinv" ] }, "ADC dead": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "x86Insts": [ "add rax, rbx", "adc rcx, rcx", @@ -83,7 +77,8 @@ "ExpectedArm64ASM": [ "adds x4, x4, x7", "adc x5, x5, x5", - "ands x26, x5, x5" + "ands x26, x5, x5", + "cfinv" ] }, "INC consumed": { @@ -94,7 +89,7 @@ ], "ExpectedArm64ASM": [ "adds x4, x4, x7", - "cset w20, hs", + "cset w20, lo", "adds x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x27, x4", @@ -102,7 +97,7 @@ ] }, "INC dead": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "x86Insts": [ "add rax, rbx", "inc rax", @@ -111,18 +106,18 @@ "ExpectedArm64ASM": [ "add x4, x4, x7", "add x4, x4, #0x1 (1)", - "ands x26, x4, x6" + "ands x26, x4, x6", + "cfinv" ] }, "DEC consumed": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "x86Insts": [ "sub rax, rbx", "dec rax" ], "ExpectedArm64ASM": [ "subs x4, x4, x7", - "cfinv", "cset w20, hs", "subs x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", @@ -131,7 +126,7 @@ ] }, "DEC dead": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "x86Insts": [ "sub rax, rbx", "dec rax", @@ -140,11 +135,12 @@ "ExpectedArm64ASM": [ "sub x4, x4, x7", "sub x4, x4, #0x1 (1)", - "ands x26, x4, x5" + "ands x26, x4, x5", + "cfinv" ] }, "8-bit DEC consumed": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 11, "x86Insts": [ "sub al, ah", "dec al" @@ -154,7 +150,6 @@ "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w20, w4, w20", - "cfinv", "bfxil x4, x20, #0, #8", "uxtb w27, w4", "sub w26, w27, #0x1 (1)", @@ -165,7 +160,7 @@ ] }, "8-bit DEC dead": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "x86Insts": [ "sub al, ah", "dec al", @@ -179,46 +174,50 @@ "sub w20, w20, #0x1 (1)", "bfxil x4, x20, #0, #8", "mov x26, x4", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "Variable shift dead": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "x86Insts": [ "sar rax, cl", "test rax, rdx" ], "ExpectedArm64ASM": [ "asr x4, x4, x5", - "ands x26, x4, x6" + "ands x26, x4, x6", + "cfinv" ] }, "Variable rotate-through-carry dead": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 17, "x86Insts": [ "rcr rax, cl", "test rax, rdx" ], "ExpectedArm64ASM": [ "and x20, x5, #0x3f", - "cbz x20, #+0x34", + "cbz x20, #+0x38", "lsr x20, x4, x5", - "cset w21, hs", + "cset w21, lo", "neg x22, x5", "lsl x23, x4, x22", "orr x20, x20, x23, lsl #1", "sub x23, x5, #0x1 (1)", "lsr x23, x4, x23", + "eor x23, x23, #0x1", "rmif x23, #63, #nzCv", "lsl x21, x21, x22", "orr x4, x20, x21", "eor x20, x4, x4, lsr #1", "rmif x20, #62, #nzcV", - "ands x26, x4, x6" + "ands x26, x4, x6", + "cfinv" ] }, "Partial NZCV select (cmp)": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "x86Insts": [ "cmp rax, rbx", "setz cl", @@ -229,11 +228,12 @@ "cset x21, eq", "bfxil x5, x21, #0, #8", "mov x26, x5", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "Partial NZCV select (add)": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "x86Insts": [ "add rax, rbx", "setz cl", @@ -244,11 +244,12 @@ "cset x20, eq", "bfxil x5, x20, #0, #8", "mov x26, x5", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "AND use only ZF": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "x86Insts": [ "and eax, ebx", "setz cl", @@ -259,11 +260,12 @@ "cset x20, eq", "bfxil x5, x20, #0, #8", "mov x26, x5", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "AND use only PF": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "x86Insts": [ "and eax, ebx", "setp cl", @@ -278,11 +280,12 @@ "and x20, x20, #0x1", "bfxil x5, x20, #0, #8", "mov x26, x5", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "Dead cmpxchg flags": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 23, "x86Insts": [ "cmpxchg8b [rbp]", "test rax, rax" @@ -309,7 +312,8 @@ "mov w21, w22", "csel x4, x21, x4, ne", "csel x6, x20, x6, ne", - "ands x26, x4, x4" + "ands x26, x4, x4", + "cfinv" ] } } diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json index b81f7e422..57519e343 100644 --- a/unittests/InstructionCountCI/FlagM/H0F38.json +++ b/unittests/InstructionCountCI/FlagM/H0F38.json @@ -27,18 +27,18 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, "adcx eax, ebx": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": [ "0x66 0x0f 0x38 0xf6" ], "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "mov w21, w7", "mov w22, w4", "add w23, w21, w20", @@ -50,17 +50,18 @@ "cset x21, ls", "cmp x20, #0x1 (1)", "csel x20, x21, x23, eq", + "eor x20, x20, #0x1", "msr nzcv, x22", "rmif x20, #63, #nzCv" ] }, "adcx rax, rbx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": [ "0x66 REX.W 0x0f 0x38 0xf6" ], "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "add x21, x7, x20", "add x4, x4, x21", "mrs x21, nzcv", @@ -70,6 +71,7 @@ "cset x23, ls", "cmp x20, #0x1 (1)", "csel x20, x23, x22, eq", + "eor x20, x20, #0x1", "msr nzcv, x21", "rmif x20, #63, #nzCv" ] diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index dbcda6ca4..c38a3a74a 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -13,7 +13,7 @@ }, "Instructions": { "The Witcher 3": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "x86Insts": [ "mov eax, 0x1", "lock xadd qword [rcx], rax", @@ -32,11 +32,12 @@ "lsl x6, x6, #6", "eor w27, w6, w5", "adds x26, x6, x5", + "cfinv", "mov x6, x26" ] }, "FMOD scalar loop": { - "ExpectedInstructionCount": 65, + "ExpectedInstructionCount": 64, "x86Insts": [ "mov esi, ecx", "mov rdx, rbp", @@ -140,13 +141,12 @@ "mov v18.s[0], v0.s[0]", "stur s18, [x4, #-4]", "subs w26, w10, #0x1 (1)", - "cfinv", "mov x27, x10", "mov x10, x26" ] }, "Scalar vector add loop": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": [ "Saw this in bytemark" ], @@ -163,12 +163,11 @@ "str q16, [x16, x4, sxtx]", "add x4, x4, #0x10 (16)", "eor w27, w10, w4", - "subs x26, x10, x4", - "cfinv" + "subs x26, x10, x4" ] }, "bytemark data xor loop": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "Saw this in bytemark" ], @@ -195,12 +194,11 @@ "eor x20, x20, x19", "str x20, [x7, x6, sxtx #3]", "eor w27, w11, w4", - "subs x26, x11, x4", - "cfinv" + "subs x26, x11, x4" ] }, "bytemark num sort": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": [ "Saw this in bytemark" ], @@ -216,12 +214,11 @@ "orr x15, x15, #0x1", "ldr x20, [x10, x15, sxtx #3]", "eor w27, w17, w20", - "subs x26, x17, x20", - "cfinv" + "subs x26, x17, x20" ] }, "pcmpistri xmm0, xmm1, 0_0_00_11_01b": { - "ExpectedInstructionCount": 40, + "ExpectedInstructionCount": 41, "Comment": [ "A Hat In Time spends at least 5% CPU time in this instruction", "Comes from vcruntime140.dll wcsstr" @@ -266,6 +263,7 @@ "cmp x21, #0x0 (0)", "csel x5, x22, x23, eq", "mov w26, #0x1", + "eor w20, w20, #0x20000000", "msr nzcv, x20" ] } diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json index 95dc691ab..123d8fcc6 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json @@ -13,7 +13,7 @@ }, "Instructions": { "Sonic Mania movie player": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 15, "Comment": "Used to be hottest block in Sonic Mania", "x86Insts": [ "movzx edx, byte [esi+ecx]", @@ -42,12 +42,11 @@ "str w20, [x4]", "add w4, w4, #0x4 (4)", "eor w27, w10, w7", - "subs w26, w10, w7", - "cfinv" + "subs w26, w10, w7" ] }, "wine mscrt.dll memmove": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 13, "Comment": "Hot in Sonic Mania", "x86Insts": [ "movdqu xmm0, [esi]", @@ -76,12 +75,11 @@ "add w11, w11, #0x40 (64)", "sub w5, w5, #0x40 (64)", "subs w26, w5, #0x40 (64)", - "cfinv", "mov x27, x5" ] }, "dxvk hotblock from MGRR": { - "ExpectedInstructionCount": 38, + "ExpectedInstructionCount": 39, "Comment": [ "Hottest block in Metal Gear Rising: Revengeance render thread" ], @@ -139,11 +137,12 @@ "rmif x0, #0, #NzCV", "mov w22, w21", "csel x4, x20, x4, ne", - "csel x6, x22, x6, ne" + "csel x6, x22, x6, ne", + "cfinv" ] }, "Psychonauts matrix swizzle": { - "ExpectedInstructionCount": 165, + "ExpectedInstructionCount": 164, "Comment": [ "Hottest block in Windows Psychonauts", "Doing a 4x4 32-bit float matrix swizzle", @@ -258,7 +257,6 @@ "str w9, [x8, #-4]!", "mov x9, x8", "subs w26, w8, #0x44 (68)", - "cfinv", "mov x27, x8", "mov x8, x26", "mov x20, #0xffffffffffffffbc", diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json index 69349b31b..2e22702b1 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json @@ -13,7 +13,7 @@ }, "Instructions": { "FMOD scalar loop": { - "ExpectedInstructionCount": 49, + "ExpectedInstructionCount": 48, "x86Insts": [ "mov esi, ecx", "mov rdx, rbp", @@ -101,7 +101,6 @@ "fadd s18, s18, s2", "stur s18, [x4, #-4]", "subs w26, w10, #0x1 (1)", - "cfinv", "mov x27, x10", "mov x10, x26" ] diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 6a47753c4..37f41c46d 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -13,47 +13,51 @@ }, "Instructions": { "add bl, cl": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x00", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #24", "cmn w0, w5, lsl #24", "add w26, w7, w5", - "bfxil x7, x26, #0, #8" + "bfxil x7, x26, #0, #8", + "cfinv" ] }, "add bx, cx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x01", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #16", "cmn w0, w5, lsl #16", "add w26, w7, w5", - "bfxil x7, x26, #0, #16" + "bfxil x7, x26, #0, #16", + "cfinv" ] }, "add ebx, ecx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x01", "ExpectedArm64ASM": [ "eor w27, w7, w5", "adds w26, w7, w5", + "cfinv", "mov x7, x26" ] }, "add rbx, rcx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x01", "ExpectedArm64ASM": [ "eor w27, w7, w5", "adds x26, x7, x5", + "cfinv", "mov x7, x26" ] }, "db 0x02, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": [ "0x02", "add bl, cl but modrm.rm as source" @@ -63,11 +67,12 @@ "lsl w0, w5, #24", "cmn w0, w7, lsl #24", "add w26, w5, w7", - "bfxil x5, x26, #0, #8" + "bfxil x5, x26, #0, #8", + "cfinv" ] }, "db 0x66, 0x03, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": [ "0x03", "add bx, cx but modrm.rm as source" @@ -77,11 +82,12 @@ "lsl w0, w5, #16", "cmn w0, w7, lsl #16", "add w26, w5, w7", - "bfxil x5, x26, #0, #16" + "bfxil x5, x26, #0, #16", + "cfinv" ] }, "db 0x03, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": [ "0x03", "add ebx, ecx but modrm.rm as source" @@ -89,11 +95,12 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "adds w26, w5, w7", + "cfinv", "mov x5, x26" ] }, "db 0x48, 0x03, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": [ "0x03", "add rbx, rcx but modrm.rm as source" @@ -101,11 +108,12 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "adds x26, x5, x7", + "cfinv", "mov x5, x26" ] }, "add al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x04", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -114,12 +122,13 @@ "add w26, w4, #0x1 (1)", "mov x20, x4", "bfxil x20, x26, #0, #8", + "cfinv", "mov x27, x4", "mov x4, x20" ] }, "add ax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -128,30 +137,33 @@ "add w26, w4, #0x1 (1)", "mov x20, x4", "bfxil x20, x26, #0, #16", + "cfinv", "mov x27, x4", "mov x4, x20" ] }, "add eax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ "adds w26, w4, #0x1 (1)", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "add rax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ "adds x26, x4, #0x1 (1)", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "add al, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "0x04", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -159,11 +171,12 @@ "lsl w0, w4, #24", "cmn w0, w20, lsl #24", "add w26, w4, #0xff (255)", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "add ax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -171,54 +184,60 @@ "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, w20", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "add eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", "adds w26, w4, w20", + "cfinv", "mov x4, x26" ] }, "add rax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x05", "ExpectedArm64ASM": [ "mvn w27, w4", "subs x26, x4, #0x1 (1)", + "cfinv", "mov x4, x26" ] }, "or bl, bh": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "", "ExpectedArm64ASM": [ "lsr w20, w7, #8", "orr w26, w7, w20", "cmn wzr, w26, lsl #24", - "bfxil x7, x26, #0, #8" + "bfxil x7, x26, #0, #8", + "cfinv" ] }, "or bl, cl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x08", "ExpectedArm64ASM": [ "orr w26, w7, w5", "cmn wzr, w26, lsl #24", - "bfxil x7, x26, #0, #8" + "bfxil x7, x26, #0, #8", + "cfinv" ] }, "or bx, cx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x09", "ExpectedArm64ASM": [ "orr w26, w7, w5", "cmn wzr, w26, lsl #16", - "bfxil x7, x26, #0, #16" + "bfxil x7, x26, #0, #16", + "cfinv" ] }, "or ebx, ecx": { @@ -226,7 +245,7 @@ "Comment": "0x09", "ExpectedArm64ASM": [ "orr w26, w7, w5", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x7, x26" ] }, @@ -235,12 +254,12 @@ "Comment": "0x09", "ExpectedArm64ASM": [ "orr x26, x7, x5", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x7, x26" ] }, "db 0x0A, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": [ "0x0A", "or bl, cl but modrm.rm as source" @@ -248,11 +267,12 @@ "ExpectedArm64ASM": [ "orr w26, w5, w7", "cmn wzr, w26, lsl #24", - "bfxil x5, x26, #0, #8" + "bfxil x5, x26, #0, #8", + "cfinv" ] }, "db 0x66, 0x0B, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": [ "0x0B", "or bx, cx but modrm.rm as source" @@ -260,7 +280,8 @@ "ExpectedArm64ASM": [ "orr w26, w5, w7", "cmn wzr, w26, lsl #16", - "bfxil x5, x26, #0, #16" + "bfxil x5, x26, #0, #16", + "cfinv" ] }, "db 0x0B, 0xcb": { @@ -271,7 +292,7 @@ ], "ExpectedArm64ASM": [ "orr w26, w5, w7", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x5, x26" ] }, @@ -283,26 +304,28 @@ ], "ExpectedArm64ASM": [ "orr x26, x5, x7", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x5, x26" ] }, "or al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x0C", "ExpectedArm64ASM": [ "orr w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "or ax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x0D", "ExpectedArm64ASM": [ "orr w26, w4, #0x1", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "or eax, 1": { @@ -310,7 +333,7 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "orr w26, w4, #0x1", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -319,26 +342,28 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "orr x26, x4, #0x1", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "or al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x0C", "ExpectedArm64ASM": [ "orr w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "or ax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x0D", "ExpectedArm64ASM": [ "orr w26, w4, #0xffff", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "or eax, -1": { @@ -347,7 +372,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "orr w26, w4, w20", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -357,7 +382,7 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "orr x26, x4, x20", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, @@ -367,11 +392,11 @@ "ExpectedArm64ASM": [ "eor w27, w7, w5", "uxtb w20, w5", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "add w22, w7, w21", "uxtb w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", "eor w20, w7, w20", @@ -387,11 +412,11 @@ "ExpectedArm64ASM": [ "eor w27, w7, w5", "uxth w20, w5", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "add w22, w7, w21", "uxth w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "rmif x21, #63, #nzCv", "eor w20, w7, w20", @@ -402,20 +427,24 @@ ] }, "adc ebx, ecx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 5, "Comment": "0x11", "ExpectedArm64ASM": [ "eor w27, w7, w5", + "cfinv", "adcs w26, w7, w5", + "cfinv", "mov x7, x26" ] }, "adc rbx, rcx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 5, "Comment": "0x11", "ExpectedArm64ASM": [ "eor w27, w7, w5", + "cfinv", "adcs x26, x7, x5", + "cfinv", "mov x7, x26" ] }, @@ -428,11 +457,11 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "uxtb w20, w7", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "add w22, w5, w21", "uxtb w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", "eor w20, w5, w20", @@ -451,11 +480,11 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "uxth w20, w7", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "add w22, w5, w21", "uxth w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "rmif x21, #63, #nzCv", "eor w20, w5, w20", @@ -466,26 +495,30 @@ ] }, "db 0x13, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 5, "Comment": [ "0x13", "adc ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", + "cfinv", "adcs w26, w5, w7", + "cfinv", "mov x5, x26" ] }, "db 0x48, 0x13, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 5, "Comment": [ "0x13", "adc rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", + "cfinv", "adcs x26, x5, x7", + "cfinv", "mov x5, x26" ] }, @@ -494,11 +527,11 @@ "Comment": "0x14", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", "eor w20, w4, #0x1", @@ -516,11 +549,11 @@ "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxth w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", "eor w20, w4, #0x1", @@ -534,21 +567,25 @@ ] }, "adc eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", + "cfinv", "adcs w26, w4, w20", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "adc rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", + "cfinv", "adcs x26, x4, x20", + "cfinv", "mov x27, x4", "mov x4, x26" ] @@ -559,11 +596,11 @@ "ExpectedArm64ASM": [ "mvn w27, w4", "mov w20, #0xff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", "eor w20, w4, #0xff", @@ -579,11 +616,11 @@ "ExpectedArm64ASM": [ "mvn w27, w4", "mov w20, #0xffff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxth w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #16", "rmif x20, #63, #nzCv", "eor w20, w4, #0xffff", @@ -594,22 +631,26 @@ ] }, "adc eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", + "cfinv", "adcs w26, w4, w20", + "cfinv", "mov x4, x26" ] }, "adc rax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "0x15", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mvn w27, w4", + "cfinv", "adcs x26, x4, x20", + "cfinv", "mov x4, x26" ] }, @@ -620,11 +661,11 @@ "eor w27, w7, w5", "uxtb w20, w7", "uxtb w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxtb w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #24", "rmif x22, #63, #nzCv", "eor w21, w20, w21", @@ -641,11 +682,11 @@ "eor w27, w7, w5", "uxth w20, w7", "uxth w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxth w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #16", "rmif x22, #63, #nzCv", "eor w21, w20, w21", @@ -656,24 +697,20 @@ ] }, "sbb ebx, ecx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "0x19", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "cfinv", "sbcs w26, w7, w5", - "cfinv", "mov x7, x26" ] }, "sbb rbx, rcx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "0x19", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "cfinv", "sbcs x26, x7, x5", - "cfinv", "mov x7, x26" ] }, @@ -687,11 +724,11 @@ "eor w27, w5, w7", "uxtb w20, w5", "uxtb w21, w7", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxtb w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #24", "rmif x22, #63, #nzCv", "eor w21, w20, w21", @@ -711,11 +748,11 @@ "eor w27, w5, w7", "uxth w20, w5", "uxth w21, w7", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxth w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #16", "rmif x22, #63, #nzCv", "eor w21, w20, w21", @@ -726,30 +763,26 @@ ] }, "db 0x1B, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": [ "0x1B", "sbb ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "cfinv", "sbcs w26, w5, w7", - "cfinv", "mov x5, x26" ] }, "db 0x48, 0x1B, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": [ "0x1B", "sbb rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "cfinv", "sbcs x26, x5, x7", - "cfinv", "mov x5, x26" ] }, @@ -759,11 +792,11 @@ "ExpectedArm64ASM": [ "uxtb w20, w4", "mov w21, #0x1", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", "eor w21, w20, #0x1", @@ -782,11 +815,11 @@ "ExpectedArm64ASM": [ "uxth w20, w4", "mov w21, #0x1", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxth w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "rmif x21, #63, #nzCv", "eor w21, w20, #0x1", @@ -800,25 +833,21 @@ ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "cfinv", "sbcs w26, w4, w20", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "cfinv", "sbcs x26, x4, x20", - "cfinv", "mov x27, x4", "mov x4, x26" ] @@ -830,11 +859,11 @@ "mvn w27, w4", "uxtb w20, w4", "mov w21, #0xff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", "eor w21, w20, #0xff", @@ -851,11 +880,11 @@ "mvn w27, w4", "uxth w20, w4", "mov w21, #0xffff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxth w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "rmif x21, #63, #nzCv", "eor w21, w20, #0xffff", @@ -866,65 +895,65 @@ ] }, "sbb eax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", - "cfinv", "sbcs w26, w4, w20", - "cfinv", "mov x4, x26" ] }, "sbb rax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mvn w27, w4", - "cfinv", "sbcs x26, x4, x20", - "cfinv", "mov x4, x26" ] }, "and bl, cl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x20", "ExpectedArm64ASM": [ "and w26, w7, w5", "cmn wzr, w26, lsl #24", - "bfxil x7, x26, #0, #8" + "bfxil x7, x26, #0, #8", + "cfinv" ] }, "and bx, cx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x21", "ExpectedArm64ASM": [ "and w26, w7, w5", "cmn wzr, w26, lsl #16", - "bfxil x7, x26, #0, #16" + "bfxil x7, x26, #0, #16", + "cfinv" ] }, "and ebx, ecx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0x21", "ExpectedArm64ASM": [ "ands w26, w7, w5", + "cfinv", "mov x7, x26" ] }, "and rbx, rcx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0x21", "ExpectedArm64ASM": [ "ands x26, x7, x5", + "cfinv", "mov x7, x26" ] }, "db 0x22, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": [ "0x22", "and bl, cl but modrm.rm as source" @@ -932,11 +961,12 @@ "ExpectedArm64ASM": [ "and w26, w5, w7", "cmn wzr, w26, lsl #24", - "bfxil x5, x26, #0, #8" + "bfxil x5, x26, #0, #8", + "cfinv" ] }, "db 0x66, 0x23, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": [ "0x23", "and bx, cx but modrm.rm as source" @@ -944,147 +974,154 @@ "ExpectedArm64ASM": [ "and w26, w5, w7", "cmn wzr, w26, lsl #16", - "bfxil x5, x26, #0, #16" + "bfxil x5, x26, #0, #16", + "cfinv" ] }, "db 0x23, 0xcb": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": [ "0x23", "and ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ "ands w26, w5, w7", + "cfinv", "mov x5, x26" ] }, "db 0x48, 0x23, 0xcb": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": [ "0x23", "and rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ "ands x26, x5, x7", + "cfinv", "mov x5, x26" ] }, "and al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x24", "ExpectedArm64ASM": [ "and w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "and ax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x25", "ExpectedArm64ASM": [ "and w26, w4, #0x1", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "and eax, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0x25", "ExpectedArm64ASM": [ "ands w26, w4, #0x1", + "cfinv", "mov x4, x26" ] }, "and rax, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0x25", "ExpectedArm64ASM": [ "ands x26, x4, #0x1", + "cfinv", "mov x4, x26" ] }, "and al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x24", "ExpectedArm64ASM": [ "and w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "and ax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x25", "ExpectedArm64ASM": [ "and w26, w4, #0xffff", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "and eax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x25", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ands w26, w4, w20", + "cfinv", "mov x4, x26" ] }, "and rax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x25", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "ands x26, x4, x20", + "cfinv", "mov x4, x26" ] }, "sub bl, cl": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x28", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #24", "cmp w0, w5, lsl #24", "sub w26, w7, w5", - "cfinv", "bfxil x7, x26, #0, #8" ] }, "sub bx, cx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x29", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #16", "cmp w0, w5, lsl #16", "sub w26, w7, w5", - "cfinv", "bfxil x7, x26, #0, #16" ] }, "sub ebx, ecx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x29", "ExpectedArm64ASM": [ "eor w27, w7, w5", "subs w26, w7, w5", - "cfinv", "mov x7, x26" ] }, "sub rbx, rcx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x29", "ExpectedArm64ASM": [ "eor w27, w7, w5", "subs x26, x7, x5", - "cfinv", "mov x7, x26" ] }, "db 0x2A, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": [ "0x2A", "sub bl, cl but modrm.rm as source" @@ -1094,12 +1131,11 @@ "lsl w0, w5, #24", "cmp w0, w7, lsl #24", "sub w26, w5, w7", - "cfinv", "bfxil x5, x26, #0, #8" ] }, "db 0x66, 0x2B, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": [ "0x2B", "sub bx, cx but modrm.rm as source" @@ -1109,12 +1145,11 @@ "lsl w0, w5, #16", "cmp w0, w7, lsl #16", "sub w26, w5, w7", - "cfinv", "bfxil x5, x26, #0, #16" ] }, "db 0x2B, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x2B", "sub ebx, ecx but modrm.rm as source" @@ -1122,12 +1157,11 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "subs w26, w5, w7", - "cfinv", "mov x5, x26" ] }, "db 0x48, 0x2B, 0xcb": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": [ "0x2B", "sub rbx, rcx but modrm.rm as source" @@ -1135,19 +1169,17 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "subs x26, x5, x7", - "cfinv", "mov x5, x26" ] }, "sub al, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x2C", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", - "cfinv", "mov x20, x4", "bfxil x20, x26, #0, #8", "mov x27, x4", @@ -1155,14 +1187,13 @@ ] }, "sub ax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, #0x1 (1)", - "cfinv", "mov x20, x4", "bfxil x20, x26, #0, #16", "mov x27, x4", @@ -1170,27 +1201,25 @@ ] }, "sub eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x2D", "ExpectedArm64ASM": [ "subs w26, w4, #0x1 (1)", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x2D", "ExpectedArm64ASM": [ "subs x26, x4, #0x1 (1)", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sub al, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x2C", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -1198,12 +1227,11 @@ "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0xff (255)", - "cfinv", "bfxil x4, x26, #0, #8" ] }, "sub ax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -1211,47 +1239,46 @@ "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "cfinv", "bfxil x4, x26, #0, #16" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", "subs w26, w4, w20", - "cfinv", "mov x4, x26" ] }, "sub rax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x2D", "ExpectedArm64ASM": [ "mvn w27, w4", "adds x26, x4, #0x1 (1)", - "cfinv", "mov x4, x26" ] }, "xor bl, cl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x30", "ExpectedArm64ASM": [ "eor w26, w7, w5", "cmn wzr, w26, lsl #24", - "bfxil x7, x26, #0, #8" + "bfxil x7, x26, #0, #8", + "cfinv" ] }, "xor bx, cx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x31", "ExpectedArm64ASM": [ "eor w26, w7, w5", "cmn wzr, w26, lsl #16", - "bfxil x7, x26, #0, #16" + "bfxil x7, x26, #0, #16", + "cfinv" ] }, "xor ebx, ecx": { @@ -1259,7 +1286,7 @@ "Comment": "0x31", "ExpectedArm64ASM": [ "eor w26, w7, w5", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x7, x26" ] }, @@ -1268,12 +1295,12 @@ "Comment": "0x31", "ExpectedArm64ASM": [ "eor x26, x7, x5", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x7, x26" ] }, "db 0x32, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": [ "0x32", "xor bl, cl but modrm.rm as source" @@ -1281,11 +1308,12 @@ "ExpectedArm64ASM": [ "eor w26, w5, w7", "cmn wzr, w26, lsl #24", - "bfxil x5, x26, #0, #8" + "bfxil x5, x26, #0, #8", + "cfinv" ] }, "db 0x66, 0x33, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": [ "0x33", "xor bx, cx but modrm.rm as source" @@ -1293,7 +1321,8 @@ "ExpectedArm64ASM": [ "eor w26, w5, w7", "cmn wzr, w26, lsl #16", - "bfxil x5, x26, #0, #16" + "bfxil x5, x26, #0, #16", + "cfinv" ] }, "db 0x33, 0xcb": { @@ -1304,7 +1333,7 @@ ], "ExpectedArm64ASM": [ "eor w26, w5, w7", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x5, x26" ] }, @@ -1316,26 +1345,28 @@ ], "ExpectedArm64ASM": [ "eor x26, x5, x7", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x5, x26" ] }, "xor al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x34", "ExpectedArm64ASM": [ "eor w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "xor ax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x35", "ExpectedArm64ASM": [ "eor w26, w4, #0x1", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "xor eax, 1": { @@ -1343,7 +1374,7 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "eor w26, w4, #0x1", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -1352,37 +1383,38 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "eor x26, x4, #0x1", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp bl, cl": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x38", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #24", "cmp w0, w5, lsl #24", - "sub w26, w7, w5", - "cfinv" + "sub w26, w7, w5" ] }, "xor al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x34", "ExpectedArm64ASM": [ "eor w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "xor ax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x35", "ExpectedArm64ASM": [ "eor w26, w4, #0xffff", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "xor eax, -1": { @@ -1391,7 +1423,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "eor w26, w4, w20", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -1401,41 +1433,38 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "eor x26, x4, x20", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp bx, cx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x39", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #16", "cmp w0, w5, lsl #16", - "sub w26, w7, w5", - "cfinv" + "sub w26, w7, w5" ] }, "cmp ebx, ecx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x39", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "subs w26, w7, w5", - "cfinv" + "subs w26, w7, w5" ] }, "cmp rbx, rcx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x39", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "subs x26, x7, x5", - "cfinv" + "subs x26, x7, x5" ] }, "db 0x3A, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": [ "0x3A", "cmp bl, cl but modrm.rm as source" @@ -1444,12 +1473,11 @@ "eor w27, w5, w7", "lsl w0, w5, #24", "cmp w0, w7, lsl #24", - "sub w26, w5, w7", - "cfinv" + "sub w26, w5, w7" ] }, "db 0x66, 0x3B, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": [ "0x3B", "cmp bx, cx but modrm.rm as source" @@ -1458,117 +1486,106 @@ "eor w27, w5, w7", "lsl w0, w5, #16", "cmp w0, w7, lsl #16", - "sub w26, w5, w7", - "cfinv" + "sub w26, w5, w7" ] }, "db 0x3B, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": [ "0x3B", "cmp ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "subs w26, w5, w7", - "cfinv" + "subs w26, w5, w7" ] }, "db 0x48, 0x3B, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": [ "0x3B", "cmp rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "subs x26, x5, x7", - "cfinv" + "subs x26, x5, x7" ] }, "cmp al, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x3C", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", - "cfinv", "mov x27, x4" ] }, "cmp ax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, #0x1 (1)", - "cfinv", "mov x27, x4" ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x3D", "ExpectedArm64ASM": [ "subs w26, w4, #0x1 (1)", - "cfinv", "mov x27, x4" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x3D", "ExpectedArm64ASM": [ "subs x26, x4, #0x1 (1)", - "cfinv", "mov x27, x4" ] }, "cmp al, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x3C", "ExpectedArm64ASM": [ "mov w20, #0xff", "mvn w27, w4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w4, #0xff (255)", - "cfinv" + "sub w26, w4, #0xff (255)" ] }, "cmp ax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffff", "mvn w27, w4", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", - "sub w26, w4, w20", - "cfinv" + "sub w26, w4, w20" ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", - "subs w26, w4, w20", - "cfinv" + "subs w26, w4, w20" ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x3D", "ExpectedArm64ASM": [ "mvn w27, w4", - "adds x26, x4, #0x1 (1)", - "cfinv" + "adds x26, x4, #0x1 (1)" ] }, "imul ax, bx, 257": { @@ -1582,7 +1599,7 @@ "bfxil x4, x20, #0, #16", "sbfx x20, x20, #15, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul eax, ebx, 257": { @@ -1595,7 +1612,7 @@ "mul w4, w7, w20", "sbfx x20, x4, #31, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul rax, rbx, 257": { @@ -1607,7 +1624,7 @@ "mul x4, x7, x20", "asr x20, x4, #63", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul ax, bx, 3": { @@ -1621,7 +1638,7 @@ "bfxil x4, x20, #0, #16", "sbfx x20, x20, #15, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul eax, ebx, 3": { @@ -1634,7 +1651,7 @@ "mul w4, w7, w20", "sbfx x20, x4, #31, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul rax, rbx, 3": { @@ -1646,44 +1663,48 @@ "mul x4, x7, x20", "asr x20, x4, #63", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "test al, bl": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0x84", "ExpectedArm64ASM": [ "and w26, w4, w7", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "test ax, bx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0x84", "ExpectedArm64ASM": [ "and w26, w4, w7", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "test eax, ebx": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "0x84", "ExpectedArm64ASM": [ - "ands w26, w4, w7" + "ands w26, w4, w7", + "cfinv" ] }, "test rax, rbx": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "0x84", "ExpectedArm64ASM": [ - "ands x26, x4, x7" + "ands x26, x4, x7", + "cfinv" ] }, "pushf": { "ExpectedInstructionCount": 39, "Comment": "0x9c", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -1728,7 +1749,7 @@ "ExpectedInstructionCount": 39, "Comment": "0x9c", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -1777,10 +1798,9 @@ "add x8, x8, #0x8 (8)", "mov w21, #0x202", "orr x27, x20, x21", - "rmif x27, #63, #nzCv", - "ubfx w20, w27, #2, #1", - "mov w21, #0x1", - "eor w26, w20, #0x1", + "mvn w20, w27", + "rmif x20, #63, #nzCv", + "ubfx w26, w20, #2, #1", "rmif x27, #4, #nZcv", "rmif x27, #4, #Nzcv", "ubfx w20, w27, #8, #1", @@ -1788,6 +1808,7 @@ "ubfx w20, w27, #9, #1", "strb w20, [x28, #985]", "ubfx w20, w27, #10, #1", + "mov w21, #0x1", "sub x20, x21, x20, lsl #1", "rmif x27, #11, #nzcV", "ubfx w21, w27, #12, #1", @@ -1817,9 +1838,9 @@ "mov w21, #0x28", "bic x20, x20, x21", "orr x27, x20, #0x2", - "rmif x27, #63, #nzCv", - "ubfx w20, w27, #2, #1", - "eor w26, w20, #0x1", + "mvn w20, w27", + "rmif x20, #63, #nzCv", + "ubfx w26, w20, #2, #1", "rmif x27, #4, #nZcv", "rmif x27, #4, #Nzcv" ] @@ -1828,7 +1849,7 @@ "ExpectedInstructionCount": 14, "Comment": "0x9f", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -1845,7 +1866,7 @@ ] }, "cmpsb": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": [ "0xa6" ], @@ -1856,14 +1877,13 @@ "lsl w0, w21, #24", "cmp w0, w20, lsl #24", "sub w26, w21, w20", - "cfinv", "ldrsb x20, [x28, #986]", "add x11, x11, x20", "add x10, x10, x20" ] }, "cmpsw": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xa7" ], @@ -1874,7 +1894,6 @@ "lsl w0, w21, #16", "cmp w0, w20, lsl #16", "sub w26, w21, w20", - "cfinv", "ldrsb x20, [x28, #986]", "lsl x20, x20, #1", "add x11, x11, x20", @@ -1882,7 +1901,7 @@ ] }, "cmpsd": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": [ "0xa7" ], @@ -1891,7 +1910,6 @@ "ldr w21, [x10]", "eor w27, w21, w20", "subs w26, w21, w20", - "cfinv", "ldrsb x20, [x28, #986]", "lsl x20, x20, #2", "add x11, x11, x20", @@ -1899,7 +1917,7 @@ ] }, "cmpsq": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": [ "0xa7" ], @@ -1908,7 +1926,6 @@ "ldr x21, [x10]", "eor w27, w21, w20", "subs x26, x21, x20", - "cfinv", "ldrsb x20, [x28, #986]", "lsl x20, x20, #3", "add x11, x11, x20", @@ -1916,10 +1933,10 @@ ] }, "repz cmpsb": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x64", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -1943,15 +1960,14 @@ "lsl w0, w27, #24", "cmp w0, w26, lsl #24", "sub w26, w27, w26", - "cfinv", "mov x27, x20" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x64", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -1975,15 +1991,14 @@ "lsl w0, w27, #16", "cmp w0, w26, lsl #16", "sub w26, w27, w26", - "cfinv", "mov x27, x20" ] }, "repz cmpsd": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x60", + "cbz x5, #+0x5c", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2005,15 +2020,14 @@ "b.eq #-0x18", "eor w20, w27, w26", "subs w26, w27, w26", - "cfinv", "mov x27, x20" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x60", + "cbz x5, #+0x5c", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2035,15 +2049,14 @@ "b.eq #-0x18", "eor w20, w27, w26", "subs x26, x27, x26", - "cfinv", "mov x27, x20" ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x64", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2067,15 +2080,14 @@ "lsl w0, w27, #24", "cmp w0, w26, lsl #24", "sub w26, w27, w26", - "cfinv", "mov x27, x20" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 25, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x64", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2099,15 +2111,14 @@ "lsl w0, w27, #16", "cmp w0, w26, lsl #16", "sub w26, w27, w26", - "cfinv", "mov x27, x20" ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x60", + "cbz x5, #+0x5c", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2129,15 +2140,14 @@ "b.ne #-0x18", "eor w20, w27, w26", "subs w26, w27, w26", - "cfinv", "mov x27, x20" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 23, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x60", + "cbz x5, #+0x5c", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -2159,72 +2169,79 @@ "b.ne #-0x18", "eor w20, w27, w26", "subs x26, x27, x26", - "cfinv", "mov x27, x20" ] }, "test al, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0xa8", "ExpectedArm64ASM": [ "and w26, w4, #0x1", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "test ax, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0xa9", "ExpectedArm64ASM": [ "and w26, w4, #0x1", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "test eax, 1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "ands w26, w4, #0x1" + "ands w26, w4, #0x1", + "cfinv" ] }, "test rax, 1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "ands x26, x4, #0x1" + "ands x26, x4, #0x1", + "cfinv" ] }, "test al, -1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0xa8", "ExpectedArm64ASM": [ "mov x26, x4", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "test ax, -1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0xa9", "ExpectedArm64ASM": [ "mov x26, x4", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "test eax, -1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "ands w26, w4, w4" + "ands w26, w4, w4", + "cfinv" ] }, "test rax, -1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "0xa9", "ExpectedArm64ASM": [ - "ands x26, x4, x4" + "ands x26, x4, x4", + "cfinv" ] }, "scasb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrb w20, [x11]", @@ -2232,13 +2249,12 @@ "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, w20", - "cfinv", "ldrsb x20, [x28, #986]", "add x11, x11, x20" ] }, "scasw": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrh w20, [x11]", @@ -2246,265 +2262,246 @@ "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "cfinv", "ldrsb x20, [x28, #986]", "add x11, x11, x20, lsl #1" ] }, "scasd": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldr w20, [x11]", "eor w27, w4, w20", "subs w26, w4, w20", - "cfinv", "ldrsb x20, [x28, #986]", "add x11, x11, x20, lsl #2" ] }, "scasq": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldr x20, [x11]", "eor w27, w4, w20", "subs x26, x4, x20", - "cfinv", "ldrsb x20, [x28, #986]", "add x11, x11, x20, lsl #3" ] }, "repz scasb": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x30", - "cbz x5, #+0x28", + "b #+0x2c", + "cbz x5, #+0x24", "ldrb w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x1 (1)", - "b.eq #-0x24", - "b #+0x2c", - "cbz x5, #+0x28", + "b.eq #-0x20", + "b #+0x28", + "cbz x5, #+0x24", "ldrb w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x1 (1)", - "b.eq #-0x24" + "b.eq #-0x20" ] }, "repz scasw": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x30", - "cbz x5, #+0x28", + "b #+0x2c", + "cbz x5, #+0x24", "ldrh w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x2 (2)", - "b.eq #-0x24", - "b #+0x2c", - "cbz x5, #+0x28", + "b.eq #-0x20", + "b #+0x28", + "cbz x5, #+0x24", "ldrh w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x2 (2)", - "b.eq #-0x24" + "b.eq #-0x20" ] }, "repz scasd": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x28", - "cbz x5, #+0x20", + "b #+0x24", + "cbz x5, #+0x1c", "ldr w20, [x11]", "eor w27, w4, w20", "subs w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x4 (4)", - "b.eq #-0x1c", - "b #+0x24", - "cbz x5, #+0x20", + "b.eq #-0x18", + "b #+0x20", + "cbz x5, #+0x1c", "ldr w20, [x11]", "eor w27, w4, w20", "subs w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x4 (4)", - "b.eq #-0x1c" + "b.eq #-0x18" ] }, "repz scasq": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x28", - "cbz x5, #+0x20", + "b #+0x24", + "cbz x5, #+0x1c", "ldr x20, [x11]", "eor w27, w4, w20", "subs x26, x4, x20", - "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x8 (8)", - "b.eq #-0x1c", - "b #+0x24", - "cbz x5, #+0x20", + "b.eq #-0x18", + "b #+0x20", + "cbz x5, #+0x1c", "ldr x20, [x11]", "eor w27, w4, w20", "subs x26, x4, x20", - "cfinv", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x8 (8)", - "b.eq #-0x1c" + "b.eq #-0x18" ] }, "repnz scasb": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x30", - "cbz x5, #+0x28", + "b #+0x2c", + "cbz x5, #+0x24", "ldrb w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x1 (1)", - "b.ne #-0x24", - "b #+0x2c", - "cbz x5, #+0x28", + "b.ne #-0x20", + "b #+0x28", + "cbz x5, #+0x24", "ldrb w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x1 (1)", - "b.ne #-0x24" + "b.ne #-0x20" ] }, "repnz scasw": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 23, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x30", - "cbz x5, #+0x28", + "b #+0x2c", + "cbz x5, #+0x24", "ldrh w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x2 (2)", - "b.ne #-0x24", - "b #+0x2c", - "cbz x5, #+0x28", + "b.ne #-0x20", + "b #+0x28", + "cbz x5, #+0x24", "ldrh w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x2 (2)", - "b.ne #-0x24" + "b.ne #-0x20" ] }, "repnz scasd": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x28", - "cbz x5, #+0x20", + "b #+0x24", + "cbz x5, #+0x1c", "ldr w20, [x11]", "eor w27, w4, w20", "subs w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x4 (4)", - "b.ne #-0x1c", - "b #+0x24", - "cbz x5, #+0x20", + "b.ne #-0x18", + "b #+0x20", + "cbz x5, #+0x1c", "ldr w20, [x11]", "eor w27, w4, w20", "subs w26, w4, w20", - "cfinv", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x4 (4)", - "b.ne #-0x1c" + "b.ne #-0x18" ] }, "repnz scasq": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 19, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x28", - "cbz x5, #+0x20", + "b #+0x24", + "cbz x5, #+0x1c", "ldr x20, [x11]", "eor w27, w4, w20", "subs x26, x4, x20", - "cfinv", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x8 (8)", - "b.ne #-0x1c", - "b #+0x24", - "cbz x5, #+0x20", + "b.ne #-0x18", + "b #+0x20", + "cbz x5, #+0x1c", "ldr x20, [x11]", "eor w27, w4, w20", "subs x26, x4, x20", - "cfinv", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x8 (8)", - "b.ne #-0x1c" + "b.ne #-0x18" ] }, "cmc": { @@ -2515,19 +2512,19 @@ ] }, "clc": { - "ExpectedInstructionCount": 1, - "Comment": "0xf8", - "ExpectedArm64ASM": [ - "rmif xzr, #63, #nzCv" - ] - }, - "stc": { "ExpectedInstructionCount": 2, - "Comment": "0xf9", + "Comment": "0xf8", "ExpectedArm64ASM": [ "mov w20, #0x1", "rmif x20, #63, #nzCv" ] + }, + "stc": { + "ExpectedInstructionCount": 1, + "Comment": "0xf9", + "ExpectedArm64ASM": [ + "rmif xzr, #63, #nzCv" + ] } } } diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index ace0f23f7..6b42801ac 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -13,7 +13,7 @@ }, "Instructions": { "add al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -22,17 +22,19 @@ "add w26, w4, #0x1 (1)", "mov x20, x4", "bfxil x20, x26, #0, #8", + "cfinv", "mov x27, x4", "mov x4, x20" ] }, "or al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "orr w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "adc al, 1": { @@ -40,11 +42,11 @@ "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", "eor w20, w4, #0x1", @@ -63,11 +65,11 @@ "ExpectedArm64ASM": [ "uxtb w20, w4", "mov w21, #0x1", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", "eor w21, w20, #0x1", @@ -81,23 +83,23 @@ ] }, "and al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "and w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "sub al, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", - "cfinv", "mov x20, x4", "bfxil x20, x26, #0, #8", "mov x27, x4", @@ -105,28 +107,28 @@ ] }, "xor al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "eor w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "cmp al, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", - "cfinv", "mov x27, x4" ] }, "add al, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -134,16 +136,18 @@ "lsl w0, w4, #24", "cmn w0, w20, lsl #24", "add w26, w4, #0xff (255)", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "or al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "orr w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "adc al, -1": { @@ -152,11 +156,11 @@ "ExpectedArm64ASM": [ "mvn w27, w4", "mov w20, #0xff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #24", "rmif x20, #63, #nzCv", "eor w20, w4, #0xff", @@ -173,11 +177,11 @@ "mvn w27, w4", "uxtb w20, w4", "mov w21, #0xff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", "eor w21, w20, #0xff", @@ -188,16 +192,17 @@ ] }, "and al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "and w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "sub al, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -205,33 +210,32 @@ "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0xff (255)", - "cfinv", "bfxil x4, x26, #0, #8" ] }, "xor al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "eor w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "cmp al, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "mov w20, #0xff", "mvn w27, w4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w4, #0xff (255)", - "cfinv" + "sub w26, w4, #0xff (255)" ] }, "add ax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", @@ -240,24 +244,27 @@ "add w26, w4, #0x100 (256)", "mov x20, x4", "bfxil x20, x26, #0, #16", + "cfinv", "mov x27, x4", "mov x4, x20" ] }, "add eax, 256": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "adds w26, w4, #0x100 (256)", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "add rax, 256": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "adds x26, x4, #0x100 (256)", + "cfinv", "mov x27, x4", "mov x4, x26" ] @@ -267,7 +274,7 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr w26, w4, #0x100", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -276,86 +283,86 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr x26, x4, #0x100", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "adc eax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", + "cfinv", "adcs w26, w4, w20", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "adc rax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", + "cfinv", "adcs x26, x4, x20", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sbb eax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "cfinv", "sbcs w26, w4, w20", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sbb rax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "cfinv", "sbcs x26, x4, x20", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "and eax, 256": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "ands w26, w4, #0x100", + "cfinv", "mov x4, x26" ] }, "and rax, 256": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "ands x26, x4, #0x100", + "cfinv", "mov x4, x26" ] }, "sub eax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "subs w26, w4, #0x100 (256)", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sub rax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "subs x26, x4, #0x100 (256)", - "cfinv", "mov x27, x4", "mov x4, x26" ] @@ -365,7 +372,7 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor w26, w4, #0x100", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -374,30 +381,28 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor x26, x4, #0x100", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp eax, 256": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "subs w26, w4, #0x100 (256)", - "cfinv", "mov x27, x4" ] }, "cmp rax, 256": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "subs x26, x4, #0x100 (256)", - "cfinv", "mov x27, x4" ] }, "add ax, -256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xff00", @@ -406,25 +411,28 @@ "add w26, w4, w20", "mov x20, x4", "bfxil x20, x26, #0, #16", + "cfinv", "mov x27, x4", "mov x4, x20" ] }, "add eax, -256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "adds w26, w4, w20", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "add rax, -256": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "subs x26, x4, #0x100 (256)", + "cfinv", "mov x27, x4", "mov x4, x26" ] @@ -434,7 +442,7 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr w26, w4, #0xffffff00", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -443,87 +451,87 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr x26, x4, #0xffffffffffffff00", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "adc eax, -256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", + "cfinv", "adcs w26, w4, w20", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "adc rax, -256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", + "cfinv", "adcs x26, x4, x20", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sbb eax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "cfinv", "sbcs w26, w4, w20", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sbb rax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "cfinv", "sbcs x26, x4, x20", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "and eax, -256": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "ands w26, w4, #0xffffff00", + "cfinv", "mov x4, x26" ] }, "and rax, -256": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "ands x26, x4, #0xffffffffffffff00", + "cfinv", "mov x4, x26" ] }, "sub eax, -256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "subs w26, w4, w20", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sub rax, -256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "adds x26, x4, #0x100 (256)", - "cfinv", "mov x27, x4", "mov x4, x26" ] @@ -533,7 +541,7 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor w26, w4, #0xffffff00", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -542,31 +550,29 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor x26, x4, #0xffffffffffffff00", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp eax, -256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "subs w26, w4, w20", - "cfinv", "mov x27, x4" ] }, "cmp rax, -256": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "adds x26, x4, #0x100 (256)", - "cfinv", "mov x27, x4" ] }, "add ax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -575,24 +581,27 @@ "add w26, w4, #0x1 (1)", "mov x20, x4", "bfxil x20, x26, #0, #16", + "cfinv", "mov x27, x4", "mov x4, x20" ] }, "add eax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "adds w26, w4, #0x1 (1)", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "add rax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "adds x26, x4, #0x1 (1)", + "cfinv", "mov x27, x4", "mov x4, x26" ] @@ -602,7 +611,7 @@ "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "orr w26, w4, #0x1", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -611,86 +620,86 @@ "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "orr x26, x4, #0x1", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "adc eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", + "cfinv", "adcs w26, w4, w20", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "adc rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", + "cfinv", "adcs x26, x4, x20", + "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "cfinv", "sbcs w26, w4, w20", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "cfinv", "sbcs x26, x4, x20", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "and eax, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "ands w26, w4, #0x1", + "cfinv", "mov x4, x26" ] }, "and rax, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "ands x26, x4, #0x1", + "cfinv", "mov x4, x26" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "subs w26, w4, #0x1 (1)", - "cfinv", "mov x27, x4", "mov x4, x26" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "subs x26, x4, #0x1 (1)", - "cfinv", "mov x27, x4", "mov x4, x26" ] @@ -700,7 +709,7 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "eor w26, w4, #0x1", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -709,30 +718,28 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "eor x26, x4, #0x1", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "subs w26, w4, #0x1 (1)", - "cfinv", "mov x27, x4" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "subs x26, x4, #0x1 (1)", - "cfinv", "mov x27, x4" ] }, "add ax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -740,25 +747,28 @@ "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, w20", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "add eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", "adds w26, w4, w20", + "cfinv", "mov x4, x26" ] }, "add rax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mvn w27, w4", "subs x26, x4, #0x1 (1)", + "cfinv", "mov x4, x26" ] }, @@ -768,7 +778,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "orr w26, w4, w20", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -778,90 +788,90 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "orr x26, x4, x20", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "adc eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", + "cfinv", "adcs w26, w4, w20", + "cfinv", "mov x4, x26" ] }, "adc rax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mvn w27, w4", + "cfinv", "adcs x26, x4, x20", + "cfinv", "mov x4, x26" ] }, "sbb eax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", - "cfinv", "sbcs w26, w4, w20", - "cfinv", "mov x4, x26" ] }, "sbb rax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mvn w27, w4", - "cfinv", "sbcs x26, x4, x20", - "cfinv", "mov x4, x26" ] }, "and eax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ands w26, w4, w20", + "cfinv", "mov x4, x26" ] }, "and rax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "ands x26, x4, x20", + "cfinv", "mov x4, x26" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", "subs w26, w4, w20", - "cfinv", "mov x4, x26" ] }, "sub rax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mvn w27, w4", "adds x26, x4, #0x1 (1)", - "cfinv", "mov x4, x26" ] }, @@ -871,7 +881,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "eor w26, w4, w20", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -881,31 +891,29 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "eor x26, x4, x20", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", - "subs w26, w4, w20", - "cfinv" + "subs w26, w4, w20" ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mvn w27, w4", - "adds x26, x4, #0x1 (1)", - "cfinv" + "adds x26, x4, #0x1 (1)" ] }, "rol al, 2": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xC0 /0", "ExpectedArm64ASM": [ "mov w20, w4", @@ -913,27 +921,29 @@ "bfi w20, w20, #16, #16", "ror w20, w20, #30", "bfxil x4, x20, #0, #8", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "ror al, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC0 /1", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #8, #8", "ror w20, w20, #2", "bfxil x4, x20, #0, #8", + "eor x20, x20, #0x80", "rmif x20, #6, #nzCv" ] }, "rcl al, 2": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 19, "Comment": "GROUP2 0xC0 /2", "ExpectedArm64ASM": [ "uxtb w20, w4", "mov w21, #0x0", - "cset w22, hs", + "cset w22, lo", "bfi x21, x20, #55, #8", "bfi x21, x22, #63, #1", "bfi x21, x20, #46, #8", @@ -948,14 +958,15 @@ "ror x20, x21, #62", "bfxil x4, x20, #0, #8", "ror x20, x21, #61", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "rcr al, 2": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xC0 /3", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "uxtb w21, w4", "bfi x21, x20, #8, #1", "bfi x21, x21, #9, #9", @@ -963,102 +974,112 @@ "bfi x21, x21, #36, #9", "lsr x20, x21, #2", "bfxil x4, x20, #0, #8", - "rmif x21, #0, #nzCv" + "eor x20, x21, #0x2", + "rmif x20, #0, #nzCv" ] }, "shl al, 2": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC0 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #2", "cmn wzr, w26, lsl #24", - "rmif x4, #5, #nzCv", + "eor x20, x4, #0x40", + "rmif x20, #5, #nzCv", "bfxil x4, x26, #0, #8" ] }, "shr al, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC0 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", "lsr w26, w20, #2", "cmn wzr, w26, lsl #24", + "eor x20, x20, #0x2", "rmif x20, #0, #nzCv", "bfxil x4, x26, #0, #8" ] }, "sar al, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC0 /7", "ExpectedArm64ASM": [ "sxtb x20, w4", "asr w26, w20, #2", "cmn wzr, w26, lsl #24", + "eor x20, x20, #0x2", "rmif x20, #0, #nzCv", "bfxil x4, x26, #0, #8" ] }, "rol ax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /0", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #16, #16", "ror w20, w20, #30", "bfxil x4, x20, #0, #16", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "rol eax, 2": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xC1 /0", "ExpectedArm64ASM": [ "ror w4, w4, #30", - "rmif x4, #63, #nzCv" + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv" ] }, "rol rax, 2": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xC1 /0", "ExpectedArm64ASM": [ "ror x4, x4, #62", - "rmif x4, #63, #nzCv" + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv" ] }, "ror ax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /1", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #16, #16", "ror w20, w20, #2", "bfxil x4, x20, #0, #16", + "eor x20, x20, #0x8000", "rmif x20, #14, #nzCv" ] }, "ror eax, 2": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xC1 /1", "ExpectedArm64ASM": [ "ror w4, w4, #2", - "rmif x4, #30, #nzCv" + "eor x20, x4, #0x80000000", + "rmif x20, #30, #nzCv" ] }, "ror rax, 2": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xC1 /1", "ExpectedArm64ASM": [ "ror x4, x4, #2", - "rmif x4, #62, #nzCv" + "eor x20, x4, #0x8000000000000000", + "rmif x20, #62, #nzCv" ] }, "rcl ax, 2": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "uxth w20, w4", "mov w21, #0x0", - "cset w22, hs", + "cset w22, lo", "bfi x21, x20, #47, #16", "bfi x21, x22, #63, #1", "bfi x21, x20, #30, #16", @@ -1069,161 +1090,176 @@ "ror x20, x21, #62", "bfxil x4, x20, #0, #16", "ror x20, x21, #61", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "rcl eax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "lsl w20, w4, #2", - "cset w21, hs", + "cset w21, lo", "orr w20, w20, w4, lsr #31", - "rmif x4, #29, #nzCv", + "eor x22, x4, #0x40000000", + "rmif x22, #29, #nzCv", "orr w4, w20, w21, lsl #1" ] }, "rcl rax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "lsl x20, x4, #2", - "cset w21, hs", + "cset w21, lo", "orr x20, x20, x4, lsr #63", - "rmif x4, #61, #nzCv", + "eor x22, x4, #0x4000000000000000", + "rmif x22, #61, #nzCv", "orr x4, x20, x21, lsl #1" ] }, "rcr ax, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "uxth w21, w4", "bfi x21, x20, #16, #1", "bfi x21, x21, #17, #17", "bfi x21, x21, #34, #17", "lsr x20, x21, #2", "bfxil x4, x20, #0, #16", - "rmif x21, #0, #nzCv" + "eor x20, x21, #0x2", + "rmif x20, #0, #nzCv" ] }, "rcr eax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "lsr w20, w4, #2", - "cset w21, hs", + "cset w21, lo", "orr w20, w20, w4, lsl #31", - "rmif x4, #0, #nzCv", + "eor x22, x4, #0x2", + "rmif x22, #0, #nzCv", "orr w4, w20, w21, lsl #30" ] }, "rcr rax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "lsr x20, x4, #2", - "cset w21, hs", + "cset w21, lo", "orr x20, x20, x4, lsl #63", - "rmif x4, #0, #nzCv", + "eor x22, x4, #0x2", + "rmif x22, #0, #nzCv", "orr x4, x20, x21, lsl #62" ] }, "shl ax, 2": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #2", "cmn wzr, w26, lsl #16", - "rmif x4, #13, #nzCv", + "eor x20, x4, #0x4000", + "rmif x20, #13, #nzCv", "bfxil x4, x26, #0, #16" ] }, "shl eax, 2": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #2", - "tst w26, w26", - "rmif x4, #29, #nzCv", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x40000000", + "rmif x20, #29, #nzCv", "mov x4, x26" ] }, "shl rax, 2": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /4", "ExpectedArm64ASM": [ "lsl x26, x4, #2", - "tst x26, x26", - "rmif x4, #61, #nzCv", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x4000000000000000", + "rmif x20, #61, #nzCv", "mov x4, x26" ] }, "shr ax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "uxth w20, w4", "lsr w26, w20, #2", "cmn wzr, w26, lsl #16", + "eor x20, x20, #0x2", "rmif x20, #0, #nzCv", "bfxil x4, x26, #0, #16" ] }, "shr eax, 2": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "lsr w26, w4, #2", - "tst w26, w26", - "rmif x4, #0, #nzCv", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x2", + "rmif x20, #0, #nzCv", "mov x4, x26" ] }, "shr rax, 2": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "lsr x26, x4, #2", - "tst x26, x26", - "rmif x4, #0, #nzCv", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x2", + "rmif x20, #0, #nzCv", "mov x4, x26" ] }, "sar ax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /7", "ExpectedArm64ASM": [ "sxth x20, w4", "asr w26, w20, #2", "cmn wzr, w26, lsl #16", + "eor x20, x20, #0x2", "rmif x20, #0, #nzCv", "bfxil x4, x26, #0, #16" ] }, "sar eax, 2": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /7", "ExpectedArm64ASM": [ "asr w26, w4, #2", - "tst w26, w26", - "rmif x4, #0, #nzCv", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x2", + "rmif x20, #0, #nzCv", "mov x4, x26" ] }, "sar rax, 2": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xC1 /7", "ExpectedArm64ASM": [ "asr x26, x4, #2", - "tst x26, x26", - "rmif x4, #0, #nzCv", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x2", + "rmif x20, #0, #nzCv", "mov x4, x26" ] }, "rol al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd0 /0", "ExpectedArm64ASM": [ "mov w20, w4", @@ -1231,44 +1267,48 @@ "bfi w20, w20, #16, #16", "ror w20, w20, #31", "bfxil x4, x20, #0, #8", - "rmif x20, #63, #nzCv", + "eor x21, x20, #0x1", + "rmif x21, #63, #nzCv", "eor w20, w20, w20, lsr #7", "rmif x20, #0, #nzcV" ] }, "ror al, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd0 /1", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #8, #8", "ror w20, w20, #1", "bfxil x4, x20, #0, #8", - "rmif x20, #6, #nzCv", + "eor x21, x20, #0x80", + "rmif x21, #6, #nzCv", "eor w20, w20, w20, lsr #1", "rmif x20, #6, #nzcV" ] }, "rcl al, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd0 /2", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, hs", + "cset w21, lo", "orr w21, w21, w20, lsl #1", - "rmif x20, #6, #nzCv", + "eor x22, x20, #0x80", + "rmif x22, #6, #nzCv", "eor w20, w21, w20", "rmif x20, #7, #nzcV", "bfxil x4, x21, #0, #8" ] }, "rcr al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd0 /3", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, hs", - "rmif x20, #63, #nzCv", + "cset w21, lo", + "eor x22, x20, #0x1", + "rmif x22, #63, #nzCv", "ubfx w20, w20, #1, #7", "bfi w20, w21, #7, #1", "bfxil x4, x20, #0, #8", @@ -1277,149 +1317,162 @@ ] }, "shl al, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd0 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #1", "cmn wzr, w26, lsl #24", - "rmif x4, #6, #nzCv", + "eor x20, x4, #0x80", + "rmif x20, #6, #nzCv", "eor w20, w26, w4", "rmif x20, #7, #nzcV", "bfxil x4, x26, #0, #8" ] }, "shr al, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd0 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", "lsr w26, w20, #1", "cmn wzr, w26, lsl #24", - "rmif x20, #63, #nzCv", + "eor x21, x20, #0x1", + "rmif x21, #63, #nzCv", "rmif x20, #7, #nzcV", "bfxil x4, x26, #0, #8" ] }, "sar al, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd0 /7", "ExpectedArm64ASM": [ "sxtb x20, w4", "asr w26, w20, #1", "cmn wzr, w26, lsl #24", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv", "bfxil x4, x26, #0, #8" ] }, "rol ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd1 /0", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #16, #16", "ror w20, w20, #31", "bfxil x4, x20, #0, #16", - "rmif x20, #63, #nzCv", + "eor x21, x20, #0x1", + "rmif x21, #63, #nzCv", "eor w20, w20, w20, lsr #15", "rmif x20, #0, #nzcV" ] }, "rol eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xd1 /0", "ExpectedArm64ASM": [ "ror w4, w4, #31", - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "eor w20, w4, w4, lsr #31", "rmif x20, #0, #nzcV" ] }, "rol rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xd1 /0", "ExpectedArm64ASM": [ "ror x4, x4, #63", - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "eor x20, x4, x4, lsr #63", "rmif x20, #0, #nzcV" ] }, "ror ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd1 /1", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #16, #16", "ror w20, w20, #1", "bfxil x4, x20, #0, #16", - "rmif x20, #14, #nzCv", + "eor x21, x20, #0x8000", + "rmif x21, #14, #nzCv", "eor w20, w20, w20, lsr #1", "rmif x20, #14, #nzcV" ] }, "ror eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xd1 /1", "ExpectedArm64ASM": [ "ror w4, w4, #1", - "rmif x4, #30, #nzCv", + "eor x20, x4, #0x80000000", + "rmif x20, #30, #nzCv", "eor w20, w4, w4, lsr #1", "rmif x20, #30, #nzcV" ] }, "ror rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xd1 /1", "ExpectedArm64ASM": [ "ror x4, x4, #1", - "rmif x4, #62, #nzCv", + "eor x20, x4, #0x8000000000000000", + "rmif x20, #62, #nzCv", "eor x20, x4, x4, lsr #1", "rmif x20, #62, #nzcV" ] }, "rcl ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ "uxth w20, w4", - "cset w21, hs", + "cset w21, lo", "orr w21, w21, w20, lsl #1", - "rmif x20, #14, #nzCv", + "eor x22, x20, #0x8000", + "rmif x22, #14, #nzCv", "eor w20, w21, w20", "rmif x20, #15, #nzcV", "bfxil x4, x21, #0, #16" ] }, "rcl eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ "mov w20, w4", - "cset w21, hs", + "cset w21, lo", "orr w4, w21, w20, lsl #1", - "rmif x20, #30, #nzCv", + "eor x21, x20, #0x80000000", + "rmif x21, #30, #nzCv", "eor w20, w4, w20", "rmif x20, #31, #nzcV" ] }, "rcl rax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "orr x20, x20, x4, lsl #1", - "rmif x4, #62, #nzCv", + "eor x21, x4, #0x8000000000000000", + "rmif x21, #62, #nzCv", "eor x21, x20, x4", "rmif x21, #63, #nzcV", "mov x4, x20" ] }, "rcr ax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, hs", - "rmif x4, #63, #nzCv", + "cset w20, lo", + "eor x21, x4, #0x1", + "rmif x21, #63, #nzCv", "ubfx w21, w4, #1, #15", "orr w20, w21, w20, lsl #15", "bfxil x4, x20, #0, #16", @@ -1428,171 +1481,184 @@ ] }, "rcr eax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, hs", - "rmif x4, #63, #nzCv", + "cset w20, lo", + "eor x21, x4, #0x1", + "rmif x21, #63, #nzCv", "extr w4, w20, w4, #1", "eor x20, x4, x4, lsr #1", "rmif x20, #30, #nzcV" ] }, "rcr rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, hs", - "rmif x4, #63, #nzCv", + "cset w20, lo", + "eor x21, x4, #0x1", + "rmif x21, #63, #nzCv", "extr x4, x20, x4, #1", "eor x20, x4, x4, lsr #1", "rmif x20, #62, #nzcV" ] }, "shl ax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #1", "cmn wzr, w26, lsl #16", - "rmif x4, #14, #nzCv", + "eor x20, x4, #0x8000", + "rmif x20, #14, #nzCv", "eor w20, w26, w4", "rmif x20, #15, #nzcV", "bfxil x4, x26, #0, #16" ] }, "shl eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #1", - "tst w26, w26", - "rmif x4, #30, #nzCv", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x80000000", + "rmif x20, #30, #nzCv", "eor w20, w26, w4", "rmif x20, #31, #nzcV", "mov x4, x26" ] }, "shl rax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ "lsl x26, x4, #1", - "tst x26, x26", - "rmif x4, #62, #nzCv", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x8000000000000000", + "rmif x20, #62, #nzCv", "eor x20, x26, x4", "rmif x20, #63, #nzcV", "mov x4, x26" ] }, "shr ax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd1 /5", "ExpectedArm64ASM": [ "uxth w20, w4", "lsr w26, w20, #1", "cmn wzr, w26, lsl #16", - "rmif x20, #63, #nzCv", + "eor x21, x20, #0x1", + "rmif x21, #63, #nzCv", "rmif x20, #15, #nzcV", "bfxil x4, x26, #0, #16" ] }, "shr eax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd1 /5", "ExpectedArm64ASM": [ "lsr w26, w4, #1", - "tst w26, w26", - "rmif x4, #63, #nzCv", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "rmif x4, #31, #nzcV", "mov x4, x26" ] }, "shr rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd1 /5", "ExpectedArm64ASM": [ "lsr x26, x4, #1", - "tst x26, x26", - "rmif x4, #63, #nzCv", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "rmif x4, #63, #nzcV", "mov x4, x26" ] }, "sar ax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd1 /7", "ExpectedArm64ASM": [ "sxth x20, w4", "asr w26, w20, #1", "cmn wzr, w26, lsl #16", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv", "bfxil x4, x26, #0, #16" ] }, "sar eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xd1 /7", "ExpectedArm64ASM": [ "asr w26, w4, #1", - "tst w26, w26", - "rmif x4, #63, #nzCv", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "mov x4, x26" ] }, "sar rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xd1 /7", "ExpectedArm64ASM": [ "asr x26, x4, #1", - "tst x26, x26", - "rmif x4, #63, #nzCv", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "mov x4, x26" ] }, "rol al, cl": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd2 /0", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x28", + "cbz x20, #+0x2c", "mov w20, w4", "bfi w20, w4, #8, #8", "bfi w20, w20, #16, #16", "neg w21, w5", "ror w20, w20, w21", "bfxil x4, x20, #0, #8", - "rmif x20, #63, #nzCv", + "eor x21, x20, #0x1", + "rmif x21, #63, #nzCv", "eor w20, w20, w20, lsr #7", "rmif x20, #0, #nzcV" ] }, "ror al, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd2 /1", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x24", + "cbz x20, #+0x28", "mov w20, w4", "bfi w20, w4, #8, #8", "bfi w20, w20, #16, #16", "ror w20, w20, w5", "bfxil x4, x20, #0, #8", - "rmif x20, #6, #nzCv", + "eor x21, x20, #0x80", + "rmif x21, #6, #nzCv", "eor w20, w20, w20, lsr #1", "rmif x20, #6, #nzcV" ] }, "rcl al, cl": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "GROUP2 0xd2 /2", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x64", + "cbz x20, #+0x68", "and w20, w5, #0x1f", "uxtb w21, w4", "mov w22, #0x0", - "cset w23, hs", + "cset w23, lo", "bfi x22, x21, #55, #8", "bfi x22, x23, #63, #1", "bfi x22, x21, #46, #8", @@ -1610,19 +1676,20 @@ "mov w23, #0x3f", "sub x20, x23, x20", "ror x20, x22, x20", - "rmif x20, #63, #nzCv", + "eor x22, x20, #0x1", + "rmif x22, #63, #nzCv", "eor x20, x20, x21, lsr #7", "rmif x20, #0, #nzcV" ] }, "rcr al, cl": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 17, "Comment": "GROUP2 0xd2 /3", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x3c", + "cbz x20, #+0x40", "and w20, w5, #0x1f", - "cset w21, hs", + "cset w21, lo", "uxtb w22, w4", "bfi x22, x21, #8, #1", "bfi x22, x22, #9, #9", @@ -1632,38 +1699,41 @@ "bfxil x4, x21, #0, #8", "sub w20, w20, #0x1 (1)", "lsr w20, w22, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv", "eor w20, w21, w21, lsr #1", "rmif x20, #6, #nzcV" ] }, "shl al, cl": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd2 /4", "ExpectedArm64ASM": [ "lsl w20, w4, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x18", + "cbz w0, #+0x1c", "cmn wzr, w20, lsl #24", "mov x26, x20", + "mvn x0, x20", "eor w2, w4, w20", - "rmif x20, #7, #nzCv", + "rmif x0, #7, #nzCv", "rmif x2, #7, #nzcV", "bfxil x4, x20, #0, #8" ] }, "shr al, cl": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xd2 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", "lsr w21, w20, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x20", + "cbz w0, #+0x24", "cmn wzr, w21, lsl #24", "mov x26, x21", "sub x0, x5, #0x1 (1)", "lsr w0, w20, w0", + "mvn x0, x0", "eor w2, w20, w21", "rmif x0, #63, #nzCv", "rmif x2, #7, #nzcV", @@ -1671,46 +1741,49 @@ ] }, "sar al, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd2 /7", "ExpectedArm64ASM": [ "sxtb x20, w4", "asr w21, w20, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x18", + "cbz w0, #+0x1c", "cmn wzr, w21, lsl #24", "mov x26, x21", "sub x0, x5, #0x1 (1)", "lsr w0, w20, w0", + "mvn x0, x0", "rmif x0, #63, #nzCv", "bfxil x4, x21, #0, #8" ] }, "rol ax, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd3 /0", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x24", + "cbz x20, #+0x28", "mov w20, w4", "bfi w20, w4, #16, #16", "neg w21, w5", "ror w20, w20, w21", "bfxil x4, x20, #0, #16", - "rmif x20, #63, #nzCv", + "eor x21, x20, #0x1", + "rmif x21, #63, #nzCv", "eor w20, w20, w20, lsr #15", "rmif x20, #0, #nzcV" ] }, "rol eax, cl": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd3 /0", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x1c", + "cbz x20, #+0x20", "neg w20, w5", "ror w4, w4, w20", - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "eor w20, w4, w4, lsr #31", "rmif x20, #0, #nzcV", "b #+0x8", @@ -1718,41 +1791,44 @@ ] }, "rol rax, cl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd3 /0", "ExpectedArm64ASM": [ "and x20, x5, #0x3f", - "cbz x20, #+0x18", + "cbz x20, #+0x1c", "neg x20, x5", "ror x4, x4, x20", - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "eor x20, x4, x4, lsr #63", "rmif x20, #0, #nzcV" ] }, "ror ax, cl": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd3 /1", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x20", + "cbz x20, #+0x24", "mov w20, w4", "bfi w20, w4, #16, #16", "ror w20, w20, w5", "bfxil x4, x20, #0, #16", - "rmif x20, #14, #nzCv", + "eor x21, x20, #0x8000", + "rmif x21, #14, #nzCv", "eor w20, w20, w20, lsr #1", "rmif x20, #14, #nzcV" ] }, "ror eax, cl": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd3 /1", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x18", + "cbz x20, #+0x1c", "ror w4, w4, w5", - "rmif x4, #30, #nzCv", + "eor x20, x4, #0x80000000", + "rmif x20, #30, #nzCv", "eor w20, w4, w4, lsr #1", "rmif x20, #30, #nzcV", "b #+0x8", @@ -1760,27 +1836,28 @@ ] }, "ror rax, cl": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd3 /1", "ExpectedArm64ASM": [ "and x20, x5, #0x3f", - "cbz x20, #+0x14", + "cbz x20, #+0x18", "ror x4, x4, x5", - "rmif x4, #62, #nzCv", + "eor x20, x4, #0x8000000000000000", + "rmif x20, #62, #nzCv", "eor x20, x4, x4, lsr #1", "rmif x20, #62, #nzcV" ] }, "rcl ax, cl": { - "ExpectedInstructionCount": 22, + "ExpectedInstructionCount": 23, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x54", + "cbz x20, #+0x58", "and w20, w5, #0x1f", "uxth w21, w4", "mov w22, #0x0", - "cset w23, hs", + "cset w23, lo", "bfi x22, x21, #47, #16", "bfi x22, x23, #63, #1", "bfi x22, x21, #30, #16", @@ -1794,24 +1871,26 @@ "mov w23, #0x3f", "sub x20, x23, x20", "ror x20, x22, x20", - "rmif x20, #63, #nzCv", + "eor x22, x20, #0x1", + "rmif x22, #63, #nzCv", "eor x20, x20, x21, lsr #15", "rmif x20, #0, #nzcV" ] }, "rcl eax, cl": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 17, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x38", + "cbz x20, #+0x3c", "lsl w20, w4, w5", - "cset w21, hs", + "cset w21, lo", "neg w22, w5", "lsr w23, w4, w22", "orr w20, w20, w23, lsr #1", "lsr w22, w4, w22", - "rmif x22, #63, #nzCv", + "eor x23, x22, #0x1", + "rmif x23, #63, #nzCv", "sub w23, w5, #0x1 (1)", "lsl w21, w21, w23", "orr w4, w20, w21", @@ -1822,18 +1901,19 @@ ] }, "rcl rax, cl": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ "and x20, x5, #0x3f", - "cbz x20, #+0x34", + "cbz x20, #+0x38", "lsl x20, x4, x5", - "cset w21, hs", + "cset w21, lo", "neg x22, x5", "lsr x23, x4, x22", "orr x20, x20, x23, lsr #1", "lsr x22, x4, x22", - "rmif x22, #63, #nzCv", + "eor x23, x22, #0x1", + "rmif x23, #63, #nzCv", "sub x23, x5, #0x1 (1)", "lsl x21, x21, x23", "orr x4, x20, x21", @@ -1842,13 +1922,13 @@ ] }, "rcr ax, cl": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 16, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x38", + "cbz x20, #+0x3c", "and w20, w5, #0x1f", - "cset w21, hs", + "cset w21, lo", "uxth w22, w4", "bfi x22, x21, #16, #1", "bfi x22, x22, #17, #17", @@ -1857,24 +1937,26 @@ "bfxil x4, x21, #0, #16", "sub w20, w20, #0x1 (1)", "lsr w20, w22, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv", "eor w20, w21, w21, lsr #1", "rmif x20, #14, #nzcV" ] }, "rcr eax, cl": { - "ExpectedInstructionCount": 16, + "ExpectedInstructionCount": 17, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x38", + "cbz x20, #+0x3c", "lsr w20, w4, w5", - "cset w21, hs", + "cset w21, lo", "neg w22, w5", "lsl w23, w4, w22", "orr w20, w20, w23, lsl #1", "sub w23, w5, #0x1 (1)", "lsr w23, w4, w23", + "eor x23, x23, #0x1", "rmif x23, #63, #nzCv", "lsl w21, w21, w22", "orr w4, w20, w21", @@ -1885,18 +1967,19 @@ ] }, "rcr rax, cl": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ "and x20, x5, #0x3f", - "cbz x20, #+0x34", + "cbz x20, #+0x38", "lsr x20, x4, x5", - "cset w21, hs", + "cset w21, lo", "neg x22, x5", "lsl x23, x4, x22", "orr x20, x20, x23, lsl #1", "sub x23, x5, #0x1 (1)", "lsr x23, x4, x23", + "eor x23, x23, #0x1", "rmif x23, #63, #nzCv", "lsl x21, x21, x22", "orr x4, x20, x21", @@ -1905,30 +1988,32 @@ ] }, "shl ax, cl": { - "ExpectedInstructionCount": 9, - "Comment": "GROUP2 0xd3 /4", - "ExpectedArm64ASM": [ - "lsl w20, w4, w5", - "and w0, w5, #0x1f", - "cbz w0, #+0x18", - "cmn wzr, w20, lsl #16", - "mov x26, x20", - "eor w2, w4, w20", - "rmif x20, #15, #nzCv", - "rmif x2, #15, #nzcV", - "bfxil x4, x20, #0, #16" - ] - }, - "shl eax, cl": { "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ "lsl w20, w4, w5", "and w0, w5, #0x1f", "cbz w0, #+0x1c", + "cmn wzr, w20, lsl #16", + "mov x26, x20", + "mvn x0, x20", + "eor w2, w4, w20", + "rmif x0, #15, #nzCv", + "rmif x2, #15, #nzcV", + "bfxil x4, x20, #0, #16" + ] + }, + "shl eax, cl": { + "ExpectedInstructionCount": 11, + "Comment": "GROUP2 0xd3 /4", + "ExpectedArm64ASM": [ + "lsl w20, w4, w5", + "and w0, w5, #0x1f", + "cbz w0, #+0x20", "ands w26, w20, w20", "neg w0, w5", "lsr w0, w4, w0", + "mvn x0, x0", "eor w2, w4, w20", "rmif x0, #63, #nzCv", "rmif x2, #31, #nzcV", @@ -1936,15 +2021,16 @@ ] }, "shl rax, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ "lsl x20, x4, x5", "and w0, w5, #0x3f", - "cbz x0, #+0x1c", + "cbz x0, #+0x20", "ands x26, x20, x20", "neg x0, x5", "lsr x0, x4, x0", + "mvn x0, x0", "eor x2, x4, x20", "rmif x0, #63, #nzCv", "rmif x2, #63, #nzcV", @@ -1952,17 +2038,18 @@ ] }, "shr ax, cl": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ "uxth w20, w4", "lsr w21, w20, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x20", + "cbz w0, #+0x24", "cmn wzr, w21, lsl #16", "mov x26, x21", "sub x0, x5, #0x1 (1)", "lsr w0, w20, w0", + "mvn x0, x0", "eor w2, w20, w21", "rmif x0, #63, #nzCv", "rmif x2, #15, #nzcV", @@ -1970,15 +2057,16 @@ ] }, "shr eax, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ "lsr w20, w4, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x1c", + "cbz w0, #+0x20", "ands w26, w20, w20", "sub x0, x5, #0x1 (1)", "lsr w0, w4, w0", + "mvn x0, x0", "eor w2, w4, w20", "rmif x0, #63, #nzCv", "rmif x2, #31, #nzcV", @@ -1986,15 +2074,16 @@ ] }, "shr rax, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ "lsr x20, x4, x5", "and w0, w5, #0x3f", - "cbz x0, #+0x1c", + "cbz x0, #+0x20", "ands x26, x20, x20", "sub x0, x5, #0x1 (1)", "lsr x0, x4, x0", + "mvn x0, x0", "eor x2, x4, x20", "rmif x0, #63, #nzCv", "rmif x2, #63, #nzcV", @@ -2002,55 +2091,59 @@ ] }, "sar ax, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ "sxth x20, w4", "asr w21, w20, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x18", + "cbz w0, #+0x1c", "cmn wzr, w21, lsl #16", "mov x26, x21", "sub x0, x5, #0x1 (1)", "lsr w0, w20, w0", + "mvn x0, x0", "rmif x0, #63, #nzCv", "bfxil x4, x21, #0, #16" ] }, "sar eax, cl": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ "asr w20, w4, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x14", + "cbz w0, #+0x18", "ands w26, w20, w20", "sub x0, x5, #0x1 (1)", "lsr w0, w4, w0", + "mvn x0, x0", "rmif x0, #63, #nzCv", "mov x4, x20" ] }, "sar rax, cl": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ "asr x20, x4, x5", "and w0, w5, #0x3f", - "cbz x0, #+0x14", + "cbz x0, #+0x18", "ands x26, x20, x20", "sub x0, x5, #0x1 (1)", "lsr x0, x4, x0", + "mvn x0, x0", "rmif x0, #63, #nzCv", "mov x4, x20" ] }, "test bl, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xf6 /0", "ExpectedArm64ASM": [ "and w26, w7, #0x1", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "not bl": { @@ -2061,12 +2154,11 @@ ] }, "neg bl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ "cmp wzr, w7, lsl #24", "neg w26, w7", - "cfinv", "mov x20, x7", "bfxil x20, x26, #0, #8", "mov x27, x7", @@ -2083,7 +2175,7 @@ "bfxil x4, x20, #0, #16", "ubfx x20, x20, #8, #8", "cmp x20, #0x0 (0)", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul bl": { @@ -2097,7 +2189,7 @@ "sbfx x21, x20, #8, #8", "sbfx x20, x20, #7, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "div bl": { @@ -2133,56 +2225,61 @@ ] }, "test bx, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ "and w26, w7, #0x1", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "test ebx, 1": { - "ExpectedInstructionCount": 1, - "Comment": "GROUP2 0xf7 /0", - "ExpectedArm64ASM": [ - "ands w26, w7, #0x1" - ] - }, - "test rbx, 1": { - "ExpectedInstructionCount": 1, - "Comment": "GROUP2 0xf7 /0", - "ExpectedArm64ASM": [ - "ands x26, x7, #0x1" - ] - }, - "test bx, -1": { "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "ands w26, w7, #0x1", + "cfinv" + ] + }, + "test rbx, 1": { + "ExpectedInstructionCount": 2, + "Comment": "GROUP2 0xf7 /0", + "ExpectedArm64ASM": [ + "ands x26, x7, #0x1", + "cfinv" + ] + }, + "test bx, -1": { + "ExpectedInstructionCount": 3, + "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ "mov x26, x7", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "cfinv" ] }, "test ebx, -1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "ands w26, w7, w7" + "ands w26, w7, w7", + "cfinv" ] }, "test rbx, -1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "ands x26, x7, x7" + "ands x26, x7, x7", + "cfinv" ] }, "neg bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "cmp wzr, w7, lsl #16", "neg w26, w7", - "cfinv", "mov x20, x7", "bfxil x20, x26, #0, #16", "mov x27, x7", @@ -2190,21 +2287,19 @@ ] }, "neg ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "negs w26, w7", - "cfinv", "mov x27, x7", "mov x7, x26" ] }, "neg rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "negs x26, x7", - "cfinv", "mov x27, x7", "mov x7, x26" ] @@ -2220,7 +2315,7 @@ "ubfx x20, x20, #16, #16", "bfxil x6, x20, #0, #16", "cmp x20, #0x0 (0)", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "mul ebx": { @@ -2233,7 +2328,7 @@ "mov w4, w20", "lsr x6, x20, #32", "cmp x6, #0x0 (0)", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "mul rbx": { @@ -2243,7 +2338,7 @@ "mul x20, x7, x4", "umulh x6, x7, x4", "cmp x6, #0x0 (0)", - "ccmn xzr, #0, #nzCV, eq", + "ccmp xzr, #0, #nzcV, eq", "mov x4, x20" ] }, @@ -2259,7 +2354,7 @@ "bfxil x6, x21, #0, #16", "sbfx x20, x20, #15, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul ebx": { @@ -2275,7 +2370,7 @@ "sxtw x20, w20", "sbfx x20, x20, #31, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul rbx": { @@ -2286,7 +2381,7 @@ "mul x4, x7, x4", "asr x20, x4, #63", "cmp x6, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "div bx": { diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json index 4fa69a3d9..e9e1b3e84 100644 --- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json @@ -96,14 +96,14 @@ "ubfx w23, w23, #4, #1", "orr x22, x23, x22", "cmp x20, #0x99 (153)", - "cset x23, hi", - "orr x21, x21, x23", + "cset x23, ls", + "and x21, x21, x23", "add x23, x20, #0x6 (6)", "cmp x22, #0x0 (0)", "csel x20, x23, x20, ne", "add x23, x20, #0x60 (96)", "cmp x21, #0x0 (0)", - "csel x26, x23, x20, ne", + "csel x26, x23, x20, eq", "bfxil w4, w26, #0, #8", "cmn wzr, w26, lsl #24", "rmif x21, #63, #nzCv", @@ -111,11 +111,11 @@ ] }, "das": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 25, "Comment": "0x2f", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, hs", + "cset w21, lo", "and x22, x20, #0xf", "cmp x22, #0x9 (9)", "cset x22, hi", @@ -136,12 +136,13 @@ "csel x26, x24, x20, ne", "bfxil w4, w26, #0, #8", "cmn wzr, w26, lsl #24", - "rmif x23, #63, #nzCv", + "eor x20, x23, #0x1", + "rmif x20, #63, #nzCv", "eor w27, w26, w22, lsl #4" ] }, "aaa": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": "0x37", "ExpectedArm64ASM": [ "and x20, x4, #0xf", @@ -150,18 +151,19 @@ "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x21, x20", - "lsl x21, x20, #29", + "eor x21, x20, #0x1", + "lsl x21, x21, #29", "eor w27, w26, w20, lsl #4", "msr nzcv, x21", "add w20, w4, #0x106 (262)", - "csel w20, w20, w4, hs", + "csel w20, w20, w4, lo", "mov w21, #0xff0f", "and w20, w20, w21", "bfxil w4, w20, #0, #16" ] }, "aas": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": "0x3f", "ExpectedArm64ASM": [ "and x20, x4, #0xf", @@ -170,11 +172,12 @@ "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x21, x20", - "lsl x21, x20, #29", + "eor x21, x20, #0x1", + "lsl x21, x21, #29", "eor w27, w26, w20, lsl #4", "msr nzcv, x21", "sub w20, w4, #0x106 (262)", - "csel w20, w20, w4, hs", + "csel w20, w20, w4, lo", "mov w21, #0xff0f", "and w20, w20, w21", "bfxil w4, w20, #0, #16" @@ -313,7 +316,7 @@ ] }, "aam": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0xd4", "ExpectedArm64ASM": [ "uxtb w20, w4", @@ -323,11 +326,12 @@ "msub x20, x2, x21, x20", "add x26, x20, x22, lsl #8", "bfxil w4, w26, #0, #16", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "aad": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0xd5", "ExpectedArm64ASM": [ "lsr w20, w4, #8", @@ -336,11 +340,12 @@ "add x20, x4, x20", "and x26, x20, #0xff", "bfxil w4, w26, #0, #16", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "db 0xd4, 0x40": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": [ "aam with a different immediate byte base", "0xd4" @@ -353,11 +358,12 @@ "msub x20, x2, x21, x20", "add x26, x20, x22, lsl #8", "bfxil w4, w26, #0, #16", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "db 0xd5, 0x40": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": [ "aad with a different immediate byte base", "0xd5" @@ -368,14 +374,15 @@ "add x20, x4, x20", "and x26, x20, #0xff", "bfxil w4, w26, #0, #16", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "cfinv" ] }, "salc": { "ExpectedInstructionCount": 2, "Comment": "0xd6", "ExpectedArm64ASM": [ - "csetm w20, hs", + "csetm w20, lo", "bfxil w4, w20, #0, #8" ] } diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 6311629e1..a39c305c6 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -14,25 +14,23 @@ }, "Instructions": { "ucomiss xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0x2e", "ExpectedArm64ASM": [ "fcmp s16, s17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "comiss xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0x2f", "ExpectedArm64ASM": [ "fcmp s16, s17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "cmovo ax, bx": { @@ -83,7 +81,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0x42", "ExpectedArm64ASM": [ - "csel w20, w7, w4, hs", + "csel w20, w7, w4, lo", "bfxil x4, x20, #0, #16" ] }, @@ -91,21 +89,21 @@ "ExpectedInstructionCount": 1, "Comment": "0x0f 0x42", "ExpectedArm64ASM": [ - "csel w4, w7, w4, hs" + "csel w4, w7, w4, lo" ] }, "cmovb rax, rbx": { "ExpectedInstructionCount": 1, "Comment": "0x0f 0x42", "ExpectedArm64ASM": [ - "csel x4, x7, x4, hs" + "csel x4, x7, x4, lo" ] }, "cmovnb ax, bx": { "ExpectedInstructionCount": 2, "Comment": "0x0f 0x43", "ExpectedArm64ASM": [ - "csel w20, w7, w4, lo", + "csel w20, w7, w4, hs", "bfxil x4, x20, #0, #16" ] }, @@ -113,14 +111,14 @@ "ExpectedInstructionCount": 1, "Comment": "0x0f 0x43", "ExpectedArm64ASM": [ - "csel w4, w7, w4, lo" + "csel w4, w7, w4, hs" ] }, "cmovnb rax, rbx": { "ExpectedInstructionCount": 1, "Comment": "0x0f 0x43", "ExpectedArm64ASM": [ - "csel x4, x7, x4, lo" + "csel x4, x7, x4, hs" ] }, "cmovz ax, bx": { @@ -168,53 +166,47 @@ ] }, "cmovbe ax, bx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x0f 0x46", "ExpectedArm64ASM": [ - "csel w20, w7, w4, hs", - "csel w20, w7, w20, eq", + "csel w20, w7, w4, ls", "bfxil x4, x20, #0, #16" ] }, "cmovbe eax, ebx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0x0f 0x46", "ExpectedArm64ASM": [ - "csel w20, w7, w4, hs", - "csel w4, w7, w20, eq" + "csel w4, w7, w4, ls" ] }, "cmovbe rax, rbx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0x0f 0x46", "ExpectedArm64ASM": [ - "csel x20, x7, x4, hs", - "csel x4, x7, x20, eq" + "csel x4, x7, x4, ls" ] }, "cmovnbe ax, bx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x0f 0x47", "ExpectedArm64ASM": [ - "csel w20, w7, w4, lo", - "csel w20, w20, w4, ne", + "csel w20, w7, w4, hi", "bfxil x4, x20, #0, #16" ] }, "cmovnbe eax, ebx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0x0f 0x47", "ExpectedArm64ASM": [ - "csel w20, w7, w4, lo", - "csel w4, w20, w4, ne" + "csel w4, w7, w4, hi" ] }, "cmovnbe rax, rbx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0x0f 0x47", "ExpectedArm64ASM": [ - "csel x20, x7, x4, lo", - "csel x4, x20, x4, ne" + "csel x4, x7, x4, hi" ] }, "cmovs ax, bx": { @@ -449,7 +441,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0x92", "ExpectedArm64ASM": [ - "cset x20, hs", + "cset x20, lo", "bfxil x4, x20, #0, #8" ] }, @@ -457,7 +449,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0x93", "ExpectedArm64ASM": [ - "cset x20, lo", + "cset x20, hs", "bfxil x4, x20, #0, #8" ] }, @@ -478,21 +470,18 @@ ] }, "setbe al": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 2, "Comment": "0x0f 0x96", "ExpectedArm64ASM": [ - "mov w20, #0x1", - "cset x21, hs", - "csel x20, x20, x21, eq", + "cset x20, ls", "bfxil x4, x20, #0, #8" ] }, "setnbe al": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x0f 0x97", "ExpectedArm64ASM": [ - "cset x20, lo", - "csel x20, x20, xzr, ne", + "cset x20, hi", "bfxil x4, x20, #0, #8" ] }, @@ -567,65 +556,71 @@ ] }, "bt ax, bx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "and x20, x7, #0xf", "lsr w20, w4, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bt [rax], bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", "sbfx x21, x7, #3, #13", "ldrb w21, [x4, x21, sxtx]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bt eax, ebx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "lsr w20, w4, w7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bt [rax], ebx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", "sbfx x21, x7, #3, #29", "ldrb w21, [x4, x21, sxtx]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bt rax, rbx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "lsr x20, x4, x7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bt [rax], rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", "asr x21, x7, #3", "ldrb w21, [x4, x21, sxtx]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "shld ax, bx, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -634,14 +629,15 @@ "lsr w20, w20, #15", "orr x26, x22, x20", "cmn wzr, w26, lsl #16", - "rmif x21, #14, #nzCv", + "eor x20, x21, #0x8000", + "rmif x20, #14, #nzCv", "eor w20, w26, w21", "rmif x20, #15, #nzcV", "bfxil x4, x26, #0, #16" ] }, "shld ax, bx, 15": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -650,12 +646,13 @@ "lsr w20, w20, #1", "orr x26, x22, x20", "cmn wzr, w26, lsl #16", - "rmif x21, #0, #nzCv", + "eor x20, x21, #0x2", + "rmif x20, #0, #nzCv", "bfxil x4, x26, #0, #16" ] }, "shld ax, bx, 16": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -663,11 +660,12 @@ "lsl x21, x21, #16", "orr x26, x21, x20", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "shld ax, bx, 31": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -676,95 +674,104 @@ "lsr w20, w20, #17", "orr x26, x21, x20", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "shld eax, ebx, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr w26, w4, w7, #31", - "tst w26, w26", - "rmif x4, #30, #nzCv", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x80000000", + "rmif x20, #30, #nzCv", "eor w20, w26, w4", "rmif x20, #31, #nzcV", "mov x4, x26" ] }, "shld eax, ebx, 15": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr w26, w4, w7, #17", - "tst w26, w26", - "rmif x4, #16, #nzCv", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x20000", + "rmif x20, #16, #nzCv", "mov x4, x26" ] }, "shld eax, ebx, 16": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr w26, w4, w7, #16", - "tst w26, w26", - "rmif x4, #15, #nzCv", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x10000", + "rmif x20, #15, #nzCv", "mov x4, x26" ] }, "shld eax, ebx, 31": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr w26, w4, w7, #1", - "tst w26, w26", - "rmif x4, #0, #nzCv", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x2", + "rmif x20, #0, #nzCv", "mov x4, x26" ] }, "shld rax, rbx, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr x26, x4, x7, #63", - "tst x26, x26", - "rmif x4, #62, #nzCv", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x8000000000000000", + "rmif x20, #62, #nzCv", "eor x20, x26, x4", "rmif x20, #63, #nzcV", "mov x4, x26" ] }, "shld rax, rbx, 15": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr x26, x4, x7, #49", - "tst x26, x26", - "rmif x4, #48, #nzCv", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x2000000000000", + "rmif x20, #48, #nzCv", "mov x4, x26" ] }, "shld rax, rbx, 32": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr x26, x4, x7, #32", - "tst x26, x26", - "rmif x4, #31, #nzCv", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x100000000", + "rmif x20, #31, #nzCv", "mov x4, x26" ] }, "shld rax, rbx, 63": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr x26, x4, x7, #1", - "tst x26, x26", - "rmif x4, #0, #nzCv", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x2", + "rmif x20, #0, #nzCv", "mov x4, x26" ] }, "shld ax, bx, cl": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 21, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -780,17 +787,18 @@ "csel x20, x21, x20, eq", "msr nzcv, x23", "and w0, w22, #0x1f", - "cbz w0, #+0x18", + "cbz w0, #+0x1c", "cmn wzr, w20, lsl #16", "mov x26, x20", + "mvn x0, x20", "eor w2, w21, w20", - "rmif x20, #15, #nzCv", + "rmif x0, #15, #nzCv", "rmif x2, #15, #nzcV", "bfxil x4, x20, #0, #16" ] }, "shld eax, ebx, cl": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 21, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "mov w20, w7", @@ -805,10 +813,11 @@ "csel x20, x21, x20, eq", "msr nzcv, x23", "and w0, w22, #0x1f", - "cbz w0, #+0x1c", + "cbz w0, #+0x20", "ands w26, w20, w20", "neg w0, w22", "lsr w0, w21, w0", + "mvn x0, x0", "eor w2, w21, w20", "rmif x0, #63, #nzCv", "rmif x2, #31, #nzcV", @@ -816,7 +825,7 @@ ] }, "shld rax, rbx, cl": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 19, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "and x20, x5, #0x3f", @@ -829,10 +838,11 @@ "csel x21, x4, x21, eq", "msr nzcv, x22", "and w0, w20, #0x3f", - "cbz x0, #+0x1c", + "cbz x0, #+0x20", "ands x26, x21, x21", "neg x0, x20", "lsr x0, x4, x0", + "mvn x0, x0", "eor x2, x4, x21", "rmif x0, #63, #nzCv", "rmif x2, #63, #nzcV", @@ -840,11 +850,12 @@ ] }, "bts ax, bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "and x20, x7, #0xf", "lsr w21, w4, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "mov w21, #0x1", "lsl w20, w21, w20", @@ -853,7 +864,7 @@ ] }, "bts [rax], bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -864,14 +875,16 @@ "orr x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bts eax, ebx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "lsr w20, w4, w7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv", "mov w20, #0x1", "lsl w20, w20, w7", @@ -879,7 +892,7 @@ ] }, "bts [rax], ebx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -890,14 +903,16 @@ "orr x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bts rax, rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "lsr x20, x4, x7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv", "mov w20, #0x1", "lsl x20, x20, x7", @@ -905,7 +920,7 @@ ] }, "bts [rax], rbx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -916,11 +931,12 @@ "orr x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock bts [rax], bx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -930,11 +946,12 @@ "add x21, x4, x21", "ldsetalb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock bts [rax], ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -944,11 +961,12 @@ "add x21, x4, x21", "ldsetalb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock bts [rax], rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -958,6 +976,7 @@ "add x21, x4, x21", "ldsetalb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, @@ -972,7 +991,7 @@ "bfxil x4, x20, #0, #16", "sbfx x20, x20, #15, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul eax, ebx": { @@ -984,7 +1003,7 @@ "mul w4, w4, w7", "sbfx x21, x4, #31, #1", "cmp x20, x21", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul rax, rbx": { @@ -995,7 +1014,7 @@ "mul x4, x4, x7", "asr x21, x4, #63", "cmp x20, x21", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul rsi, rax, 0xffffffff8646c299": { @@ -1008,11 +1027,11 @@ "mul x10, x4, x20", "asr x20, x10, #63", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "cmpxchg cl, bl": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "ExpectedArm64ASM": [ "uxtb w20, w7", "uxtb w21, w5", @@ -1021,14 +1040,13 @@ "lsl w0, w22, #24", "cmp w0, w21, lsl #24", "sub w26, w22, w21", - "cfinv", "bfxil x4, x21, #0, #8", "csel x20, x20, x21, eq", "bfxil x5, x20, #0, #8" ] }, "cmpxchg cx, bx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "ExpectedArm64ASM": [ "uxth w20, w7", "uxth w21, w5", @@ -1037,31 +1055,28 @@ "lsl w0, w22, #16", "cmp w0, w21, lsl #16", "sub w26, w22, w21", - "cfinv", "bfxil x4, x21, #0, #16", "csel x20, x20, x21, eq", "bfxil x5, x20, #0, #16" ] }, "cmpxchg ecx, ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "ExpectedArm64ASM": [ "mov w20, w7", "mov w21, w5", "mov w22, w4", "eor w27, w22, w21", "subs w26, w22, w21", - "cfinv", "csel x4, x4, x21, eq", "csel x5, x20, x5, eq" ] }, "cmpxchg rcx, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "ExpectedArm64ASM": [ "eor w27, w4, w5", "subs x26, x4, x5", - "cfinv", "csel x20, x7, x5, eq", "mov x21, x5", "mov x5, x20", @@ -1069,7 +1084,7 @@ ] }, "cmpxchg [rax], rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov x1, x4", @@ -1077,12 +1092,11 @@ "mov x20, x1", "eor w27, w4, w20", "subs x26, x4, x20", - "cfinv", "mov x4, x20" ] }, "cmpxchg al, bl": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xb0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -1092,12 +1106,11 @@ "lsl w0, w22, #24", "cmp w0, w21, lsl #24", "sub w26, w22, w21", - "cfinv", "bfxil x4, x20, #0, #8" ] }, "cmpxchg [rax], bl": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -1109,12 +1122,11 @@ "lsl w0, w21, #24", "cmp w0, w20, lsl #24", "sub w26, w21, w20", - "cfinv", "bfxil x4, x20, #0, #8" ] }, "cmpxchg ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1124,12 +1136,11 @@ "lsl w0, w22, #16", "cmp w0, w21, lsl #16", "sub w26, w22, w21", - "cfinv", "bfxil x4, x20, #0, #16" ] }, "cmpxchg [rax], bx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1141,12 +1152,11 @@ "lsl w0, w21, #16", "cmp w0, w20, lsl #16", "sub w26, w21, w20", - "cfinv", "bfxil x4, x20, #0, #16" ] }, "cmpxchg eax, ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", @@ -1154,12 +1164,11 @@ "mov w22, w4", "eor w27, w22, w21", "subs w26, w22, w21", - "cfinv", "mov x4, x20" ] }, "cmpxchg [rax], ebx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", @@ -1170,26 +1179,25 @@ "cmp w20, w21", "csel x4, x4, x20, eq", "eor w27, w21, w20", - "subs w26, w21, w20", - "cfinv" + "subs w26, w21, w20" ] }, "cmpxchg rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w27, #0x0", "subs x26, x4, x4", - "cfinv", "mov x4, x7" ] }, "btr ax, bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "and x20, x7, #0xf", "lsr w21, w4, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "mov w21, #0x1", "lsl w20, w21, w20", @@ -1198,7 +1206,7 @@ ] }, "btr [rax], bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1209,14 +1217,16 @@ "bic x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btr eax, ebx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "lsr w20, w4, w7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv", "mov w20, #0x1", "lsl w20, w20, w7", @@ -1224,7 +1234,7 @@ ] }, "btr [rax], ebx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1235,14 +1245,16 @@ "bic x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btr rax, rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "lsr x20, x4, x7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv", "mov w20, #0x1", "lsl x20, x20, x7", @@ -1250,7 +1262,7 @@ ] }, "btr [rax], rbx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1261,11 +1273,12 @@ "bic x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btr [rax], bx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1275,11 +1288,12 @@ "add x21, x4, x21", "ldclralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btr [rax], ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1289,11 +1303,12 @@ "add x21, x4, x21", "ldclralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btr [rax], rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1303,15 +1318,17 @@ "add x21, x4, x21", "ldclralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btc ax, bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "and x20, x7, #0xf", "lsr w21, w4, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "mov w21, #0x1", "lsl w20, w21, w20", @@ -1320,7 +1337,7 @@ ] }, "btc [rax], bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1331,14 +1348,16 @@ "eor x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btc eax, ebx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "lsr w20, w4, w7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv", "mov w20, #0x1", "lsl w20, w20, w7", @@ -1346,7 +1365,7 @@ ] }, "btc [rax], ebx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1357,14 +1376,16 @@ "eor x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btc rax, rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "lsr x20, x4, x7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv", "mov w20, #0x1", "lsl x20, x20, x7", @@ -1372,7 +1393,7 @@ ] }, "btc [rax], rbx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1383,11 +1404,12 @@ "eor x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btc [rax], bx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1397,11 +1419,12 @@ "add x21, x4, x21", "ldeoralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btc [rax], ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1411,11 +1434,12 @@ "add x21, x4, x21", "ldeoralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btc [rax], rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1425,11 +1449,12 @@ "add x21, x4, x21", "ldeoralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bsf ax, bx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xbc", "ExpectedArm64ASM": [ "uxth w20, w4", @@ -1441,7 +1466,8 @@ "csinv w22, w22, wzr, ne", "cmn wzr, w21, lsl #16", "csel x20, x20, x22, eq", - "bfxil x4, x20, #0, #16" + "bfxil x4, x20, #0, #16", + "cfinv" ] }, "bsf eax, ebx": { @@ -1454,7 +1480,7 @@ "rbit w0, w0", "clz w21, w0", "csinv w21, w21, wzr, ne", - "tst w20, w20", + "cmp w20, #0x0 (0)", "csel x4, x4, x21, eq" ] }, @@ -1466,12 +1492,12 @@ "cmp x7, #0x0 (0)", "clz x20, x0", "csinv x20, x20, xzr, ne", - "tst x7, x7", + "cmp x7, #0x0 (0)", "csel x4, x4, x20, eq" ] }, "bsr ax, bx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xbd", "ExpectedArm64ASM": [ "uxth w20, w4", @@ -1483,7 +1509,8 @@ "sub x22, x0, x22", "cmn wzr, w21, lsl #16", "csel x20, x20, x22, eq", - "bfxil x4, x20, #0, #16" + "bfxil x4, x20, #0, #16", + "cfinv" ] }, "bsr eax, ebx": { @@ -1494,7 +1521,7 @@ "mov x0, #0x1f", "clz w21, w20", "sub x21, x0, x21", - "tst w20, w20", + "cmp w20, #0x0 (0)", "csel x4, x4, x21, eq" ] }, @@ -1505,12 +1532,12 @@ "mov x0, #0x3f", "clz x20, x7", "sub x20, x0, x20", - "tst x7, x7", + "cmp x7, #0x0 (0)", "csel x4, x4, x20, eq" ] }, "xadd al, bl": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w4", @@ -1520,11 +1547,12 @@ "cmn w0, w21, lsl #24", "add w26, w20, w21", "bfxil x7, x20, #0, #8", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "cfinv" ] }, "xadd [rax], bl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -1533,11 +1561,12 @@ "lsl w0, w21, #24", "cmn w0, w20, lsl #24", "add w26, w21, w20", - "bfxil x7, x21, #0, #8" + "bfxil x7, x21, #0, #8", + "cfinv" ] }, "xadd ax, bx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w4", @@ -1547,11 +1576,12 @@ "cmn w0, w21, lsl #16", "add w26, w20, w21", "bfxil x7, x20, #0, #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "cfinv" ] }, "xadd [rax], bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1560,48 +1590,53 @@ "lsl w0, w21, #16", "cmn w0, w20, lsl #16", "add w26, w21, w20", - "bfxil x7, x21, #0, #16" + "bfxil x7, x21, #0, #16", + "cfinv" ] }, "xadd eax, ebx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w4", "mov w21, w7", "eor w27, w20, w21", "adds w26, w20, w21", + "cfinv", "mov x7, x20", "mov x4, x26" ] }, "xadd [rax], ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", "eor w27, w7, w20", - "adds w26, w7, w20" + "adds w26, w7, w20", + "cfinv" ] }, "xadd rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "eor w27, w4, w7", "adds x26, x4, x7", + "cfinv", "mov x7, x4", "mov x4, x26" ] }, "xadd [rax], rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "ldaddal x7, x20, [x4]", "eor w27, w20, w7", "adds x26, x20, x7", + "cfinv", "mov x7, x20" ] }, diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index a7366d870..0866b4729 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -24,623 +24,689 @@ ] }, "bt ax, 0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv" + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv" ] }, "bt eax, 0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv" + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv" ] }, "bt rax, 0": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv" + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv" ] }, "bt ax, 15": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "rmif x4, #14, #nzCv" + "eor x20, x4, #0x8000", + "rmif x20, #14, #nzCv" ] }, "bt eax, 31": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "rmif x4, #30, #nzCv" + "eor x20, x4, #0x80000000", + "rmif x20, #30, #nzCv" ] }, "bt rax, 63": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "rmif x4, #62, #nzCv" + "eor x20, x4, #0x8000000000000000", + "rmif x20, #62, #nzCv" ] }, "bt word [rax], 0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bt dword [rax], 0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bt qword [rax], 0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bt word [rax], 15": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bt dword [rax], 31": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bt qword [rax], 63": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bts ax, 0": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "orr w20, w4, #0x1", "bfxil x4, x20, #0, #16" ] }, "bts eax, 0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "orr w4, w4, #0x1" ] }, "bts rax, 0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "orr x4, x4, #0x1" ] }, "bts ax, 15": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "rmif x4, #14, #nzCv", + "eor x20, x4, #0x8000", + "rmif x20, #14, #nzCv", "orr w20, w4, #0x8000", "bfxil x4, x20, #0, #16" ] }, "bts eax, 31": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "rmif x4, #30, #nzCv", + "eor x20, x4, #0x80000000", + "rmif x20, #30, #nzCv", "orr w4, w4, #0x80000000" ] }, "bts rax, 63": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "rmif x4, #62, #nzCv", + "eor x20, x4, #0x8000000000000000", + "rmif x20, #62, #nzCv", "orr x4, x4, #0x8000000000000000" ] }, "bts word [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "orr x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bts dword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "orr x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bts qword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "orr x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bts word [rax], 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", "orr x21, x20, #0x80", "strb w21, [x4, #1]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bts dword [rax], 31": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", "orr x21, x20, #0x80", "strb w21, [x4, #3]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "bts qword [rax], 63": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", "orr x21, x20, #0x80", "strb w21, [x4, #7]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock bts word [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldsetalb w20, w20, [x21]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock bts dword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldsetalb w20, w20, [x21]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock bts qword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldsetalb w20, w20, [x21]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock bts word [rax], 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x1 (1)", "ldsetalb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock bts dword [rax], 31": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x3 (3)", "ldsetalb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock bts qword [rax], 63": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x7 (7)", "ldsetalb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btr ax, 0": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "and w20, w4, #0xfffffffe", "bfxil x4, x20, #0, #16" ] }, "btr eax, 0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "and w4, w4, #0xfffffffe" ] }, "btr rax, 0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "and x4, x4, #0xfffffffffffffffe" ] }, "btr ax, 15": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "rmif x4, #14, #nzCv", + "eor x20, x4, #0x8000", + "rmif x20, #14, #nzCv", "and w20, w4, #0xffff7fff", "bfxil x4, x20, #0, #16" ] }, "btr eax, 31": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "rmif x4, #30, #nzCv", + "eor x20, x4, #0x80000000", + "rmif x20, #30, #nzCv", "and w4, w4, #0x7fffffff" ] }, "btr rax, 63": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "rmif x4, #62, #nzCv", + "eor x20, x4, #0x8000000000000000", + "rmif x20, #62, #nzCv", "and x4, x4, #0x7fffffffffffffff" ] }, "btr word [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "and x21, x20, #0xfffffffffffffffe", "strb w21, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btr dword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "and x21, x20, #0xfffffffffffffffe", "strb w21, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btr qword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "and x21, x20, #0xfffffffffffffffe", "strb w21, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btr word [rax], 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", "and x21, x20, #0xffffffffffffff7f", "strb w21, [x4, #1]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btr dword [rax], 31": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", "and x21, x20, #0xffffffffffffff7f", "strb w21, [x4, #3]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btr qword [rax], 63": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", "and x21, x20, #0xffffffffffffff7f", "strb w21, [x4, #7]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btr word [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldclralb w20, w20, [x21]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btr dword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldclralb w20, w20, [x21]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btr qword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldclralb w20, w20, [x21]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btr word [rax], 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x1 (1)", "ldclralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btr dword [rax], 31": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x3 (3)", "ldclralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btr qword [rax], 63": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x7 (7)", "ldclralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btc ax, 0": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "eor w20, w4, #0x1", "bfxil x4, x20, #0, #16" ] }, "btc eax, 0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "eor w4, w4, #0x1" ] }, "btc rax, 0": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "rmif x4, #63, #nzCv", + "eor x20, x4, #0x1", + "rmif x20, #63, #nzCv", "eor x4, x4, #0x1" ] }, "btc ax, 15": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "rmif x4, #14, #nzCv", + "eor x20, x4, #0x8000", + "rmif x20, #14, #nzCv", "eor w20, w4, #0x8000", "bfxil x4, x20, #0, #16" ] }, "btc eax, 31": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "rmif x4, #30, #nzCv", + "eor x20, x4, #0x80000000", + "rmif x20, #30, #nzCv", "eor w4, w4, #0x80000000" ] }, "btc rax, 63": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "rmif x4, #62, #nzCv", + "eor x20, x4, #0x8000000000000000", + "rmif x20, #62, #nzCv", "eor x4, x4, #0x8000000000000000" ] }, "btc word [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "eor x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btc dword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "eor x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btc qword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "eor x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btc word [rax], 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", "eor x21, x20, #0x80", "strb w21, [x4, #1]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btc dword [rax], 31": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", "eor x21, x20, #0x80", "strb w21, [x4, #3]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "btc qword [rax], 63": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", "eor x21, x20, #0x80", "strb w21, [x4, #7]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btc word [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldeoralb w20, w20, [x21]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btc dword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldeoralb w20, w20, [x21]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btc qword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldeoralb w20, w20, [x21]", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btc word [rax], 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x1 (1)", "ldeoralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btc dword [rax], 31": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x3 (3)", "ldeoralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, "lock btc qword [rax], 63": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x7 (7)", "ldeoralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] }, @@ -695,87 +761,73 @@ ] }, "rdrand ax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", - "cset x21, ne", - "mov x22, x21", "bfxil x4, x20, #0, #16", - "mov w27, #0x0", "mov w26, #0x1", - "lsl x20, x22, #29", - "msr nzcv, x20" + "mov w27, #0x0", + "cset w20, eq", + "rmif x20, #63, #NZCV" ] }, "rdrand eax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", - "cset x21, ne", - "mov x22, x21", "mov w4, w20", - "mov w27, #0x0", "mov w26, #0x1", - "lsl x20, x22, #29", - "msr nzcv, x20" + "mov w27, #0x0", + "cset w20, eq", + "rmif x20, #63, #NZCV" ] }, "rdrand rax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "mrs x20, rndr", - "cset x21, ne", - "mov x22, x21", - "mov x4, x20", - "mov w27, #0x0", + "mrs x4, rndr", "mov w26, #0x1", - "lsl x20, x22, #29", - "msr nzcv, x20" + "mov w27, #0x0", + "cset w20, eq", + "rmif x20, #63, #NZCV" ] }, "rdseed ax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", - "cset x21, ne", - "mov x22, x21", "bfxil x4, x20, #0, #16", - "mov w27, #0x0", "mov w26, #0x1", - "lsl x20, x22, #29", - "msr nzcv, x20" + "mov w27, #0x0", + "cset w20, eq", + "rmif x20, #63, #NZCV" ] }, "rdseed eax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", - "cset x21, ne", - "mov x22, x21", "mov w4, w20", - "mov w27, #0x0", "mov w26, #0x1", - "lsl x20, x22, #29", - "msr nzcv, x20" + "mov w27, #0x0", + "cset w20, eq", + "rmif x20, #63, #NZCV" ] }, "rdseed rax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ - "mrs x20, rndrrs", - "cset x21, ne", - "mov x22, x21", - "mov x4, x20", - "mov w27, #0x0", + "mrs x4, rndrrs", "mov w26, #0x1", - "lsl x20, x22, #29", - "msr nzcv, x20" + "mov w27, #0x0", + "cset w20, eq", + "rmif x20, #63, #NZCV" ] }, "psrlw mm0, 0": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index 401d7b4bb..723429cbe 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -14,25 +14,23 @@ }, "Instructions": { "ucomisd xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x66 0x0f 0x2e", "ExpectedArm64ASM": [ "fcmp d16, d17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "comisd xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "0x66 0x0f 0x2f", "ExpectedArm64ASM": [ "fcmp d16, d17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "pmovmskb eax, xmm0": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json index d31556cba..246f3439b 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json @@ -23,9 +23,9 @@ "addp v0.8b, v0.8b, v0.8b", "umov w20, v0.b[0]", "bfxil x4, x20, #0, #16", - "tst w20, w20", - "mov w26, #0x1", - "mov w27, #0x0" + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "mov w26, #0x1" ] }, "popcnt eax, ebx": { @@ -36,9 +36,9 @@ "cnt v0.8b, v0.8b", "addv b0, v0.8b", "umov w4, v0.b[0]", - "tst w4, w4", - "mov w26, #0x1", - "mov w27, #0x0" + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "mov w26, #0x1" ] }, "popcnt rax, rbx": { @@ -49,13 +49,13 @@ "cnt v0.8b, v0.8b", "addv b0, v0.8b", "umov w4, v0.b[0]", - "tst w4, w4", - "mov w26, #0x1", - "mov w27, #0x0" + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "mov w26, #0x1" ] }, "tzcnt ax, bx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "0xf3 0x0f 0xbc", "ExpectedArm64ASM": [ "rbit w20, w7", @@ -63,31 +63,34 @@ "clz w20, w20", "bfxil x4, x20, #0, #16", "cmn wzr, w20, lsl #16", + "eor x20, x20, #0x10", "rmif x20, #3, #nzCv" ] }, "tzcnt eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0xf3 0x0f 0xbc", "ExpectedArm64ASM": [ "rbit w4, w7", "clz w4, w4", - "tst w4, w4", - "rmif x4, #4, #nzCv" + "cmp w4, #0x0 (0)", + "eor x20, x4, #0x20", + "rmif x20, #4, #nzCv" ] }, "tzcnt rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0xf3 0x0f 0xbc", "ExpectedArm64ASM": [ "rbit x4, x7", "clz x4, x4", - "tst x4, x4", - "rmif x4, #5, #nzCv" + "cmp x4, #0x0 (0)", + "eor x20, x4, #0x40", + "rmif x20, #5, #nzCv" ] }, "lzcnt ax, bx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "0xf3 0x0f 0xbd", "ExpectedArm64ASM": [ "lsl w20, w7, #16", @@ -95,25 +98,28 @@ "clz w20, w20", "bfxil x4, x20, #0, #16", "cmn wzr, w20, lsl #16", + "eor x20, x20, #0x10", "rmif x20, #3, #nzCv" ] }, "lzcnt eax, ebx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0xf3 0x0f 0xbd", "ExpectedArm64ASM": [ "clz w4, w7", - "tst w4, w4", - "rmif x4, #4, #nzCv" + "cmp w4, #0x0 (0)", + "eor x20, x4, #0x20", + "rmif x20, #4, #nzCv" ] }, "lzcnt rax, rbx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "0xf3 0x0f 0xbd", "ExpectedArm64ASM": [ "clz x4, x7", - "tst x4, x4", - "rmif x4, #5, #nzCv" + "cmp x4, #0x0 (0)", + "eor x20, x4, #0x40", + "rmif x20, #5, #nzCv" ] } } diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index b3b689998..a8c31ebc8 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -15,7 +15,7 @@ }, "Instructions": { "vucomiss xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": [ "Map 1 0b00 0x2e 128-bit" ], @@ -23,12 +23,11 @@ "fcmp s16, s17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "vucomisd xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": [ "Map 1 0b01 0x2e 128-bit" ], @@ -36,12 +35,11 @@ "fcmp d16, d17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "vcomiss xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": [ "Map 1 0b00 0x2f 128-bit" ], @@ -49,12 +47,11 @@ "fcmp s16, s17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "vcomisd xmm0, xmm1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": [ "Map 1 0b01 0x2f 128-bit" ], @@ -62,8 +59,7 @@ "fcmp d16, d17", "mov w27, #0x0", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "vpmovmskb rax, xmm0": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json index 48efdd074..8e63fb90c 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map2.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json @@ -31,8 +31,8 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -55,8 +55,8 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -79,8 +79,8 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -103,8 +103,8 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -123,8 +123,8 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -143,8 +143,8 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "rmif x21, #63, #nzCv" ] }, @@ -351,7 +351,7 @@ ], "ExpectedArm64ASM": [ "bic w26, w5, w7", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -362,7 +362,7 @@ ], "ExpectedArm64ASM": [ "bic x26, x5, x7", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, @@ -377,8 +377,8 @@ "bic w20, w7, w20", "tst x5, #0xe0", "csel w4, w7, w20, ne", - "cset w20, ne", - "tst w4, w4", + "cset w20, eq", + "cmp w4, #0x0 (0)", "rmif x20, #63, #nzCv" ] }, @@ -393,8 +393,8 @@ "bic x20, x7, x20", "tst x5, #0xc0", "csel x4, x7, x20, ne", - "cset w20, ne", - "tst x4, x4", + "cset w20, eq", + "cmp x4, #0x0 (0)", "rmif x20, #63, #nzCv" ] }, @@ -459,7 +459,7 @@ "bic w22, w20, w22", "cmp w21, #0x1f (31)", "csel w4, w22, w20, ls", - "tst w4, w4" + "cmp w4, #0x0 (0)" ] }, "bextr rax, rbx, rcx": { @@ -479,7 +479,7 @@ "bic x22, x20, x22", "cmp x21, #0x3f (63)", "csel x4, x22, x20, ls", - "tst x4, x4" + "cmp x4, #0x0 (0)" ] } } diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json index a26c2bad3..a3509748b 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map_group.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json @@ -20,8 +20,8 @@ "sub w20, w7, #0x1 (1)", "and w4, w20, w7", "cmp x7, #0x0 (0)", - "cset x20, eq", - "tst w4, w4", + "cset x20, ne", + "cmp w4, #0x0 (0)", "rmif x20, #63, #nzCv" ] }, @@ -34,8 +34,8 @@ "sub x20, x7, #0x1 (1)", "and x4, x20, x7", "cmp x7, #0x0 (0)", - "cset x20, eq", - "tst x4, x4", + "cset x20, ne", + "cmp x4, #0x0 (0)", "rmif x20, #63, #nzCv" ] }, @@ -48,8 +48,8 @@ "sub w20, w7, #0x1 (1)", "eor w4, w20, w7", "cmp x7, #0x0 (0)", - "cset x20, eq", - "tst w4, w4", + "cset x20, ne", + "cmp w4, #0x0 (0)", "rmif x20, #63, #nzCv" ] }, @@ -62,8 +62,8 @@ "sub x20, x7, #0x1 (1)", "eor x4, x20, x7", "cmp x7, #0x0 (0)", - "cset x20, eq", - "tst x4, x4", + "cset x20, ne", + "cmp x4, #0x0 (0)", "rmif x20, #63, #nzCv" ] }, @@ -75,8 +75,8 @@ "ExpectedArm64ASM": [ "neg w20, w7", "and w4, w7, w20", - "tst w4, w4", - "cset w20, ne", + "cmp w4, #0x0 (0)", + "cset w20, eq", "rmif x20, #63, #nzCv" ] }, @@ -88,8 +88,8 @@ "ExpectedArm64ASM": [ "neg x20, x7", "and x4, x7, x20", - "tst x4, x4", - "cset w20, ne", + "cmp x4, #0x0 (0)", + "cset w20, eq", "rmif x20, #63, #nzCv" ] } diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index bb2f70b75..e7c46ecfa 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -13,7 +13,7 @@ }, "Instructions": { "Block1": { - "ExpectedInstructionCount": 1368, + "ExpectedInstructionCount": 1369, "x86Insts": [ "sub esp,0x2c", "mov ecx,dword [esp + 0x34]", @@ -1425,6 +1425,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -1458,7 +1459,7 @@ ] }, "Block2": { - "ExpectedInstructionCount": 551, + "ExpectedInstructionCount": 552, "x86Insts": [ "sub esp,0x1c", "mov edx,dword [esp + 0x20]", @@ -1601,11 +1602,11 @@ "ubfx x22, x22, #2, #1", "orr w23, w23, w22", "orr w22, w24, w22", + "eor x23, x23, #0x1", "rmif x23, #63, #nzCv", "rmif x22, #62, #nZcv", "mov w22, #0x1", - "csetm x23, hs", - "csel x23, x20, x23, eq", + "csetm x23, ls", "dup v4.2d, x23", "bit v2.16b, v3.16b, v4.16b", "ldr s3, [x6, #4]", @@ -1704,10 +1705,10 @@ "ubfx x23, x23, #2, #1", "orr w24, w24, w23", "orr w23, w25, w23", + "eor x24, x24, #0x1", "rmif x24, #63, #nzCv", "rmif x23, #62, #nZcv", - "csetm x23, hs", - "csel x23, x20, x23, eq", + "csetm x23, ls", "dup v5.2d, x23", "bit v3.16b, v4.16b, v5.16b", "mov w23, #0x8", @@ -1801,16 +1802,16 @@ "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64", "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", - "mov x21, x0", - "ubfx x24, x21, #1, #1", - "ubfx x25, x21, #0, #1", - "ubfx x21, x21, #2, #1", - "orr w24, w24, w21", - "orr w21, w25, w21", - "rmif x24, #63, #nzCv", - "rmif x21, #62, #nZcv", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "mov x20, x0", + "ubfx x21, x20, #1, #1", + "ubfx x24, x20, #0, #1", + "ubfx x20, x20, #2, #1", + "orr w21, w21, w20", + "orr w20, w24, w20", + "eor x21, x21, #0x1", + "rmif x21, #63, #nzCv", + "rmif x20, #62, #nZcv", + "csetm x20, ls", "dup v6.2d, x20", "bit v4.16b, v5.16b, v6.16b", "mrs x0, nzcv", @@ -2025,6 +2026,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w24, w24, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x24, #62, #nZcv", "eor w26, w20, #0x1", @@ -2899,7 +2901,7 @@ ] }, "Block4": { - "ExpectedInstructionCount": 206, + "ExpectedInstructionCount": 205, "x86Insts": [ "push ebp", "push edi", @@ -2962,7 +2964,6 @@ "str w10, [x8, #-4]!", "str w7, [x8, #-4]!", "subs w26, w8, #0x4c (76)", - "cfinv", "mov x27, x8", "mov x8, x26", "ldr w4, [x8, #104]", @@ -4158,12 +4159,12 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "mov w21, #0x1", "eor w26, w20, #0x1", - "cset x20, lo", - "csel x20, x20, xzr, ne", + "cset x20, hi", "strb w20, [x8, #48]", "ldrb w4, [x8, #48]", "add w20, w10, #0x4 (4)", @@ -4193,7 +4194,7 @@ ] }, "Block6": { - "ExpectedInstructionCount": 924, + "ExpectedInstructionCount": 925, "x86Insts": [ "push ebp", "push edi", @@ -5126,6 +5127,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -6756,7 +6758,7 @@ "ldr w4, [x20, #20]", "str w4, [x8, #156]", "mov w26, #0x0", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26", "mov w20, #0x869c", "movk w20, #0x5, lsl #16", diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 80af6ce0e..86c26c0b3 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -13,7 +13,7 @@ }, "Instructions": { "Block1": { - "ExpectedInstructionCount": 25782, + "ExpectedInstructionCount": 25781, "x86Insts": [ "sub esp,0x118", "fld dword [ecx + 0x1084]", @@ -26707,13 +26707,12 @@ "ldr w20, [x5, #4096]", "eor w27, w20, w5", "subs w26, w20, w5", - "cfinv", "add w4, w5, #0x800 (2048)", "strb wzr, [x28, #1298]" ] }, "Block2": { - "ExpectedInstructionCount": 16635, + "ExpectedInstructionCount": 16636, "x86Insts": [ "mov eax,dword [ebp + 0x8]", "fld dword [eax + 0x40]", @@ -43981,6 +43980,7 @@ "mov x8, x9", "ldr w9, [x8]", "add x8, x8, #0x4 (4)", + "cfinv", "strb wzr, [x28, #1298]" ] }, @@ -58298,7 +58298,7 @@ ] }, "Block5": { - "ExpectedInstructionCount": 284, + "ExpectedInstructionCount": 283, "x86Insts": [ "mov ebx,dword [eax + 0x68]", "fld dword [esi + 0x2c]", @@ -58675,7 +58675,6 @@ "ldr w4, [x9, #104]", "mvn w27, w8", "subs w26, w8, #0x14 (20)", - "cfinv", "mov x8, x26", "add w20, w8, #0x10 (16)", "str s2, [x20]", @@ -59337,7 +59336,7 @@ ] }, "Block7": { - "ExpectedInstructionCount": 7397, + "ExpectedInstructionCount": 7396, "x86Insts": [ "fld dword [ecx + 0xc]", "fld dword [ecx + 0x18]", @@ -64925,7 +64924,6 @@ "add w4, w4, #0x18 (24)", "add w5, w5, #0x4 (4)", "subs w26, w6, #0x1 (1)", - "cfinv", "mov x27, x6", "mov x6, x26", "add w12, w8, #0x44 (68)", @@ -66955,7 +66953,7 @@ ] }, "Block8": { - "ExpectedInstructionCount": 6590, + "ExpectedInstructionCount": 6589, "x86Insts": [ "movzx eax,word [esi + edx*0x8]", "fld dword [esi + edx*0x8 + 0x4]", @@ -71719,7 +71717,6 @@ "ldr w21, [x8, #28]", "eor w27, w6, w21", "subs w26, w6, w21", - "cfinv", "ldr s2, [x8, #196]", "mrs x0, nzcv", "str w0, [x28, #1000]", diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index 82feaa352..cdffbfd27 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -13,7 +13,7 @@ }, "Instructions": { "Block1": { - "ExpectedInstructionCount": 16357, + "ExpectedInstructionCount": 16358, "x86Insts": [ "sub esp,0x88", "fld dword [ecx + 0x4]", @@ -16891,13 +16891,14 @@ "fmov s2, s0", "str s2, [x20]", "adds w26, w8, #0x88 (136)", + "cfinv", "mov x27, x8", "mov x8, x26", "strb wzr, [x28, #1298]" ] }, "Block2": { - "ExpectedInstructionCount": 14021, + "ExpectedInstructionCount": 14022, "x86Insts": [ "sub esp,0x90", "fld dword [ecx + 0x4]", @@ -31347,6 +31348,7 @@ "str s2, [x20]", "mvn w27, w8", "adds w26, w8, #0x90 (144)", + "cfinv", "mov x8, x26", "ldrb w20, [x28, #1019]", "mov w21, #0x1", @@ -31359,7 +31361,7 @@ ] }, "Block3": { - "ExpectedInstructionCount": 118, + "ExpectedInstructionCount": 119, "x86Insts": [ "mov eax,dword [ebp + 0xffffff44]", "mov ecx,dword [eax + 0x4]", @@ -32179,6 +32181,7 @@ "movk w21, #0x819, lsl #16", "add w21, w20, w21", "str w20, [x8, #-4]!", + "cfinv", "ldr x0, [x28, #2272]", "and x3, x21, #0xfffff", "add x0, x0, x3, lsl #4", @@ -32186,7 +32189,7 @@ ] }, "Block4": { - "ExpectedInstructionCount": 12313, + "ExpectedInstructionCount": 12312, "x86Insts": [ "mov ebp,dword [esp + 0x64]", "fadd dword [ebp + 0x8]", @@ -43530,7 +43533,6 @@ "orr w21, w21, w23", "strb w21, [x28, #1298]", "subs w9, w9, #0x10 (16)", - "cfinv", "ldr s2, [x8, #24]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -44857,7 +44859,7 @@ ] }, "Block5": { - "ExpectedInstructionCount": 12248, + "ExpectedInstructionCount": 12247, "x86Insts": [ "mov ebp,dword [esp + 0x64]", "fadd dword [ebp + 0x8]", @@ -56331,7 +56333,6 @@ "orr w21, w21, w23", "strb w21, [x28, #1298]", "subs w7, w7, #0x10 (16)", - "cfinv", "cset w21, hs", "subs w26, w9, #0x1 (1)", "rmif x21, #63, #nzCv", @@ -65449,7 +65450,7 @@ ] }, "Block7": { - "ExpectedInstructionCount": 7583, + "ExpectedInstructionCount": 7582, "x86Insts": [ "push ebp", "mov ebp,esp", @@ -65875,7 +65876,6 @@ "mov x9, x8", "str w7, [x8, #-4]!", "subs w26, w8, #0x84 (132)", - "cfinv", "mov x27, x8", "mov x8, x26", "ldr w7, [x9, #8]", @@ -73457,7 +73457,7 @@ ] }, "Block8": { - "ExpectedInstructionCount": 8522, + "ExpectedInstructionCount": 8523, "x86Insts": [ "fadd dword [esp + 0x40]", "lea edx,[ecx + ecx*0x2]", @@ -82213,11 +82213,12 @@ "add x8, x8, #0x4 (4)", "mvn w27, w8", "adds w26, w8, #0x74 (116)", + "cfinv", "mov x8, x26" ] }, "Block9": { - "ExpectedInstructionCount": 8441, + "ExpectedInstructionCount": 8442, "x86Insts": [ "fadd dword [esp + 0x40]", "lea edx,[ecx + ecx*0x2]", @@ -90883,11 +90884,12 @@ "add x8, x8, #0x4 (4)", "mvn w27, w8", "adds w26, w8, #0x74 (116)", + "cfinv", "mov x8, x26" ] }, "Block10": { - "ExpectedInstructionCount": 6382, + "ExpectedInstructionCount": 6383, "x86Insts": [ "push ebp", "mov ebp,esp", @@ -97681,6 +97683,7 @@ "movk w21, #0x816, lsl #16", "add w21, w20, w21", "str w20, [x8, #-4]!", + "cfinv", "ldrb w20, [x28, #1019]", "add w20, w20, #0x5 (5)", "and w20, w20, #0x7", diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index c144e5ca3..7e0139577 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -5965,7 +5965,7 @@ "0xda 11b 0xc0 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -5983,7 +5983,7 @@ "0xda 11b 0xc1 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -6003,7 +6003,7 @@ "0xda 11b 0xc2 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -6023,7 +6023,7 @@ "0xda 11b 0xc3 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -6043,7 +6043,7 @@ "0xda 11b 0xc4 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -6063,7 +6063,7 @@ "0xda 11b 0xc5 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -6083,7 +6083,7 @@ "0xda 11b 0xc6 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -6103,7 +6103,7 @@ "0xda 11b 0xc7 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -6276,14 +6276,12 @@ ] }, "fcmovbe st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xd0 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -6296,14 +6294,12 @@ ] }, "fcmovbe st0, st1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd1 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -6318,14 +6314,12 @@ ] }, "fcmovbe st0, st2": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd2 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -6340,14 +6334,12 @@ ] }, "fcmovbe st0, st3": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd3 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -6362,14 +6354,12 @@ ] }, "fcmovbe st0, st4": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd4 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -6384,14 +6374,12 @@ ] }, "fcmovbe st0, st5": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd5 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -6406,14 +6394,12 @@ ] }, "fcmovbe st0, st6": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd6 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -6428,14 +6414,12 @@ ] }, "fcmovbe st0, st7": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd7 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -6943,7 +6927,7 @@ "0xdb 11b 0xc0 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -6961,7 +6945,7 @@ "0xdb 11b 0xc1 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -6981,7 +6965,7 @@ "0xdb 11b 0xc2 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -7001,7 +6985,7 @@ "0xdb 11b 0xc3 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -7021,7 +7005,7 @@ "0xdb 11b 0xc4 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -7041,7 +7025,7 @@ "0xdb 11b 0xc5 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -7061,7 +7045,7 @@ "0xdb 11b 0xc6 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -7081,7 +7065,7 @@ "0xdb 11b 0xc7 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -7254,13 +7238,12 @@ ] }, "fcmovnbe st0, st0": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xd0 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -7273,13 +7256,12 @@ ] }, "fcmovnbe st0, st1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd1 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -7294,13 +7276,12 @@ ] }, "fcmovnbe st0, st2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd2 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -7315,13 +7296,12 @@ ] }, "fcmovnbe st0, st3": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd3 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -7336,13 +7316,12 @@ ] }, "fcmovnbe st0, st4": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd4 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -7357,13 +7336,12 @@ ] }, "fcmovnbe st0, st5": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd5 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -7378,13 +7356,12 @@ ] }, "fcmovnbe st0, st6": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd6 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -7399,13 +7376,12 @@ ] }, "fcmovnbe st0, st7": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd7 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -7649,7 +7625,7 @@ ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 42, "Comment": [ "0xdb 11b 0xe8 /5" ], @@ -7692,13 +7668,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fucomi st0, st1": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xe9 /5" ], @@ -7743,13 +7720,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fucomi st0, st2": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xea /5" ], @@ -7794,13 +7772,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fucomi st0, st3": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xeb /5" ], @@ -7845,13 +7824,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fucomi st0, st4": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xec /5" ], @@ -7896,13 +7876,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fucomi st0, st5": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xed /5" ], @@ -7947,13 +7928,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fucomi st0, st6": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xee /5" ], @@ -7998,13 +7980,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fucomi st0, st7": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xef /5" ], @@ -8049,13 +8032,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 41, + "ExpectedInstructionCount": 42, "Comment": [ "0xdb 11b 0xf0 /6" ], @@ -8098,13 +8082,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fcomi st0, st1": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xf1 /6" ], @@ -8149,13 +8134,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fcomi st0, st2": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xf2 /6" ], @@ -8200,13 +8186,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fcomi st0, st3": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xf3 /6" ], @@ -8251,13 +8238,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fcomi st0, st4": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xf4 /6" ], @@ -8302,13 +8290,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fcomi st0, st5": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xf5 /6" ], @@ -8353,13 +8342,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fcomi st0, st6": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xf6 /6" ], @@ -8404,13 +8394,14 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" ] }, "fcomi st0, st7": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xf7 /6" ], @@ -8455,6 +8446,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "rmif x21, #63, #nzCv", "rmif x22, #62, #nZcv", "eor w26, w20, #0x1" @@ -16944,7 +16936,7 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 49, + "ExpectedInstructionCount": 50, "Comment": [ "0xdf 11b 0xe8 /5" ], @@ -16987,6 +16979,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17001,7 +16994,7 @@ ] }, "fucomip st1": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xe9 /5" ], @@ -17047,6 +17040,7 @@ "ubfx x22, x22, #2, #1", "orr w23, w23, w22", "orr w24, w24, w22", + "eor x23, x23, #0x1", "rmif x23, #63, #nzCv", "rmif x24, #62, #nZcv", "eor w26, w22, #0x1", @@ -17060,7 +17054,7 @@ ] }, "fucomip st2": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xea /5" ], @@ -17105,6 +17099,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17119,7 +17114,7 @@ ] }, "fucomip st3": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xeb /5" ], @@ -17164,6 +17159,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17178,7 +17174,7 @@ ] }, "fucomip st4": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xec /5" ], @@ -17223,6 +17219,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17237,7 +17234,7 @@ ] }, "fucomip st5": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xed /5" ], @@ -17282,6 +17279,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17296,7 +17294,7 @@ ] }, "fucomip st6": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xee /5" ], @@ -17341,6 +17339,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17355,7 +17354,7 @@ ] }, "fucomip st7": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xef /5" ], @@ -17400,6 +17399,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17414,7 +17414,7 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 49, + "ExpectedInstructionCount": 50, "Comment": [ "0xdf 11b 0xf0 /6" ], @@ -17457,6 +17457,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17471,7 +17472,7 @@ ] }, "fcomip st1": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xf1 /6" ], @@ -17517,6 +17518,7 @@ "ubfx x22, x22, #2, #1", "orr w23, w23, w22", "orr w24, w24, w22", + "eor x23, x23, #0x1", "rmif x23, #63, #nzCv", "rmif x24, #62, #nZcv", "eor w26, w22, #0x1", @@ -17530,7 +17532,7 @@ ] }, "fcomip st2": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xf2 /6" ], @@ -17575,6 +17577,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17589,7 +17592,7 @@ ] }, "fcomip st3": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xf3 /6" ], @@ -17634,6 +17637,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17648,7 +17652,7 @@ ] }, "fcomip st4": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xf4 /6" ], @@ -17693,6 +17697,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17707,7 +17712,7 @@ ] }, "fcomip st5": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xf5 /6" ], @@ -17752,6 +17757,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17766,7 +17772,7 @@ ] }, "fcomip st6": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xf6 /6" ], @@ -17811,6 +17817,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", @@ -17825,7 +17832,7 @@ ] }, "fcomip st7": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xf7 /6" ], @@ -17870,6 +17877,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "rmif x22, #63, #nzCv", "rmif x23, #62, #nZcv", "mov w22, #0x1", diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 7306151f3..2acf6b1ff 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -3316,7 +3316,7 @@ "0xda 11b 0xc0 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -3334,7 +3334,7 @@ "0xda 11b 0xc1 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -3354,7 +3354,7 @@ "0xda 11b 0xc2 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -3374,7 +3374,7 @@ "0xda 11b 0xc3 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -3394,7 +3394,7 @@ "0xda 11b 0xc4 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -3414,7 +3414,7 @@ "0xda 11b 0xc5 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -3434,7 +3434,7 @@ "0xda 11b 0xc6 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -3454,7 +3454,7 @@ "0xda 11b 0xc7 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -3627,14 +3627,12 @@ ] }, "fcmovbe st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xd0 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -3647,14 +3645,12 @@ ] }, "fcmovbe st0, st1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd1 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -3669,14 +3665,12 @@ ] }, "fcmovbe st0, st2": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd2 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -3691,14 +3685,12 @@ ] }, "fcmovbe st0, st3": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd3 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -3713,14 +3705,12 @@ ] }, "fcmovbe st0, st4": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd4 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -3735,14 +3725,12 @@ ] }, "fcmovbe st0, st5": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd5 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -3757,14 +3745,12 @@ ] }, "fcmovbe st0, st6": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd6 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -3779,14 +3765,12 @@ ] }, "fcmovbe st0, st7": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd7 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -4224,7 +4208,7 @@ "0xdb 11b 0xc0 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -4242,7 +4226,7 @@ "0xdb 11b 0xc1 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -4262,7 +4246,7 @@ "0xdb 11b 0xc2 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -4282,7 +4266,7 @@ "0xdb 11b 0xc3 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -4302,7 +4286,7 @@ "0xdb 11b 0xc4 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -4322,7 +4306,7 @@ "0xdb 11b 0xc5 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -4342,7 +4326,7 @@ "0xdb 11b 0xc6 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -4362,7 +4346,7 @@ "0xdb 11b 0xc7 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -4535,13 +4519,12 @@ ] }, "fcmovnbe st0, st0": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xd0 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -4554,13 +4537,12 @@ ] }, "fcmovnbe st0, st1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd1 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -4575,13 +4557,12 @@ ] }, "fcmovnbe st0, st2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd2 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -4596,13 +4577,12 @@ ] }, "fcmovnbe st0, st3": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd3 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -4617,13 +4597,12 @@ ] }, "fcmovnbe st0, st4": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd4 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -4638,13 +4617,12 @@ ] }, "fcmovnbe st0, st5": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd5 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -4659,13 +4637,12 @@ ] }, "fcmovnbe st0, st6": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd6 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -4680,13 +4657,12 @@ ] }, "fcmovnbe st0, st7": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd7 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -4938,7 +4914,7 @@ ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": [ "0xdb 11b 0xe8 /5" ], @@ -4950,12 +4926,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fucomi st0, st1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xe9 /5" ], @@ -4969,12 +4944,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fucomi st0, st2": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xea /5" ], @@ -4988,12 +4962,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fucomi st0, st3": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xeb /5" ], @@ -5007,12 +4980,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fucomi st0, st4": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xec /5" ], @@ -5026,12 +4998,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fucomi st0, st5": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xed /5" ], @@ -5045,12 +5016,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fucomi st0, st6": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xee /5" ], @@ -5064,12 +5034,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fucomi st0, st7": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xef /5" ], @@ -5083,12 +5052,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": [ "0xdb 11b 0xf0 /6" ], @@ -5100,12 +5068,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fcomi st0, st1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xf1 /6" ], @@ -5119,12 +5086,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fcomi st0, st2": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xf2 /6" ], @@ -5138,12 +5104,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fcomi st0, st3": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xf3 /6" ], @@ -5157,12 +5122,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fcomi st0, st4": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xf4 /6" ], @@ -5176,12 +5140,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fcomi st0, st5": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xf5 /6" ], @@ -5195,12 +5158,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fcomi st0, st6": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xf6 /6" ], @@ -5214,12 +5176,11 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fcomi st0, st7": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xf7 /6" ], @@ -5233,8 +5194,7 @@ "ldr d3, [x0, #1040]", "fcmp d3, d2", "cset w26, vc", - "axflag", - "cfinv" + "axflag" ] }, "fadd qword [rax]": { @@ -9710,7 +9670,7 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xdf 11b 0xe8 /5" ], @@ -9724,7 +9684,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -9735,7 +9694,7 @@ ] }, "fucomip st1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xe9 /5" ], @@ -9751,7 +9710,6 @@ "fcmp d3, d2", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -9762,7 +9720,7 @@ ] }, "fucomip st2": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xea /5" ], @@ -9778,7 +9736,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -9789,7 +9746,7 @@ ] }, "fucomip st3": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xeb /5" ], @@ -9805,7 +9762,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -9816,7 +9772,7 @@ ] }, "fucomip st4": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xec /5" ], @@ -9832,7 +9788,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -9843,7 +9798,7 @@ ] }, "fucomip st5": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xed /5" ], @@ -9859,7 +9814,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -9870,7 +9824,7 @@ ] }, "fucomip st6": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xee /5" ], @@ -9886,7 +9840,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -9897,7 +9850,7 @@ ] }, "fucomip st7": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xef /5" ], @@ -9913,7 +9866,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -9924,7 +9876,7 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 16, "Comment": [ "0xdf 11b 0xf0 /6" ], @@ -9938,7 +9890,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -9949,7 +9900,7 @@ ] }, "fcomip st1": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xf1 /6" ], @@ -9965,7 +9916,6 @@ "fcmp d3, d2", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -9976,7 +9926,7 @@ ] }, "fcomip st2": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xf2 /6" ], @@ -9992,7 +9942,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -10003,7 +9952,7 @@ ] }, "fcomip st3": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xf3 /6" ], @@ -10019,7 +9968,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -10030,7 +9978,7 @@ ] }, "fcomip st4": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xf4 /6" ], @@ -10046,7 +9994,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -10057,7 +10004,7 @@ ] }, "fcomip st5": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xf5 /6" ], @@ -10073,7 +10020,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -10084,7 +10030,7 @@ ] }, "fcomip st6": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xf6 /6" ], @@ -10100,7 +10046,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", @@ -10111,7 +10056,7 @@ ] }, "fcomip st7": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 18, "Comment": [ "0xdf 11b 0xf7 /6" ], @@ -10127,7 +10072,6 @@ "mov w21, #0x1", "cset w26, vc", "axflag", - "cfinv", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w22, w21", diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index 87bd690fa..64f115d76 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -404,10 +404,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -858,12 +858,12 @@ ] }, "adcx eax, ebx": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": [ "0x66 0x0f 0x38 0xf6" ], "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "mov w21, w7", "mov w22, w4", "add w23, w21, w20", @@ -875,17 +875,18 @@ "cset x21, ls", "cmp x20, #0x1 (1)", "csel x20, x21, x23, eq", + "eor x20, x20, #0x1", "bfi w22, w20, #29, #1", "msr nzcv, x22" ] }, "adcx rax, rbx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": [ "0x66 REX.W 0x0f 0x38 0xf6" ], "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "add x21, x7, x20", "add x4, x4, x21", "mrs x21, nzcv", @@ -895,6 +896,7 @@ "cset x23, ls", "cmp x20, #0x1 (1)", "csel x20, x23, x22, eq", + "eor x20, x20, #0x1", "bfi w21, w20, #29, #1", "msr nzcv, x21" ] diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 40c1824e4..074e0d343 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -12,47 +12,59 @@ }, "Instructions": { "add bl, cl": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "0x00", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #24", "cmn w0, w5, lsl #24", "add w26, w7, w5", - "bfxil x7, x26, #0, #8" + "bfxil x7, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "add bx, cx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": "0x01", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #16", "cmn w0, w5, lsl #16", "add w26, w7, w5", - "bfxil x7, x26, #0, #16" + "bfxil x7, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "add ebx, ecx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x01", "ExpectedArm64ASM": [ "eor w27, w7, w5", "adds w26, w7, w5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x7, x26" ] }, "add rbx, rcx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x01", "ExpectedArm64ASM": [ "eor w27, w7, w5", "adds x26, x7, x5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x7, x26" ] }, "db 0x02, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": [ "0x02", "add bl, cl but modrm.rm as source" @@ -62,11 +74,14 @@ "lsl w0, w5, #24", "cmn w0, w7, lsl #24", "add w26, w5, w7", - "bfxil x5, x26, #0, #8" + "bfxil x5, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "db 0x66, 0x03, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 8, "Comment": [ "0x03", "add bx, cx but modrm.rm as source" @@ -76,11 +91,14 @@ "lsl w0, w5, #16", "cmn w0, w7, lsl #16", "add w26, w5, w7", - "bfxil x5, x26, #0, #16" + "bfxil x5, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "db 0x03, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": [ "0x03", "add ebx, ecx but modrm.rm as source" @@ -88,11 +106,14 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "adds w26, w5, w7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x5, x26" ] }, "db 0x48, 0x03, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": [ "0x03", "add rbx, rcx but modrm.rm as source" @@ -100,11 +121,14 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "adds x26, x5, x7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x5, x26" ] }, "add al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 11, "Comment": "0x04", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -113,12 +137,15 @@ "add w26, w4, #0x1 (1)", "mov x20, x4", "bfxil x20, x26, #0, #8", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "mov x27, x4", "mov x4, x20" ] }, "add ax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 11, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -127,30 +154,39 @@ "add w26, w4, #0x1 (1)", "mov x20, x4", "bfxil x20, x26, #0, #16", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "mov x27, x4", "mov x4, x20" ] }, "add eax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "adds w26, w4, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "add rax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "adds x26, x4, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "add al, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 9, "Comment": "0x04", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -158,11 +194,14 @@ "lsl w0, w4, #24", "cmn w0, w20, lsl #24", "add w26, w4, #0xff (255)", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "add ax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 9, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -170,54 +209,72 @@ "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, w20", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "add eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "0x05", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", "adds w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "add rax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x05", "ExpectedArm64ASM": [ "mvn w27, w4", "subs x26, x4, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "or bl, bh": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "", "ExpectedArm64ASM": [ "lsr w20, w7, #8", "orr w26, w7, w20", "cmn wzr, w26, lsl #24", - "bfxil x7, x26, #0, #8" + "bfxil x7, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "or bl, cl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x08", "ExpectedArm64ASM": [ "orr w26, w7, w5", "cmn wzr, w26, lsl #24", - "bfxil x7, x26, #0, #8" + "bfxil x7, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "or bx, cx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x09", "ExpectedArm64ASM": [ "orr w26, w7, w5", "cmn wzr, w26, lsl #16", - "bfxil x7, x26, #0, #16" + "bfxil x7, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "or ebx, ecx": { @@ -225,7 +282,7 @@ "Comment": "0x09", "ExpectedArm64ASM": [ "orr w26, w7, w5", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x7, x26" ] }, @@ -234,12 +291,12 @@ "Comment": "0x09", "ExpectedArm64ASM": [ "orr x26, x7, x5", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x7, x26" ] }, "db 0x0A, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": [ "0x0A", "or bl, cl but modrm.rm as source" @@ -247,11 +304,14 @@ "ExpectedArm64ASM": [ "orr w26, w5, w7", "cmn wzr, w26, lsl #24", - "bfxil x5, x26, #0, #8" + "bfxil x5, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "db 0x66, 0x0B, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": [ "0x0B", "or bx, cx but modrm.rm as source" @@ -259,7 +319,10 @@ "ExpectedArm64ASM": [ "orr w26, w5, w7", "cmn wzr, w26, lsl #16", - "bfxil x5, x26, #0, #16" + "bfxil x5, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "db 0x0B, 0xcb": { @@ -270,7 +333,7 @@ ], "ExpectedArm64ASM": [ "orr w26, w5, w7", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x5, x26" ] }, @@ -282,26 +345,32 @@ ], "ExpectedArm64ASM": [ "orr x26, x5, x7", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x5, x26" ] }, "or al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x0C", "ExpectedArm64ASM": [ "orr w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "or ax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x0D", "ExpectedArm64ASM": [ "orr w26, w4, #0x1", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "or eax, 1": { @@ -309,7 +378,7 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "orr w26, w4, #0x1", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -318,26 +387,32 @@ "Comment": "0x0D", "ExpectedArm64ASM": [ "orr x26, x4, #0x1", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "or al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x0C", "ExpectedArm64ASM": [ "orr w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "or ax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x0D", "ExpectedArm64ASM": [ "orr w26, w4, #0xffff", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "or eax, -1": { @@ -346,7 +421,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "orr w26, w4, w20", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -356,7 +431,7 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "orr x26, x4, x20", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, @@ -366,11 +441,11 @@ "ExpectedArm64ASM": [ "eor w27, w7, w5", "uxtb w20, w5", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "add w22, w7, w21", "uxtb w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -389,11 +464,11 @@ "ExpectedArm64ASM": [ "eor w27, w7, w5", "uxth w20, w5", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "add w22, w7, w21", "uxth w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -407,20 +482,32 @@ ] }, "adc ebx, ecx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 9, "Comment": "0x11", "ExpectedArm64ASM": [ "eor w27, w7, w5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "adcs w26, w7, w5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x7, x26" ] }, "adc rbx, rcx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 9, "Comment": "0x11", "ExpectedArm64ASM": [ "eor w27, w7, w5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "adcs x26, x7, x5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x7, x26" ] }, @@ -433,11 +520,11 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "uxtb w20, w7", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "add w22, w5, w21", "uxtb w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -459,11 +546,11 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "uxth w20, w7", - "adc w21, wzr, w20", + "cinc w21, w20, lo", "add w22, w5, w21", "uxth w26, w22", "cmp w26, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -477,26 +564,38 @@ ] }, "db 0x13, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 9, "Comment": [ "0x13", "adc ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "adcs w26, w5, w7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x5, x26" ] }, "db 0x48, 0x13, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 9, "Comment": [ "0x13", "adc rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "adcs x26, x5, x7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x5, x26" ] }, @@ -505,11 +604,11 @@ "Comment": "0x14", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -530,11 +629,11 @@ "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxth w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -551,21 +650,33 @@ ] }, "adc eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "adc rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0x1", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] @@ -576,11 +687,11 @@ "ExpectedArm64ASM": [ "mvn w27, w4", "mov w20, #0xff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -599,11 +710,11 @@ "ExpectedArm64ASM": [ "mvn w27, w4", "mov w20, #0xffff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxth w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -617,22 +728,34 @@ ] }, "adc eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "0x15", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "adc rax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "0x15", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mvn w27, w4", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, @@ -643,11 +766,11 @@ "eor w27, w7, w5", "uxtb w20, w7", "uxtb w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxtb w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #24", "mrs x23, nzcv", "orr w22, w23, w22, lsl #29", @@ -667,11 +790,11 @@ "eor w27, w7, w5", "uxth w20, w7", "uxth w21, w5", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxth w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #16", "mrs x23, nzcv", "orr w22, w23, w22, lsl #29", @@ -685,32 +808,20 @@ ] }, "sbb ebx, ecx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 3, "Comment": "0x19", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sbcs w26, w7, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x7, x26" ] }, "sbb rbx, rcx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 3, "Comment": "0x19", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sbcs x26, x7, x5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x7, x26" ] }, @@ -724,11 +835,11 @@ "eor w27, w5, w7", "uxtb w20, w5", "uxtb w21, w7", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxtb w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #24", "mrs x23, nzcv", "orr w22, w23, w22, lsl #29", @@ -751,11 +862,11 @@ "eor w27, w5, w7", "uxth w20, w5", "uxth w21, w7", - "adc w22, wzr, w21", + "cinc w22, w21, lo", "sub w23, w20, w22", "uxth w26, w23", "cmp w20, w22", - "cset x22, lo", + "cset x22, hs", "cmn wzr, w26, lsl #16", "mrs x23, nzcv", "orr w22, w23, w22, lsl #29", @@ -769,38 +880,26 @@ ] }, "db 0x1B, 0xcb": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 3, "Comment": [ "0x1B", "sbb ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sbcs w26, w5, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x5, x26" ] }, "db 0x48, 0x1B, 0xcb": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 3, "Comment": [ "0x1B", "sbb rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sbcs x26, x5, x7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x5, x26" ] }, @@ -810,11 +909,11 @@ "ExpectedArm64ASM": [ "uxtb w20, w4", "mov w21, #0x1", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -836,11 +935,11 @@ "ExpectedArm64ASM": [ "uxth w20, w4", "mov w21, #0x1", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxth w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -857,33 +956,21 @@ ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs x26, x4, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] @@ -895,11 +982,11 @@ "mvn w27, w4", "uxtb w20, w4", "mov w21, #0xff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -919,11 +1006,11 @@ "mvn w27, w4", "uxth w20, w4", "mov w21, #0xffff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxth w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -937,73 +1024,73 @@ ] }, "sbb eax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x4, x26" ] }, "sbb rax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "0x1D", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mvn w27, w4", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs x26, x4, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x4, x26" ] }, "and bl, cl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x20", "ExpectedArm64ASM": [ "and w26, w7, w5", "cmn wzr, w26, lsl #24", - "bfxil x7, x26, #0, #8" + "bfxil x7, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "and bx, cx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x21", "ExpectedArm64ASM": [ "and w26, w7, w5", "cmn wzr, w26, lsl #16", - "bfxil x7, x26, #0, #16" + "bfxil x7, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "and ebx, ecx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0x21", "ExpectedArm64ASM": [ "ands w26, w7, w5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x7, x26" ] }, "and rbx, rcx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0x21", "ExpectedArm64ASM": [ "ands x26, x7, x5", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x7, x26" ] }, "db 0x22, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": [ "0x22", "and bl, cl but modrm.rm as source" @@ -1011,11 +1098,14 @@ "ExpectedArm64ASM": [ "and w26, w5, w7", "cmn wzr, w26, lsl #24", - "bfxil x5, x26, #0, #8" + "bfxil x5, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "db 0x66, 0x23, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": [ "0x23", "and bx, cx but modrm.rm as source" @@ -1023,155 +1113,176 @@ "ExpectedArm64ASM": [ "and w26, w5, w7", "cmn wzr, w26, lsl #16", - "bfxil x5, x26, #0, #16" + "bfxil x5, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "db 0x23, 0xcb": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": [ "0x23", "and ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ "ands w26, w5, w7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x5, x26" ] }, "db 0x48, 0x23, 0xcb": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": [ "0x23", "and rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ "ands x26, x5, x7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x5, x26" ] }, "and al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x24", "ExpectedArm64ASM": [ "and w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "and ax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x25", "ExpectedArm64ASM": [ "and w26, w4, #0x1", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "and eax, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0x25", "ExpectedArm64ASM": [ "ands w26, w4, #0x1", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "and rax, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0x25", "ExpectedArm64ASM": [ "ands x26, x4, #0x1", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "and al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x24", "ExpectedArm64ASM": [ "and w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "and ax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x25", "ExpectedArm64ASM": [ "and w26, w4, #0xffff", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "and eax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x25", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ands w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "and rax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x25", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "ands x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "sub bl, cl": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "0x28", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #24", "cmp w0, w5, lsl #24", "sub w26, w7, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "bfxil x7, x26, #0, #8", - "msr nzcv, x20" + "bfxil x7, x26, #0, #8" ] }, "sub bx, cx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "0x29", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #16", "cmp w0, w5, lsl #16", "sub w26, w7, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "bfxil x7, x26, #0, #16", - "msr nzcv, x20" + "bfxil x7, x26, #0, #16" ] }, "sub ebx, ecx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "0x29", "ExpectedArm64ASM": [ "eor w27, w7, w5", "subs w26, w7, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x7, x26" ] }, "sub rbx, rcx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "0x29", "ExpectedArm64ASM": [ "eor w27, w7, w5", "subs x26, x7, x5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x7, x26" ] }, "db 0x2A, 0xcb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": [ "0x2A", "sub bl, cl but modrm.rm as source" @@ -1181,14 +1292,11 @@ "lsl w0, w5, #24", "cmp w0, w7, lsl #24", "sub w26, w5, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "bfxil x5, x26, #0, #8", - "msr nzcv, x20" + "bfxil x5, x26, #0, #8" ] }, "db 0x66, 0x2B, 0xcb": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": [ "0x2B", "sub bx, cx but modrm.rm as source" @@ -1198,14 +1306,11 @@ "lsl w0, w5, #16", "cmp w0, w7, lsl #16", "sub w26, w5, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "bfxil x5, x26, #0, #16", - "msr nzcv, x20" + "bfxil x5, x26, #0, #16" ] }, "db 0x2B, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": [ "0x2B", "sub ebx, ecx but modrm.rm as source" @@ -1213,14 +1318,11 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "subs w26, w5, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x5, x26" ] }, "db 0x48, 0x2B, 0xcb": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": [ "0x2B", "sub rbx, rcx but modrm.rm as source" @@ -1228,72 +1330,57 @@ "ExpectedArm64ASM": [ "eor w27, w5, w7", "subs x26, x5, x7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x5, x26" ] }, "sub al, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 8, "Comment": "0x2C", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "mov x21, x4", - "bfxil x21, x26, #0, #8", - "msr nzcv, x20", + "mov x20, x4", + "bfxil x20, x26, #0, #8", "mov x27, x4", - "mov x4, x21" + "mov x4, x20" ] }, "sub ax, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 8, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "mov x21, x4", - "bfxil x21, x26, #0, #16", - "msr nzcv, x20", + "mov x20, x4", + "bfxil x20, x26, #0, #16", "mov x27, x4", - "mov x4, x21" + "mov x4, x20" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "0x2D", "ExpectedArm64ASM": [ "subs w26, w4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "0x2D", "ExpectedArm64ASM": [ "subs x26, x4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sub al, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "0x2C", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -1301,14 +1388,11 @@ "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0xff (255)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "bfxil x4, x26, #0, #8" ] }, "sub ax, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -1316,53 +1400,50 @@ "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "bfxil x4, x26, #0, #16", - "msr nzcv, x20" + "bfxil x4, x26, #0, #16" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "0x2D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x4, x26" ] }, "sub rax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "0x2D", "ExpectedArm64ASM": [ "mvn w27, w4", "adds x26, x4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x4, x26" ] }, "xor bl, cl": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x30", "ExpectedArm64ASM": [ "eor w26, w7, w5", "cmn wzr, w26, lsl #24", - "bfxil x7, x26, #0, #8" + "bfxil x7, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xor bx, cx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x31", "ExpectedArm64ASM": [ "eor w26, w7, w5", "cmn wzr, w26, lsl #16", - "bfxil x7, x26, #0, #16" + "bfxil x7, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xor ebx, ecx": { @@ -1370,7 +1451,7 @@ "Comment": "0x31", "ExpectedArm64ASM": [ "eor w26, w7, w5", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x7, x26" ] }, @@ -1379,12 +1460,12 @@ "Comment": "0x31", "ExpectedArm64ASM": [ "eor x26, x7, x5", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x7, x26" ] }, "db 0x32, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": [ "0x32", "xor bl, cl but modrm.rm as source" @@ -1392,11 +1473,14 @@ "ExpectedArm64ASM": [ "eor w26, w5, w7", "cmn wzr, w26, lsl #24", - "bfxil x5, x26, #0, #8" + "bfxil x5, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "db 0x66, 0x33, 0xcb": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": [ "0x33", "xor bx, cx but modrm.rm as source" @@ -1404,7 +1488,10 @@ "ExpectedArm64ASM": [ "eor w26, w5, w7", "cmn wzr, w26, lsl #16", - "bfxil x5, x26, #0, #16" + "bfxil x5, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "db 0x33, 0xcb": { @@ -1415,7 +1502,7 @@ ], "ExpectedArm64ASM": [ "eor w26, w5, w7", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x5, x26" ] }, @@ -1427,26 +1514,32 @@ ], "ExpectedArm64ASM": [ "eor x26, x5, x7", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x5, x26" ] }, "xor al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x34", "ExpectedArm64ASM": [ "eor w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xor ax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x35", "ExpectedArm64ASM": [ "eor w26, w4, #0x1", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xor eax, 1": { @@ -1454,7 +1547,7 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "eor w26, w4, #0x1", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -1463,39 +1556,42 @@ "Comment": "0x35", "ExpectedArm64ASM": [ "eor x26, x4, #0x1", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp bl, cl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "0x38", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #24", "cmp w0, w5, lsl #24", - "sub w26, w7, w5", + "sub w26, w7, w5" + ] + }, + "xor al, -1": { + "ExpectedInstructionCount": 6, + "Comment": "0x34", + "ExpectedArm64ASM": [ + "eor w26, w4, #0xff", + "cmn wzr, w26, lsl #24", + "bfxil x4, x26, #0, #8", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, - "xor al, -1": { - "ExpectedInstructionCount": 3, - "Comment": "0x34", - "ExpectedArm64ASM": [ - "eor w26, w4, #0xff", - "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" - ] - }, "xor ax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "0x35", "ExpectedArm64ASM": [ "eor w26, w4, #0xffff", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xor eax, -1": { @@ -1504,7 +1600,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "eor w26, w4, w20", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -1514,47 +1610,38 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "eor x26, x4, x20", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp bx, cx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "0x39", "ExpectedArm64ASM": [ "eor w27, w7, w5", "lsl w0, w7, #16", "cmp w0, w5, lsl #16", - "sub w26, w7, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w7, w5" ] }, "cmp ebx, ecx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "0x39", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "subs w26, w7, w5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs w26, w7, w5" ] }, "cmp rbx, rcx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "0x39", "ExpectedArm64ASM": [ "eor w27, w7, w5", - "subs x26, x7, x5", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs x26, x7, x5" ] }, "db 0x3A, 0xcb": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": [ "0x3A", "cmp bl, cl but modrm.rm as source" @@ -1563,14 +1650,11 @@ "eor w27, w5, w7", "lsl w0, w5, #24", "cmp w0, w7, lsl #24", - "sub w26, w5, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w5, w7" ] }, "db 0x66, 0x3B, 0xcb": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": [ "0x3B", "cmp bx, cx but modrm.rm as source" @@ -1579,139 +1663,106 @@ "eor w27, w5, w7", "lsl w0, w5, #16", "cmp w0, w7, lsl #16", - "sub w26, w5, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w5, w7" ] }, "db 0x3B, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": [ "0x3B", "cmp ebx, ecx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "subs w26, w5, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs w26, w5, w7" ] }, "db 0x48, 0x3B, 0xcb": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": [ "0x3B", "cmp rbx, rcx but modrm.rm as source" ], "ExpectedArm64ASM": [ "eor w27, w5, w7", - "subs x26, x5, x7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs x26, x5, x7" ] }, "cmp al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "0x3C", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "cmp ax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "0x3D", "ExpectedArm64ASM": [ "subs w26, w4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "0x3D", "ExpectedArm64ASM": [ "subs x26, x4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "cmp al, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "0x3C", "ExpectedArm64ASM": [ "mov w20, #0xff", "mvn w27, w4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w4, #0xff (255)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w4, #0xff (255)" ] }, "cmp ax, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffff", "mvn w27, w4", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", - "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w4, w20" ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "0x3D", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", - "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs w26, w4, w20" ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "0x3D", "ExpectedArm64ASM": [ "mvn w27, w4", - "adds x26, x4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "adds x26, x4, #0x1 (1)" ] }, "push ax": { @@ -1779,7 +1830,7 @@ "bfxil x4, x20, #0, #16", "sbfx x20, x20, #15, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul eax, ebx, 257": { @@ -1792,7 +1843,7 @@ "mul w4, w7, w20", "sbfx x20, x4, #31, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul rax, rbx, 257": { @@ -1804,7 +1855,7 @@ "mul x4, x7, x20", "asr x20, x4, #63", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "push word -1": { @@ -1842,7 +1893,7 @@ "bfxil x4, x20, #0, #16", "sbfx x20, x20, #15, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul eax, ebx, 3": { @@ -1855,7 +1906,7 @@ "mul w4, w7, w20", "sbfx x20, x4, #31, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul rax, rbx, 3": { @@ -1867,67 +1918,91 @@ "mul x4, x7, x20", "asr x20, x4, #63", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "test al, bl": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0x84", "ExpectedArm64ASM": [ "and w26, w4, w7", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test ax, bx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0x84", "ExpectedArm64ASM": [ "and w26, w4, w7", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test eax, ebx": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "0x84", "ExpectedArm64ASM": [ - "ands w26, w4, w7" + "ands w26, w4, w7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test rax, rbx": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "0x84", "ExpectedArm64ASM": [ - "ands x26, x4, x7" + "ands x26, x4, x7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test al, al": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0x84", "ExpectedArm64ASM": [ "mov x26, x4", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test ax, ax": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0x84", "ExpectedArm64ASM": [ "mov x26, x4", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test eax, eax": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "0x84", "ExpectedArm64ASM": [ - "ands w26, w4, w4" + "ands w26, w4, w4", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test rax, rax": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "0x84", "ExpectedArm64ASM": [ - "ands x26, x4, x4" + "ands x26, x4, x4", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xchg bl, cl": { @@ -2539,7 +2614,7 @@ "ExpectedInstructionCount": 39, "Comment": "0x9c", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -2584,7 +2659,7 @@ "ExpectedInstructionCount": 39, "Comment": "0x9c", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -2633,13 +2708,12 @@ "add x8, x8, #0x8 (8)", "mov w21, #0x202", "orr x27, x20, x21", - "ubfx x20, x27, #0, #1", - "lsl x20, x20, #29", - "ubfx w21, w27, #2, #1", - "mov w22, #0x1", - "eor w26, w21, #0x1", - "ubfx x21, x27, #6, #1", - "orr w20, w20, w21, lsl #30", + "mvn w20, w27", + "ubfx x21, x20, #0, #1", + "lsl x21, x21, #29", + "ubfx w26, w20, #2, #1", + "ubfx x20, x27, #6, #1", + "orr w20, w21, w20, lsl #30", "ubfx x21, x27, #7, #1", "orr w20, w20, w21, lsl #31", "ubfx w21, w27, #8, #1", @@ -2647,6 +2721,7 @@ "ubfx w21, w27, #9, #1", "strb w21, [x28, #985]", "ubfx w21, w27, #10, #1", + "mov w22, #0x1", "sub x21, x22, x21, lsl #1", "ubfx x22, x27, #11, #1", "orr w20, w20, w22, lsl #28", @@ -2678,23 +2753,23 @@ "mov w21, #0x28", "bic x20, x20, x21", "orr x27, x20, #0x2", - "ubfx x20, x27, #0, #1", - "mrs x21, nzcv", - "bfi w21, w20, #29, #1", - "ubfx w20, w27, #2, #1", - "eor w26, w20, #0x1", + "mvn w20, w27", + "ubfx x21, x20, #0, #1", + "mrs x22, nzcv", + "bfi w22, w21, #29, #1", + "ubfx w26, w20, #2, #1", "ubfx x20, x27, #6, #1", - "bfi w21, w20, #30, #1", + "bfi w22, w20, #30, #1", "ubfx x20, x27, #7, #1", - "bfi w21, w20, #31, #1", - "msr nzcv, x21" + "bfi w22, w20, #31, #1", + "msr nzcv, x22" ] }, "lahf": { "ExpectedInstructionCount": 14, "Comment": "0x9f", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -3175,7 +3250,7 @@ ] }, "cmpsb": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 9, "Comment": [ "0xa6" ], @@ -3186,16 +3261,13 @@ "lsl w0, w21, #24", "cmp w0, w20, lsl #24", "sub w26, w21, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "ldrsb x21, [x28, #986]", - "add x11, x11, x21", - "add x10, x10, x21", - "msr nzcv, x20" + "ldrsb x20, [x28, #986]", + "add x11, x11, x20", + "add x10, x10, x20" ] }, "cmpsw": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 10, "Comment": [ "0xa7" ], @@ -3206,17 +3278,14 @@ "lsl w0, w21, #16", "cmp w0, w20, lsl #16", "sub w26, w21, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "ldrsb x21, [x28, #986]", - "lsl x21, x21, #1", - "add x11, x11, x21", - "add x10, x10, x21", - "msr nzcv, x20" + "ldrsb x20, [x28, #986]", + "lsl x20, x20, #1", + "add x11, x11, x20", + "add x10, x10, x20" ] }, "cmpsd": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 8, "Comment": [ "0xa7" ], @@ -3225,17 +3294,14 @@ "ldr w21, [x10]", "eor w27, w21, w20", "subs w26, w21, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "ldrsb x21, [x28, #986]", - "lsl x21, x21, #2", - "add x11, x11, x21", - "add x10, x10, x21", - "msr nzcv, x20" + "ldrsb x20, [x28, #986]", + "lsl x20, x20, #2", + "add x11, x11, x20", + "add x10, x10, x20" ] }, "cmpsq": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 8, "Comment": [ "0xa7" ], @@ -3244,20 +3310,17 @@ "ldr x21, [x10]", "eor w27, w21, w20", "subs x26, x21, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "ldrsb x21, [x28, #986]", - "lsl x21, x21, #3", - "add x11, x11, x21", - "add x10, x10, x21", - "msr nzcv, x20" + "ldrsb x20, [x28, #986]", + "lsl x20, x20, #3", + "add x11, x11, x20", + "add x10, x10, x20" ] }, "repz cmpsb": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 25, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x70", + "cbz x5, #+0x64", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3281,17 +3344,14 @@ "lsl w0, w27, #24", "cmp w0, w26, lsl #24", "sub w26, w27, w26", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "mov x27, x20" ] }, "repz cmpsw": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 25, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x70", + "cbz x5, #+0x64", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3315,17 +3375,14 @@ "lsl w0, w27, #16", "cmp w0, w26, lsl #16", "sub w26, w27, w26", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "mov x27, x20" ] }, "repz cmpsd": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 23, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x5c", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3347,17 +3404,14 @@ "b.eq #-0x18", "eor w20, w27, w26", "subs w26, w27, w26", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "mov x27, x20" ] }, "repz cmpsq": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 23, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x5c", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3379,17 +3433,14 @@ "b.eq #-0x18", "eor w20, w27, w26", "subs x26, x27, x26", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "mov x27, x20" ] }, "repnz cmpsb": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 25, "Comment": "0xa6", "ExpectedArm64ASM": [ - "cbz x5, #+0x70", + "cbz x5, #+0x64", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3413,17 +3464,14 @@ "lsl w0, w27, #24", "cmp w0, w26, lsl #24", "sub w26, w27, w26", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "mov x27, x20" ] }, "repnz cmpsw": { - "ExpectedInstructionCount": 28, + "ExpectedInstructionCount": 25, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x70", + "cbz x5, #+0x64", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3447,17 +3495,14 @@ "lsl w0, w27, #16", "cmp w0, w26, lsl #16", "sub w26, w27, w26", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "mov x27, x20" ] }, "repnz cmpsd": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 23, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x5c", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3479,17 +3524,14 @@ "b.ne #-0x18", "eor w20, w27, w26", "subs w26, w27, w26", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "mov x27, x20" ] }, "repnz cmpsq": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 23, "Comment": "0xa7", "ExpectedArm64ASM": [ - "cbz x5, #+0x68", + "cbz x5, #+0x5c", "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", @@ -3511,70 +3553,91 @@ "b.ne #-0x18", "eor w20, w27, w26", "subs x26, x27, x26", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "mov x27, x20" ] }, "test al, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0xa8", "ExpectedArm64ASM": [ "and w26, w4, #0x1", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test ax, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0xa9", "ExpectedArm64ASM": [ "and w26, w4, #0x1", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test eax, 1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "0xa9", "ExpectedArm64ASM": [ - "ands w26, w4, #0x1" + "ands w26, w4, #0x1", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test rax, 1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "0xa9", "ExpectedArm64ASM": [ - "ands x26, x4, #0x1" + "ands x26, x4, #0x1", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test al, -1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0xa8", "ExpectedArm64ASM": [ "mov x26, x4", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test ax, -1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "0xa9", "ExpectedArm64ASM": [ "mov x26, x4", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test eax, -1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "0xa9", "ExpectedArm64ASM": [ - "ands w26, w4, w4" + "ands w26, w4, w4", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test rax, -1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "0xa9", "ExpectedArm64ASM": [ - "ands x26, x4, x4" + "ands x26, x4, x4", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "stosb": { @@ -3987,7 +4050,7 @@ ] }, "scasb": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 7, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrb w20, [x11]", @@ -3995,15 +4058,12 @@ "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "ldrsb x21, [x28, #986]", - "add x11, x11, x21", - "msr nzcv, x20" + "ldrsb x20, [x28, #986]", + "add x11, x11, x20" ] }, "scasw": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 7, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrh w20, [x11]", @@ -4011,303 +4071,246 @@ "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "ldrsb x21, [x28, #986]", - "add x11, x11, x21, lsl #1", - "msr nzcv, x20" + "ldrsb x20, [x28, #986]", + "add x11, x11, x20, lsl #1" ] }, "scasd": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldr w20, [x11]", "eor w27, w4, w20", "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "ldrsb x21, [x28, #986]", - "add x11, x11, x21, lsl #2", - "msr nzcv, x20" + "ldrsb x20, [x28, #986]", + "add x11, x11, x20, lsl #2" ] }, "scasq": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldr x20, [x11]", "eor w27, w4, w20", "subs x26, x4, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "ldrsb x21, [x28, #986]", - "add x11, x11, x21, lsl #3", - "msr nzcv, x20" + "ldrsb x20, [x28, #986]", + "add x11, x11, x20, lsl #3" ] }, "repz scasb": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 23, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x38", - "cbz x5, #+0x30", + "b #+0x2c", + "cbz x5, #+0x24", "ldrb w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x1 (1)", - "b.eq #-0x2c", - "b #+0x34", - "cbz x5, #+0x30", + "b.eq #-0x20", + "b #+0x28", + "cbz x5, #+0x24", "ldrb w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x1 (1)", - "b.eq #-0x2c" + "b.eq #-0x20" ] }, "repz scasw": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 23, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x38", - "cbz x5, #+0x30", + "b #+0x2c", + "cbz x5, #+0x24", "ldrh w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x2 (2)", - "b.eq #-0x2c", - "b #+0x34", - "cbz x5, #+0x30", + "b.eq #-0x20", + "b #+0x28", + "cbz x5, #+0x24", "ldrh w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x2 (2)", - "b.eq #-0x2c" + "b.eq #-0x20" ] }, "repz scasd": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 19, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x30", - "cbz x5, #+0x28", + "b #+0x24", + "cbz x5, #+0x1c", "ldr w20, [x11]", "eor w27, w4, w20", "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x4 (4)", - "b.eq #-0x24", - "b #+0x2c", - "cbz x5, #+0x28", + "b.eq #-0x18", + "b #+0x20", + "cbz x5, #+0x1c", "ldr w20, [x11]", "eor w27, w4, w20", "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x4 (4)", - "b.eq #-0x24" + "b.eq #-0x18" ] }, "repz scasq": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 19, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x30", - "cbz x5, #+0x28", + "b #+0x24", + "cbz x5, #+0x1c", "ldr x20, [x11]", "eor w27, w4, w20", "subs x26, x4, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x8 (8)", - "b.eq #-0x24", - "b #+0x2c", - "cbz x5, #+0x28", + "b.eq #-0x18", + "b #+0x20", + "cbz x5, #+0x1c", "ldr x20, [x11]", "eor w27, w4, w20", "subs x26, x4, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x8 (8)", - "b.eq #-0x24" + "b.eq #-0x18" ] }, "repnz scasb": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 23, "Comment": "0xae", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x38", - "cbz x5, #+0x30", + "b #+0x2c", + "cbz x5, #+0x24", "ldrb w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x1 (1)", - "b.ne #-0x2c", - "b #+0x34", - "cbz x5, #+0x30", + "b.ne #-0x20", + "b #+0x28", + "cbz x5, #+0x24", "ldrb w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x1 (1)", - "b.ne #-0x2c" + "b.ne #-0x20" ] }, "repnz scasw": { - "ExpectedInstructionCount": 29, + "ExpectedInstructionCount": 23, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x38", - "cbz x5, #+0x30", + "b #+0x2c", + "cbz x5, #+0x24", "ldrh w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x2 (2)", - "b.ne #-0x2c", - "b #+0x34", - "cbz x5, #+0x30", + "b.ne #-0x20", + "b #+0x28", + "cbz x5, #+0x24", "ldrh w20, [x11]", "eor w27, w4, w20", "lsl w0, w4, #16", "cmp w0, w20, lsl #16", "sub w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x2 (2)", - "b.ne #-0x2c" + "b.ne #-0x20" ] }, "repnz scasd": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 19, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x30", - "cbz x5, #+0x28", + "b #+0x24", + "cbz x5, #+0x1c", "ldr w20, [x11]", "eor w27, w4, w20", "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x4 (4)", - "b.ne #-0x24", - "b #+0x2c", - "cbz x5, #+0x28", + "b.ne #-0x18", + "b #+0x20", + "cbz x5, #+0x1c", "ldr w20, [x11]", "eor w27, w4, w20", "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x4 (4)", - "b.ne #-0x24" + "b.ne #-0x18" ] }, "repnz scasq": { - "ExpectedInstructionCount": 25, + "ExpectedInstructionCount": 19, "Comment": "0xaf", "ExpectedArm64ASM": [ "ldrsb x20, [x28, #986]", "lsr x20, x20, #63", "cbz x20, #+0x8", - "b #+0x30", - "cbz x5, #+0x28", + "b #+0x24", + "cbz x5, #+0x1c", "ldr x20, [x11]", "eor w27, w4, w20", "subs x26, x4, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "add x11, x11, #0x8 (8)", - "b.ne #-0x24", - "b #+0x2c", - "cbz x5, #+0x28", + "b.ne #-0x18", + "b #+0x20", + "cbz x5, #+0x1c", "ldr x20, [x11]", "eor w27, w4, w20", "subs x26, x4, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "sub x5, x5, #0x1 (1)", "sub x11, x11, #0x8 (8)", - "b.ne #-0x24" + "b.ne #-0x18" ] }, "mov al, 0xff": { @@ -4398,7 +4401,7 @@ "Comment": "0xf8", "ExpectedArm64ASM": [ "mrs x20, nzcv", - "and w20, w20, #0xdfffffff", + "orr w20, w20, #0x20000000", "msr nzcv, x20" ] }, @@ -4407,7 +4410,7 @@ "Comment": "0xf9", "ExpectedArm64ASM": [ "mrs x20, nzcv", - "orr w20, w20, #0x20000000", + "and w20, w20, #0xdfffffff", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index adc7dea31..18c81dd5e 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -16,7 +16,7 @@ ], "Instructions": { "add al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -25,17 +25,23 @@ "add w26, w4, #0x1 (1)", "mov x20, x4", "bfxil x20, x26, #0, #8", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "mov x27, x4", "mov x4, x20" ] }, "or al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "orr w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "adc al, 1": { @@ -43,11 +49,11 @@ "Comment": "GROUP1 0x80 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -69,11 +75,11 @@ "ExpectedArm64ASM": [ "uxtb w20, w4", "mov w21, #0x1", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -90,56 +96,56 @@ ] }, "and al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "and w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "sub al, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 8, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "mov x21, x4", - "bfxil x21, x26, #0, #8", - "msr nzcv, x20", + "mov x20, x4", + "bfxil x20, x26, #0, #8", "mov x27, x4", - "mov x4, x21" + "mov x4, x20" ] }, "xor al, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "eor w26, w4, #0x1", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "cmp al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "mov w20, #0x1", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "add al, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x80 /0", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -147,16 +153,22 @@ "lsl w0, w4, #24", "cmn w0, w20, lsl #24", "add w26, w4, #0xff (255)", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "or al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /1", "ExpectedArm64ASM": [ "orr w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "adc al, -1": { @@ -165,11 +177,11 @@ "ExpectedArm64ASM": [ "mvn w27, w4", "mov w20, #0xff", - "adc w20, wzr, w20", + "cinc w20, w20, lo", "add w21, w4, w20", "uxtb w26, w21", "cmp w26, w20", - "cset x20, lo", + "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -189,11 +201,11 @@ "mvn w27, w4", "uxtb w20, w4", "mov w21, #0xff", - "adc w21, wzr, w21", + "cinc w21, w21, lo", "sub w22, w20, w21", "uxtb w26, w22", "cmp w20, w21", - "cset x21, lo", + "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", @@ -207,16 +219,19 @@ ] }, "and al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /4", "ExpectedArm64ASM": [ "and w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "sub al, -1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /5", "ExpectedArm64ASM": [ "mov w20, #0xff", @@ -224,37 +239,34 @@ "lsl w0, w4, #24", "cmp w0, w20, lsl #24", "sub w26, w4, #0xff (255)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "bfxil x4, x26, #0, #8" ] }, "xor al, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x80 /6", "ExpectedArm64ASM": [ "eor w26, w4, #0xff", "cmn wzr, w26, lsl #24", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "cmp al, -1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x80 /7", "ExpectedArm64ASM": [ "mov w20, #0xff", "mvn w27, w4", "lsl w0, w4, #24", "cmp w0, w20, lsl #24", - "sub w26, w4, #0xff (255)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "sub w26, w4, #0xff (255)" ] }, "add ax, 256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0x100", @@ -263,24 +275,33 @@ "add w26, w4, #0x100 (256)", "mov x20, x4", "bfxil x20, x26, #0, #16", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "mov x27, x4", "mov x4, x20" ] }, "add eax, 256": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "adds w26, w4, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "add rax, 256": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "adds x26, x4, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] @@ -290,7 +311,7 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr w26, w4, #0x100", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -299,98 +320,98 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr x26, x4, #0x100", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "adc eax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "adc rax, 256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0x100", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sbb eax, 256": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sbb rax, 256": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0x100", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs x26, x4, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "and eax, 256": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "ands w26, w4, #0x100", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "and rax, 256": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "ands x26, x4, #0x100", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "sub eax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "subs w26, w4, #0x100 (256)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sub rax, 256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "subs x26, x4, #0x100 (256)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] @@ -400,7 +421,7 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor w26, w4, #0x100", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -409,34 +430,28 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor x26, x4, #0x100", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp eax, 256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "subs w26, w4, #0x100 (256)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "cmp rax, 256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "subs x26, x4, #0x100 (256)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "add ax, -256": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xff00", @@ -445,25 +460,34 @@ "add w26, w4, w20", "mov x20, x4", "bfxil x20, x26, #0, #16", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "mov x27, x4", "mov x4, x20" ] }, "add eax, -256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "adds w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "add rax, -256": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x81 /0", "ExpectedArm64ASM": [ "subs x26, x4, #0x100 (256)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] @@ -473,7 +497,7 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr w26, w4, #0xffffff00", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -482,99 +506,99 @@ "Comment": "GROUP1 0x81 /1", "ExpectedArm64ASM": [ "orr x26, x4, #0xffffffffffffff00", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "adc eax, -256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "adc rax, -256": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x81 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sbb eax, -256": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sbb rax, -256": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffff00", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs x26, x4, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "and eax, -256": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "ands w26, w4, #0xffffff00", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "and rax, -256": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x81 /4", "ExpectedArm64ASM": [ "ands x26, x4, #0xffffffffffffff00", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "sub eax, -256": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sub rax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /5", "ExpectedArm64ASM": [ "adds x26, x4, #0x100 (256)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] @@ -584,7 +608,7 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor w26, w4, #0xffffff00", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -593,35 +617,29 @@ "Comment": "GROUP1 0x81 /6", "ExpectedArm64ASM": [ "eor x26, x4, #0xffffffffffffff00", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp eax, -256": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffff00", "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "cmp rax, -256": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x81 /7", "ExpectedArm64ASM": [ "adds x26, x4, #0x100 (256)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "add ax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 11, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -630,24 +648,33 @@ "add w26, w4, #0x1 (1)", "mov x20, x4", "bfxil x20, x26, #0, #16", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "mov x27, x4", "mov x4, x20" ] }, "add eax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "adds w26, w4, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "add rax, 1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "adds x26, x4, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] @@ -657,7 +684,7 @@ "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "orr w26, w4, #0x1", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -666,98 +693,98 @@ "Comment": "GROUP1 0x83 /1", "ExpectedArm64ASM": [ "orr x26, x4, #0x1", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "adc eax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "adc rax, 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0x1", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sbb eax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sbb rax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0x1", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs x26, x4, x20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "and eax, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "ands w26, w4, #0x1", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "and rax, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "ands x26, x4, #0x1", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "sub eax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "subs w26, w4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] }, "sub rax, 1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "subs x26, x4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4", "mov x4, x26" ] @@ -767,7 +794,7 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "eor w26, w4, #0x1", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -776,34 +803,28 @@ "Comment": "GROUP1 0x83 /6", "ExpectedArm64ASM": [ "eor x26, x4, #0x1", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp eax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "subs w26, w4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "cmp rax, 1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "subs x26, x4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x4" ] }, "add ax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 9, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffff", @@ -811,25 +832,34 @@ "lsl w0, w4, #16", "cmn w0, w20, lsl #16", "add w26, w4, w20", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "add eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", "adds w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "add rax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /0", "ExpectedArm64ASM": [ "mvn w27, w4", "subs x26, x4, #0x1 (1)", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, @@ -839,7 +869,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "orr w26, w4, w20", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -849,102 +879,102 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "orr x26, x4, x20", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "adc eax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs w26, w4, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "adc rax, -1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 10, "Comment": "GROUP1 0x83 /2", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mvn w27, w4", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "adcs x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "sbb eax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x4, x26" ] }, "sbb rax, -1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /3", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "mvn w27, w4", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "sbcs x26, x4, x20", + "mov x4, x26" + ] + }, + "and eax, -1": { + "ExpectedInstructionCount": 6, + "Comment": "GROUP1 0x83 /4", + "ExpectedArm64ASM": [ + "mov w20, #0xffffffff", + "ands w26, w4, w20", "mrs x20, nzcv", "eor w20, w20, #0x20000000", "msr nzcv, x20", "mov x4, x26" ] }, - "and eax, -1": { - "ExpectedInstructionCount": 3, - "Comment": "GROUP1 0x83 /4", - "ExpectedArm64ASM": [ - "mov w20, #0xffffffff", - "ands w26, w4, w20", - "mov x4, x26" - ] - }, "and rax, -1": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 6, "Comment": "GROUP1 0x83 /4", "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "ands x26, x4, x20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x4, x26" ] }, "sub eax, -1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 4, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x4, x26" ] }, "sub rax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /5", "ExpectedArm64ASM": [ "mvn w27, w4", "adds x26, x4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x4, x26" ] }, @@ -954,7 +984,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "eor w26, w4, w20", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -964,35 +994,29 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "eor x26, x4, x20", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, "cmp eax, -1": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "mvn w27, w4", - "subs w26, w4, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs w26, w4, w20" ] }, "cmp rax, -1": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 2, "Comment": "GROUP1 0x83 /7", "ExpectedArm64ASM": [ "mvn w27, w4", - "adds x26, x4, #0x1 (1)", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "adds x26, x4, #0x1 (1)" ] }, "rol al, 2": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xC0 /0", "ExpectedArm64ASM": [ "mov w20, w4", @@ -1000,6 +1024,7 @@ "bfi w20, w20, #16, #16", "ror w20, w20, #30", "bfxil x4, x20, #0, #8", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -1007,13 +1032,14 @@ ] }, "ror al, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC0 /1", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #8, #8", "ror w20, w20, #2", "bfxil x4, x20, #0, #8", + "eor x20, x20, #0x80", "ubfx x20, x20, #7, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -1021,12 +1047,12 @@ ] }, "rcl al, 2": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 22, "Comment": "GROUP2 0xC0 /2", "ExpectedArm64ASM": [ "uxtb w20, w4", "mov w21, #0x0", - "cset w22, hs", + "cset w22, lo", "bfi x21, x20, #55, #8", "bfi x21, x22, #63, #1", "bfi x21, x20, #46, #8", @@ -1041,6 +1067,7 @@ "ror x20, x21, #62", "bfxil x4, x20, #0, #8", "ror x20, x21, #61", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -1048,10 +1075,10 @@ ] }, "rcr al, 2": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xC0 /3", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "uxtb w21, w4", "bfi x21, x20, #8, #1", "bfi x21, x21, #9, #9", @@ -1059,19 +1086,21 @@ "bfi x21, x21, #36, #9", "lsr x20, x21, #2", "bfxil x4, x20, #0, #8", - "ubfx x20, x21, #1, #1", + "eor x20, x21, #0x2", + "ubfx x20, x20, #1, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "msr nzcv, x21" ] }, "shl al, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC0 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #2", "cmn wzr, w26, lsl #24", - "ubfx x20, x4, #6, #1", + "eor x20, x4, #0x40", + "ubfx x20, x20, #6, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", "msr nzcv, x20", @@ -1079,12 +1108,13 @@ ] }, "shr al, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC0 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", "lsr w26, w20, #2", "cmn wzr, w26, lsl #24", + "eor x20, x20, #0x2", "ubfx x20, x20, #1, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -1093,12 +1123,13 @@ ] }, "sar al, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC0 /7", "ExpectedArm64ASM": [ "sxtb x20, w4", "asr w26, w20, #2", "cmn wzr, w26, lsl #24", + "eor x20, x20, #0x2", "ubfx x20, x20, #1, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -1107,13 +1138,14 @@ ] }, "rol ax, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /0", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #16, #16", "ror w20, w20, #30", "bfxil x4, x20, #0, #16", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -1121,35 +1153,38 @@ ] }, "rol eax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /0", "ExpectedArm64ASM": [ "ror w4, w4, #30", - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "msr nzcv, x21" ] }, "rol rax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /0", "ExpectedArm64ASM": [ "ror x4, x4, #62", - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "msr nzcv, x21" ] }, "ror ax, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /1", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #16, #16", "ror w20, w20, #2", "bfxil x4, x20, #0, #16", + "eor x20, x20, #0x8000", "ubfx x20, x20, #15, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -1157,34 +1192,36 @@ ] }, "ror eax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /1", "ExpectedArm64ASM": [ "ror w4, w4, #2", - "ubfx x20, x4, #31, #1", + "eor x20, x4, #0x80000000", + "ubfx x20, x20, #31, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "msr nzcv, x21" ] }, "ror rax, 2": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xC1 /1", "ExpectedArm64ASM": [ "ror x4, x4, #2", - "lsr x20, x4, #63", + "eor x20, x4, #0x8000000000000000", + "lsr x20, x20, #63", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "msr nzcv, x21" ] }, "rcl ax, 2": { - "ExpectedInstructionCount": 17, + "ExpectedInstructionCount": 18, "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "uxth w20, w4", "mov w21, #0x0", - "cset w22, hs", + "cset w22, lo", "bfi x21, x20, #47, #16", "bfi x21, x22, #63, #1", "bfi x21, x20, #30, #16", @@ -1195,6 +1232,7 @@ "ror x20, x21, #62", "bfxil x4, x20, #0, #16", "ror x20, x21, #61", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -1202,81 +1240,87 @@ ] }, "rcl eax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "lsl w20, w4, #2", - "cset w21, hs", + "cset w21, lo", "orr w20, w20, w4, lsr #31", - "ubfx x22, x4, #30, #1", + "eor x22, x4, #0x40000000", + "ubfx x22, x22, #30, #1", "lsl x22, x22, #29", "orr w4, w20, w21, lsl #1", "msr nzcv, x22" ] }, "rcl rax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "lsl x20, x4, #2", - "cset w21, hs", + "cset w21, lo", "orr x20, x20, x4, lsr #63", - "ubfx x22, x4, #62, #1", + "eor x22, x4, #0x4000000000000000", + "ubfx x22, x22, #62, #1", "lsl x22, x22, #29", "orr x4, x20, x21, lsl #1", "msr nzcv, x22" ] }, "rcr ax, 2": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "uxth w21, w4", "bfi x21, x20, #16, #1", "bfi x21, x21, #17, #17", "bfi x21, x21, #34, #17", "lsr x20, x21, #2", "bfxil x4, x20, #0, #16", - "ubfx x20, x21, #1, #1", + "eor x20, x21, #0x2", + "ubfx x20, x20, #1, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "msr nzcv, x21" ] }, "rcr eax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "lsr w20, w4, #2", - "cset w21, hs", + "cset w21, lo", "orr w20, w20, w4, lsl #31", - "ubfx x22, x4, #1, #1", + "eor x22, x4, #0x2", + "ubfx x22, x22, #1, #1", "lsl x22, x22, #29", "orr w4, w20, w21, lsl #30", "msr nzcv, x22" ] }, "rcr rax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "lsr x20, x4, #2", - "cset w21, hs", + "cset w21, lo", "orr x20, x20, x4, lsl #63", - "ubfx x22, x4, #1, #1", + "eor x22, x4, #0x2", + "ubfx x22, x22, #1, #1", "lsl x22, x22, #29", "orr x4, x20, x21, lsl #62", "msr nzcv, x22" ] }, "shl ax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #2", "cmn wzr, w26, lsl #16", - "ubfx x20, x4, #14, #1", + "eor x20, x4, #0x4000", + "ubfx x20, x20, #14, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", "msr nzcv, x20", @@ -1284,38 +1328,41 @@ ] }, "shl eax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #2", - "tst w26, w26", - "ubfx x20, x4, #30, #1", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x40000000", + "ubfx x20, x20, #30, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "shl rax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /4", "ExpectedArm64ASM": [ "lsl x26, x4, #2", - "tst x26, x26", - "ubfx x20, x4, #62, #1", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x4000000000000000", + "ubfx x20, x20, #62, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "shr ax, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "uxth w20, w4", "lsr w26, w20, #2", "cmn wzr, w26, lsl #16", + "eor x20, x20, #0x2", "ubfx x20, x20, #1, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -1324,38 +1371,41 @@ ] }, "shr eax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "lsr w26, w4, #2", - "tst w26, w26", - "ubfx x20, x4, #1, #1", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x2", + "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "shr rax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /5", "ExpectedArm64ASM": [ "lsr x26, x4, #2", - "tst x26, x26", - "ubfx x20, x4, #1, #1", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x2", + "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "sar ax, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /7", "ExpectedArm64ASM": [ "sxth x20, w4", "asr w26, w20, #2", "cmn wzr, w26, lsl #16", + "eor x20, x20, #0x2", "ubfx x20, x20, #1, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -1364,33 +1414,35 @@ ] }, "sar eax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /7", "ExpectedArm64ASM": [ "asr w26, w4, #2", - "tst w26, w26", - "ubfx x20, x4, #1, #1", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x2", + "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "sar rax, 2": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xC1 /7", "ExpectedArm64ASM": [ "asr x26, x4, #2", - "tst x26, x26", - "ubfx x20, x4, #1, #1", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x2", + "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "rol al, 1": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xd0 /0", "ExpectedArm64ASM": [ "mov w20, w4", @@ -1398,7 +1450,8 @@ "bfi w20, w20, #16, #16", "ror w20, w20, #31", "bfxil x4, x20, #0, #8", - "ubfx x21, x20, #0, #1", + "eor x21, x20, #0x1", + "ubfx x21, x21, #0, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "eor w20, w20, w20, lsr #7", @@ -1408,14 +1461,15 @@ ] }, "ror al, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd0 /1", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #8, #8", "ror w20, w20, #1", "bfxil x4, x20, #0, #8", - "ubfx x21, x20, #7, #1", + "eor x21, x20, #0x80", + "ubfx x21, x21, #7, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "eor w20, w20, w20, lsr #1", @@ -1425,13 +1479,14 @@ ] }, "rcl al, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd0 /2", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, hs", + "cset w21, lo", "orr w21, w21, w20, lsl #1", - "ubfx x22, x20, #7, #1", + "eor x22, x20, #0x80", + "ubfx x22, x22, #7, #1", "mrs x23, nzcv", "bfi w23, w22, #29, #1", "eor w20, w21, w20", @@ -1442,12 +1497,13 @@ ] }, "rcr al, 1": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xd0 /3", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, hs", - "ubfx x22, x20, #0, #1", + "cset w21, lo", + "eor x22, x20, #0x1", + "ubfx x22, x22, #0, #1", "mrs x23, nzcv", "bfi w23, w22, #29, #1", "ubfx w20, w20, #1, #7", @@ -1460,12 +1516,13 @@ ] }, "shl al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd0 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #1", "cmn wzr, w26, lsl #24", - "ubfx x20, x4, #7, #1", + "eor x20, x4, #0x80", + "ubfx x20, x20, #7, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", "eor w21, w26, w4", @@ -1476,13 +1533,14 @@ ] }, "shr al, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd0 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", "lsr w26, w20, #1", "cmn wzr, w26, lsl #24", - "ubfx x21, x20, #0, #1", + "eor x21, x20, #0x1", + "ubfx x21, x21, #0, #1", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", "ubfx x20, x20, #7, #1", @@ -1492,12 +1550,13 @@ ] }, "sar al, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd0 /7", "ExpectedArm64ASM": [ "sxtb x20, w4", "asr w26, w20, #1", "cmn wzr, w26, lsl #24", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -1506,14 +1565,15 @@ ] }, "rol ax, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd1 /0", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #16, #16", "ror w20, w20, #31", "bfxil x4, x20, #0, #16", - "ubfx x21, x20, #0, #1", + "eor x21, x20, #0x1", + "ubfx x21, x21, #0, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "eor w20, w20, w20, lsr #15", @@ -1523,11 +1583,12 @@ ] }, "rol eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd1 /0", "ExpectedArm64ASM": [ "ror w4, w4, #31", - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "eor w20, w4, w4, lsr #31", @@ -1537,11 +1598,12 @@ ] }, "rol rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd1 /0", "ExpectedArm64ASM": [ "ror x4, x4, #63", - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "eor x20, x4, x4, lsr #63", @@ -1551,14 +1613,15 @@ ] }, "ror ax, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd1 /1", "ExpectedArm64ASM": [ "mov w20, w4", "bfi w20, w4, #16, #16", "ror w20, w20, #1", "bfxil x4, x20, #0, #16", - "ubfx x21, x20, #15, #1", + "eor x21, x20, #0x8000", + "ubfx x21, x21, #15, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "eor w20, w20, w20, lsr #1", @@ -1568,11 +1631,12 @@ ] }, "ror eax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd1 /1", "ExpectedArm64ASM": [ "ror w4, w4, #1", - "ubfx x20, x4, #31, #1", + "eor x20, x4, #0x80000000", + "ubfx x20, x20, #31, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "eor w20, w4, w4, lsr #1", @@ -1582,11 +1646,12 @@ ] }, "ror rax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd1 /1", "ExpectedArm64ASM": [ "ror x4, x4, #1", - "lsr x20, x4, #63", + "eor x20, x4, #0x8000000000000000", + "lsr x20, x20, #63", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "eor x20, x4, x4, lsr #1", @@ -1596,13 +1661,14 @@ ] }, "rcl ax, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ "uxth w20, w4", - "cset w21, hs", + "cset w21, lo", "orr w21, w21, w20, lsl #1", - "ubfx x22, x20, #15, #1", + "eor x22, x20, #0x8000", + "ubfx x22, x22, #15, #1", "mrs x23, nzcv", "bfi w23, w22, #29, #1", "eor w20, w21, w20", @@ -1613,13 +1679,14 @@ ] }, "rcl eax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ "mov w20, w4", - "cset w21, hs", + "cset w21, lo", "orr w4, w21, w20, lsl #1", - "ubfx x21, x20, #31, #1", + "eor x21, x20, #0x80000000", + "ubfx x21, x21, #31, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "eor w20, w4, w20", @@ -1629,12 +1696,13 @@ ] }, "rcl rax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset w20, lo", "orr x20, x20, x4, lsl #1", - "lsr x21, x4, #63", + "eor x21, x4, #0x8000000000000000", + "lsr x21, x21, #63", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "eor x21, x20, x4", @@ -1645,11 +1713,12 @@ ] }, "rcr ax, 1": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, hs", - "ubfx x21, x4, #0, #1", + "cset w20, lo", + "eor x21, x4, #0x1", + "ubfx x21, x21, #0, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "ubfx w21, w4, #1, #15", @@ -1662,11 +1731,12 @@ ] }, "rcr eax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, hs", - "ubfx x21, x4, #0, #1", + "cset w20, lo", + "eor x21, x4, #0x1", + "ubfx x21, x21, #0, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "extr w4, w20, w4, #1", @@ -1677,11 +1747,12 @@ ] }, "rcr rax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, hs", - "ubfx x21, x4, #0, #1", + "cset w20, lo", + "eor x21, x4, #0x1", + "ubfx x21, x21, #0, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "extr x4, x20, x4, #1", @@ -1692,12 +1763,13 @@ ] }, "shl ax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #1", "cmn wzr, w26, lsl #16", - "ubfx x20, x4, #15, #1", + "eor x20, x4, #0x8000", + "ubfx x20, x20, #15, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", "eor w21, w26, w4", @@ -1708,45 +1780,48 @@ ] }, "shl eax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ "lsl w26, w4, #1", - "tst w26, w26", - "ubfx x20, x4, #31, #1", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x80000000", + "ubfx x20, x20, #31, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w26, w4", - "ubfx x21, x21, #31, #1", - "orr w20, w20, w21, lsl #28", + "bfi w21, w20, #29, #1", + "eor w20, w26, w4", + "ubfx x20, x20, #31, #1", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20", "mov x4, x26" ] }, "shl rax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd1 /4", "ExpectedArm64ASM": [ "lsl x26, x4, #1", - "tst x26, x26", - "lsr x20, x4, #63", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x8000000000000000", + "lsr x20, x20, #63", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor x21, x26, x4", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "bfi w21, w20, #29, #1", + "eor x20, x26, x4", + "lsr x20, x20, #63", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20", "mov x4, x26" ] }, "shr ax, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd1 /5", "ExpectedArm64ASM": [ "uxth w20, w4", "lsr w26, w20, #1", "cmn wzr, w26, lsl #16", - "ubfx x21, x20, #0, #1", + "eor x21, x20, #0x1", + "ubfx x21, x21, #0, #1", "mrs x22, nzcv", "orr w21, w22, w21, lsl #29", "ubfx x20, x20, #15, #1", @@ -1756,42 +1831,45 @@ ] }, "shr eax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd1 /5", "ExpectedArm64ASM": [ "lsr w26, w4, #1", - "tst w26, w26", - "ubfx x20, x4, #0, #1", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "ubfx x21, x4, #31, #1", - "orr w20, w20, w21, lsl #28", + "bfi w21, w20, #29, #1", + "ubfx x20, x4, #31, #1", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20", "mov x4, x26" ] }, "shr rax, 1": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd1 /5", "ExpectedArm64ASM": [ "lsr x26, x4, #1", - "tst x26, x26", - "ubfx x20, x4, #0, #1", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "lsr x21, x4, #63", - "orr w20, w20, w21, lsl #28", + "bfi w21, w20, #29, #1", + "lsr x20, x4, #63", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20", "mov x4, x26" ] }, "sar ax, 1": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xd1 /7", "ExpectedArm64ASM": [ "sxth x20, w4", "asr w26, w20, #1", "cmn wzr, w26, lsl #16", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -1800,44 +1878,47 @@ ] }, "sar eax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd1 /7", "ExpectedArm64ASM": [ "asr w26, w4, #1", - "tst w26, w26", - "ubfx x20, x4, #0, #1", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "sar rax, 1": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd1 /7", "ExpectedArm64ASM": [ "asr x26, x4, #1", - "tst x26, x26", - "ubfx x20, x4, #0, #1", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "rol al, cl": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 16, "Comment": "GROUP2 0xd2 /0", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x38", + "cbz x20, #+0x3c", "mov w20, w4", "bfi w20, w4, #8, #8", "bfi w20, w20, #16, #16", "neg w21, w5", "ror w20, w20, w21", "bfxil x4, x20, #0, #8", - "ubfx x21, x20, #0, #1", + "eor x21, x20, #0x1", + "ubfx x21, x21, #0, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "eor w20, w20, w20, lsr #7", @@ -1847,17 +1928,18 @@ ] }, "ror al, cl": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": "GROUP2 0xd2 /1", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x34", + "cbz x20, #+0x38", "mov w20, w4", "bfi w20, w4, #8, #8", "bfi w20, w20, #16, #16", "ror w20, w20, w5", "bfxil x4, x20, #0, #8", - "ubfx x21, x20, #7, #1", + "eor x21, x20, #0x80", + "ubfx x21, x21, #7, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "eor w20, w20, w20, lsr #1", @@ -1867,15 +1949,15 @@ ] }, "rcl al, cl": { - "ExpectedInstructionCount": 30, + "ExpectedInstructionCount": 31, "Comment": "GROUP2 0xd2 /2", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x74", + "cbz x20, #+0x78", "and w20, w5, #0x1f", "uxtb w21, w4", "mov w22, #0x0", - "cset w23, hs", + "cset w23, lo", "bfi x22, x21, #55, #8", "bfi x22, x23, #63, #1", "bfi x22, x21, #46, #8", @@ -1893,7 +1975,8 @@ "mov w23, #0x3f", "sub x20, x23, x20", "ror x20, x22, x20", - "ubfx x22, x20, #0, #1", + "eor x22, x20, #0x1", + "ubfx x22, x22, #0, #1", "mrs x23, nzcv", "bfi w23, w22, #29, #1", "eor x20, x20, x21, lsr #7", @@ -1903,13 +1986,13 @@ ] }, "rcr al, cl": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 21, "Comment": "GROUP2 0xd2 /3", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x4c", + "cbz x20, #+0x50", "and w20, w5, #0x1f", - "cset w21, hs", + "cset w21, lo", "uxtb w22, w4", "bfi x22, x21, #8, #1", "bfi x22, x22, #9, #9", @@ -1919,6 +2002,7 @@ "bfxil x4, x21, #0, #8", "sub w20, w20, #0x1 (1)", "lsr w20, w22, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x22, nzcv", "bfi w22, w20, #29, #1", @@ -1929,17 +2013,18 @@ ] }, "shl al, cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd2 /4", "ExpectedArm64ASM": [ "lsl w20, w4, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x28", + "cbz w0, #+0x2c", "cmn wzr, w20, lsl #24", "mov x26, x20", + "mvn x0, x20", "eor w2, w4, w20", "mrs x1, nzcv", - "lsr x0, x20, #8", + "lsr x0, x0, #8", "bfi w1, w0, #29, #1", "lsr w2, w2, #7", "bfi w1, w2, #28, #1", @@ -1948,17 +2033,18 @@ ] }, "shr al, cl": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 16, "Comment": "GROUP2 0xd2 /5", "ExpectedArm64ASM": [ "uxtb w20, w4", "lsr w21, w20, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x2c", + "cbz w0, #+0x30", "cmn wzr, w21, lsl #24", "mov x26, x21", "sub x0, x5, #0x1 (1)", "lsr w0, w20, w0", + "mvn x0, x0", "eor w2, w20, w21", "mrs x1, nzcv", "bfi w1, w0, #29, #1", @@ -1969,17 +2055,18 @@ ] }, "sar al, cl": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xd2 /7", "ExpectedArm64ASM": [ "sxtb x20, w4", "asr w21, w20, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x20", + "cbz w0, #+0x24", "cmn wzr, w21, lsl #24", "mov x26, x21", "sub x0, x5, #0x1 (1)", "lsr w0, w20, w0", + "mvn x0, x0", "mrs x1, nzcv", "bfi w1, w0, #29, #1", "msr nzcv, x1", @@ -1987,17 +2074,18 @@ ] }, "rol ax, cl": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": "GROUP2 0xd3 /0", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x34", + "cbz x20, #+0x38", "mov w20, w4", "bfi w20, w4, #16, #16", "neg w21, w5", "ror w20, w20, w21", "bfxil x4, x20, #0, #16", - "ubfx x21, x20, #0, #1", + "eor x21, x20, #0x1", + "ubfx x21, x21, #0, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "eor w20, w20, w20, lsr #15", @@ -2007,14 +2095,15 @@ ] }, "rol eax, cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /0", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x2c", + "cbz x20, #+0x30", "neg w20, w5", "ror w4, w4, w20", - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "eor w20, w4, w4, lsr #31", @@ -2026,14 +2115,15 @@ ] }, "rol rax, cl": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd3 /0", "ExpectedArm64ASM": [ "and x20, x5, #0x3f", - "cbz x20, #+0x28", + "cbz x20, #+0x2c", "neg x20, x5", "ror x4, x4, x20", - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "eor x20, x4, x4, lsr #63", @@ -2043,16 +2133,17 @@ ] }, "ror ax, cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /1", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x30", + "cbz x20, #+0x34", "mov w20, w4", "bfi w20, w4, #16, #16", "ror w20, w20, w5", "bfxil x4, x20, #0, #16", - "ubfx x21, x20, #15, #1", + "eor x21, x20, #0x8000", + "ubfx x21, x21, #15, #1", "mrs x22, nzcv", "bfi w22, w21, #29, #1", "eor w20, w20, w20, lsr #1", @@ -2062,13 +2153,14 @@ ] }, "ror eax, cl": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xd3 /1", "ExpectedArm64ASM": [ "and x20, x5, #0x1f", - "cbz x20, #+0x28", + "cbz x20, #+0x2c", "ror w4, w4, w5", - "ubfx x20, x4, #31, #1", + "eor x20, x4, #0x80000000", + "ubfx x20, x20, #31, #1", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "eor w20, w4, w4, lsr #1", @@ -2080,13 +2172,14 @@ ] }, "ror rax, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd3 /1", "ExpectedArm64ASM": [ "and x20, x5, #0x3f", - "cbz x20, #+0x24", + "cbz x20, #+0x28", "ror x4, x4, x5", - "lsr x20, x4, #63", + "eor x20, x4, #0x8000000000000000", + "lsr x20, x20, #63", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "eor x20, x4, x4, lsr #1", @@ -2096,15 +2189,15 @@ ] }, "rcl ax, cl": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x64", + "cbz x20, #+0x68", "and w20, w5, #0x1f", "uxth w21, w4", "mov w22, #0x0", - "cset w23, hs", + "cset w23, lo", "bfi x22, x21, #47, #16", "bfi x22, x23, #63, #1", "bfi x22, x21, #30, #16", @@ -2118,7 +2211,8 @@ "mov w23, #0x3f", "sub x20, x23, x20", "ror x20, x22, x20", - "ubfx x22, x20, #0, #1", + "eor x22, x20, #0x1", + "ubfx x22, x22, #0, #1", "mrs x23, nzcv", "bfi w23, w22, #29, #1", "eor x20, x20, x21, lsr #15", @@ -2128,18 +2222,19 @@ ] }, "rcl eax, cl": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 21, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x48", + "cbz x20, #+0x4c", "lsl w20, w4, w5", - "cset w21, hs", + "cset w21, lo", "neg w22, w5", "lsr w23, w4, w22", "orr w20, w20, w23, lsr #1", "lsr w22, w4, w22", - "ubfx x23, x22, #0, #1", + "eor x23, x22, #0x1", + "ubfx x23, x23, #0, #1", "mrs x24, nzcv", "bfi w24, w23, #29, #1", "sub w23, w5, #0x1 (1)", @@ -2154,18 +2249,19 @@ ] }, "rcl rax, cl": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 19, "Comment": "GROUP2 0xd3 /2", "ExpectedArm64ASM": [ "and x20, x5, #0x3f", - "cbz x20, #+0x44", + "cbz x20, #+0x48", "lsl x20, x4, x5", - "cset w21, hs", + "cset w21, lo", "neg x22, x5", "lsr x23, x4, x22", "orr x20, x20, x23, lsr #1", "lsr x22, x4, x22", - "ubfx x23, x22, #0, #1", + "eor x23, x22, #0x1", + "ubfx x23, x23, #0, #1", "mrs x24, nzcv", "bfi w24, w23, #29, #1", "sub x23, x5, #0x1 (1)", @@ -2178,13 +2274,13 @@ ] }, "rcr ax, cl": { - "ExpectedInstructionCount": 19, + "ExpectedInstructionCount": 20, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x48", + "cbz x20, #+0x4c", "and w20, w5, #0x1f", - "cset w21, hs", + "cset w21, lo", "uxth w22, w4", "bfi x22, x21, #16, #1", "bfi x22, x22, #17, #17", @@ -2193,6 +2289,7 @@ "bfxil x4, x21, #0, #16", "sub w20, w20, #0x1 (1)", "lsr w20, w22, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x22, nzcv", "bfi w22, w20, #29, #1", @@ -2203,18 +2300,19 @@ ] }, "rcr eax, cl": { - "ExpectedInstructionCount": 20, + "ExpectedInstructionCount": 21, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ "and w20, w5, #0x1f", - "cbz x20, #+0x48", + "cbz x20, #+0x4c", "lsr w20, w4, w5", - "cset w21, hs", + "cset w21, lo", "neg w22, w5", "lsl w23, w4, w22", "orr w20, w20, w23, lsl #1", "sub w23, w5, #0x1 (1)", "lsr w23, w4, w23", + "eor x23, x23, #0x1", "ubfx x23, x23, #0, #1", "mrs x24, nzcv", "bfi w24, w23, #29, #1", @@ -2229,18 +2327,19 @@ ] }, "rcr rax, cl": { - "ExpectedInstructionCount": 18, + "ExpectedInstructionCount": 19, "Comment": "GROUP2 0xd3 /3", "ExpectedArm64ASM": [ "and x20, x5, #0x3f", - "cbz x20, #+0x44", + "cbz x20, #+0x48", "lsr x20, x4, x5", - "cset w21, hs", + "cset w21, lo", "neg x22, x5", "lsl x23, x4, x22", "orr x20, x20, x23, lsl #1", "sub x23, x5, #0x1 (1)", "lsr x23, x4, x23", + "eor x23, x23, #0x1", "ubfx x23, x23, #0, #1", "mrs x24, nzcv", "bfi w24, w23, #29, #1", @@ -2253,17 +2352,18 @@ ] }, "shl ax, cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ "lsl w20, w4, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x28", + "cbz w0, #+0x2c", "cmn wzr, w20, lsl #16", "mov x26, x20", + "mvn x0, x20", "eor w2, w4, w20", "mrs x1, nzcv", - "lsr x0, x20, #16", + "lsr x0, x0, #16", "bfi w1, w0, #29, #1", "lsr w2, w2, #15", "bfi w1, w2, #28, #1", @@ -2272,15 +2372,16 @@ ] }, "shl eax, cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ "lsl w20, w4, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x28", + "cbz w0, #+0x2c", "ands w26, w20, w20", "neg w0, w5", "lsr w0, w4, w0", + "mvn x0, x0", "eor w2, w4, w20", "mrs x1, nzcv", "bfi w1, w0, #29, #1", @@ -2291,15 +2392,16 @@ ] }, "shl rax, cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /4", "ExpectedArm64ASM": [ "lsl x20, x4, x5", "and w0, w5, #0x3f", - "cbz x0, #+0x28", + "cbz x0, #+0x2c", "ands x26, x20, x20", "neg x0, x5", "lsr x0, x4, x0", + "mvn x0, x0", "eor x2, x4, x20", "mrs x1, nzcv", "bfi w1, w0, #29, #1", @@ -2310,17 +2412,18 @@ ] }, "shr ax, cl": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 16, "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ "uxth w20, w4", "lsr w21, w20, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x2c", + "cbz w0, #+0x30", "cmn wzr, w21, lsl #16", "mov x26, x21", "sub x0, x5, #0x1 (1)", "lsr w0, w20, w0", + "mvn x0, x0", "eor w2, w20, w21", "mrs x1, nzcv", "bfi w1, w0, #29, #1", @@ -2331,15 +2434,16 @@ ] }, "shr eax, cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ "lsr w20, w4, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x28", + "cbz w0, #+0x2c", "ands w26, w20, w20", "sub x0, x5, #0x1 (1)", "lsr w0, w4, w0", + "mvn x0, x0", "eor w2, w4, w20", "mrs x1, nzcv", "bfi w1, w0, #29, #1", @@ -2350,15 +2454,16 @@ ] }, "shr rax, cl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 14, "Comment": "GROUP2 0xd3 /5", "ExpectedArm64ASM": [ "lsr x20, x4, x5", "and w0, w5, #0x3f", - "cbz x0, #+0x28", + "cbz x0, #+0x2c", "ands x26, x20, x20", "sub x0, x5, #0x1 (1)", "lsr x0, x4, x0", + "mvn x0, x0", "eor x2, x4, x20", "mrs x1, nzcv", "bfi w1, w0, #29, #1", @@ -2369,17 +2474,18 @@ ] }, "sar ax, cl": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ "sxth x20, w4", "asr w21, w20, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x20", + "cbz w0, #+0x24", "cmn wzr, w21, lsl #16", "mov x26, x21", "sub x0, x5, #0x1 (1)", "lsr w0, w20, w0", + "mvn x0, x0", "mrs x1, nzcv", "bfi w1, w0, #29, #1", "msr nzcv, x1", @@ -2387,15 +2493,16 @@ ] }, "sar eax, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ "asr w20, w4, w5", "and w0, w5, #0x1f", - "cbz w0, #+0x1c", + "cbz w0, #+0x20", "ands w26, w20, w20", "sub x0, x5, #0x1 (1)", "lsr w0, w4, w0", + "mvn x0, x0", "mrs x1, nzcv", "bfi w1, w0, #29, #1", "msr nzcv, x1", @@ -2403,15 +2510,16 @@ ] }, "sar rax, cl": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd3 /7", "ExpectedArm64ASM": [ "asr x20, x4, x5", "and w0, w5, #0x3f", - "cbz x0, #+0x1c", + "cbz x0, #+0x20", "ands x26, x20, x20", "sub x0, x5, #0x1 (1)", "lsr x0, x4, x0", + "mvn x0, x0", "mrs x1, nzcv", "bfi w1, w0, #29, #1", "msr nzcv, x1", @@ -2419,11 +2527,14 @@ ] }, "test bl, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xf6 /0", "ExpectedArm64ASM": [ "and w26, w7, #0x1", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "not bl": { @@ -2441,18 +2552,15 @@ ] }, "neg bl": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf6 /3", "ExpectedArm64ASM": [ "cmp wzr, w7, lsl #24", "neg w26, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "mov x21, x7", - "bfxil x21, x26, #0, #8", - "msr nzcv, x20", + "mov x20, x7", + "bfxil x20, x26, #0, #8", "mov x27, x7", - "mov x7, x21" + "mov x7, x20" ] }, "mul bl": { @@ -2465,7 +2573,7 @@ "bfxil x4, x20, #0, #16", "ubfx x20, x20, #8, #8", "cmp x20, #0x0 (0)", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul bl": { @@ -2479,7 +2587,7 @@ "sbfx x21, x20, #8, #8", "sbfx x20, x20, #7, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "div bl": { @@ -2515,47 +2623,65 @@ ] }, "test bx, 1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ "and w26, w7, #0x1", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test ebx, 1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "ands w26, w7, #0x1" + "ands w26, w7, #0x1", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test rbx, 1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "ands x26, x7, #0x1" + "ands x26, x7, #0x1", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test bx, -1": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 5, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ "mov x26, x7", - "cmn wzr, w26, lsl #16" + "cmn wzr, w26, lsl #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test ebx, -1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "ands w26, w7, w7" + "ands w26, w7, w7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "test rbx, -1": { - "ExpectedInstructionCount": 1, + "ExpectedInstructionCount": 4, "Comment": "GROUP2 0xf7 /0", "ExpectedArm64ASM": [ - "ands x26, x7, x7" + "ands x26, x7, x7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "not bx": { @@ -2580,40 +2706,31 @@ ] }, "neg bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "cmp wzr, w7, lsl #16", "neg w26, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "mov x21, x7", - "bfxil x21, x26, #0, #16", - "msr nzcv, x20", + "mov x20, x7", + "bfxil x20, x26, #0, #16", "mov x27, x7", - "mov x7, x21" + "mov x7, x20" ] }, "neg ebx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "negs w26, w7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x7", "mov x7, x26" ] }, "neg rbx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "GROUP2 0xf7 /2", "ExpectedArm64ASM": [ "negs x26, x7", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x27, x7", "mov x7, x26" ] @@ -2629,7 +2746,7 @@ "ubfx x20, x20, #16, #16", "bfxil x6, x20, #0, #16", "cmp x20, #0x0 (0)", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "mul ebx": { @@ -2642,7 +2759,7 @@ "mov w4, w20", "lsr x6, x20, #32", "cmp x6, #0x0 (0)", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "mul rbx": { @@ -2652,7 +2769,7 @@ "mul x20, x7, x4", "umulh x6, x7, x4", "cmp x6, #0x0 (0)", - "ccmn xzr, #0, #nzCV, eq", + "ccmp xzr, #0, #nzcV, eq", "mov x4, x20" ] }, @@ -2668,7 +2785,7 @@ "bfxil x6, x21, #0, #16", "sbfx x20, x20, #15, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul ebx": { @@ -2684,7 +2801,7 @@ "sxtw x20, w20", "sbfx x20, x20, #31, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul rbx": { @@ -2695,7 +2812,7 @@ "mul x4, x7, x4", "asr x20, x4, #63", "cmp x6, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "div bx": { diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index 0b9b669a1..ebd50e449 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -95,14 +95,14 @@ "ubfx w23, w23, #4, #1", "orr x22, x23, x22", "cmp x20, #0x99 (153)", - "cset x23, hi", - "orr x21, x21, x23", + "cset x23, ls", + "and x21, x21, x23", "add x23, x20, #0x6 (6)", "cmp x22, #0x0 (0)", "csel x20, x23, x20, ne", "add x23, x20, #0x60 (96)", "cmp x21, #0x0 (0)", - "csel x26, x23, x20, ne", + "csel x26, x23, x20, eq", "bfxil w4, w26, #0, #8", "cmn wzr, w26, lsl #24", "mrs x20, nzcv", @@ -112,11 +112,11 @@ ] }, "das": { - "ExpectedInstructionCount": 26, + "ExpectedInstructionCount": 27, "Comment": "0x2f", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, hs", + "cset w21, lo", "and x22, x20, #0xf", "cmp x22, #0x9 (9)", "cset x22, hi", @@ -137,14 +137,15 @@ "csel x26, x24, x20, ne", "bfxil w4, w26, #0, #8", "cmn wzr, w26, lsl #24", - "mrs x20, nzcv", - "orr w20, w20, w23, lsl #29", + "eor x20, x23, #0x1", + "mrs x21, nzcv", + "orr w20, w21, w20, lsl #29", "eor w27, w26, w22, lsl #4", "msr nzcv, x20" ] }, "aaa": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": "0x37", "ExpectedArm64ASM": [ "and x20, x4, #0xf", @@ -153,18 +154,19 @@ "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x21, x20", - "lsl x21, x20, #29", + "eor x21, x20, #0x1", + "lsl x21, x21, #29", "eor w27, w26, w20, lsl #4", "msr nzcv, x21", "add w20, w4, #0x106 (262)", - "csel w20, w20, w4, hs", + "csel w20, w20, w4, lo", "mov w21, #0xff0f", "and w20, w20, w21", "bfxil w4, w20, #0, #16" ] }, "aas": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": "0x3f", "ExpectedArm64ASM": [ "and x20, x4, #0xf", @@ -173,11 +175,12 @@ "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x21, x20", - "lsl x21, x20, #29", + "eor x21, x20, #0x1", + "lsl x21, x21, #29", "eor w27, w26, w20, lsl #4", "msr nzcv, x21", "sub w20, w4, #0x106 (262)", - "csel w20, w20, w4, hs", + "csel w20, w20, w4, lo", "mov w21, #0xff0f", "and w20, w20, w21", "bfxil w4, w20, #0, #16" @@ -328,7 +331,7 @@ ] }, "aam": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 11, "Comment": "0xd4", "ExpectedArm64ASM": [ "uxtb w20, w4", @@ -338,11 +341,14 @@ "msub x20, x2, x21, x20", "add x26, x20, x22, lsl #8", "bfxil w4, w26, #0, #16", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "aad": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 10, "Comment": "0xd5", "ExpectedArm64ASM": [ "lsr w20, w4, #8", @@ -351,11 +357,14 @@ "add x20, x4, x20", "and x26, x20, #0xff", "bfxil w4, w26, #0, #16", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "db 0xd4, 0x40": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 11, "Comment": [ "aam with a different immediate byte base", "0xd4" @@ -368,11 +377,14 @@ "msub x20, x2, x21, x20", "add x26, x20, x22, lsl #8", "bfxil w4, w26, #0, #16", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "db 0xd5, 0x40": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 9, "Comment": [ "aad with a different immediate byte base", "0xd5" @@ -383,14 +395,17 @@ "add x20, x4, x20", "and x26, x20, #0xff", "bfxil w4, w26, #0, #16", - "cmn wzr, w26, lsl #24" + "cmn wzr, w26, lsl #24", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "salc": { "ExpectedInstructionCount": 2, "Comment": "0xd6", "ExpectedArm64ASM": [ - "csetm w20, hs", + "csetm w20, lo", "bfxil w4, w20, #0, #8" ] } diff --git a/unittests/InstructionCountCI/SSE42_Strings.json b/unittests/InstructionCountCI/SSE42_Strings.json index 1f88c8625..35edf8bb0 100644 --- a/unittests/InstructionCountCI/SSE42_Strings.json +++ b/unittests/InstructionCountCI/SSE42_Strings.json @@ -36,7 +36,7 @@ }, "Instructions": { "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": { - "ExpectedInstructionCount": 35, + "ExpectedInstructionCount": 36, "Comment": [ "0x66 0x0f 0x3A 0x60" ], @@ -75,11 +75,12 @@ "uxth w0, w20", "fmov s16, w0", "mov w26, #0x1", + "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "pcmpestri xmm0, xmm1, 0_0_00_00_00b": { - "ExpectedInstructionCount": 42, + "ExpectedInstructionCount": 43, "Comment": [ "0x66 0x0f 0x3A 0x61" ], @@ -125,11 +126,12 @@ "cmp x21, #0x0 (0)", "csel x5, x22, x23, eq", "mov w26, #0x1", + "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "pcmpistrm xmm0, xmm1, 0_0_00_00_00b": { - "ExpectedInstructionCount": 33, + "ExpectedInstructionCount": 34, "Comment": [ "0x66 0x0f 0x3A 0x62" ], @@ -166,11 +168,12 @@ "uxth w0, w20", "fmov s16, w0", "mov w26, #0x1", + "eor w20, w20, #0x20000000", "msr nzcv, x20" ] }, "pcmpistri xmm0, xmm1, 0_0_00_00_00b": { - "ExpectedInstructionCount": 40, + "ExpectedInstructionCount": 41, "Comment": [ "0x66 0x0f 0x3A 0x63" ], @@ -214,6 +217,7 @@ "cmp x21, #0x0 (0)", "csel x5, x22, x23, eq", "mov w26, #0x1", + "eor w20, w20, #0x20000000", "msr nzcv, x20" ] } diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index b03490147..5ca2bf494 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -210,13 +210,13 @@ "fcmp s16, s17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -227,13 +227,13 @@ "fcmp s16, s17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -294,7 +294,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0x42", "ExpectedArm64ASM": [ - "csel w20, w7, w4, hs", + "csel w20, w7, w4, lo", "bfxil x4, x20, #0, #16" ] }, @@ -302,21 +302,21 @@ "ExpectedInstructionCount": 1, "Comment": "0x0f 0x42", "ExpectedArm64ASM": [ - "csel w4, w7, w4, hs" + "csel w4, w7, w4, lo" ] }, "cmovb rax, rbx": { "ExpectedInstructionCount": 1, "Comment": "0x0f 0x42", "ExpectedArm64ASM": [ - "csel x4, x7, x4, hs" + "csel x4, x7, x4, lo" ] }, "cmovnb ax, bx": { "ExpectedInstructionCount": 2, "Comment": "0x0f 0x43", "ExpectedArm64ASM": [ - "csel w20, w7, w4, lo", + "csel w20, w7, w4, hs", "bfxil x4, x20, #0, #16" ] }, @@ -324,14 +324,14 @@ "ExpectedInstructionCount": 1, "Comment": "0x0f 0x43", "ExpectedArm64ASM": [ - "csel w4, w7, w4, lo" + "csel w4, w7, w4, hs" ] }, "cmovnb rax, rbx": { "ExpectedInstructionCount": 1, "Comment": "0x0f 0x43", "ExpectedArm64ASM": [ - "csel x4, x7, x4, lo" + "csel x4, x7, x4, hs" ] }, "cmovz ax, bx": { @@ -379,53 +379,47 @@ ] }, "cmovbe ax, bx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x0f 0x46", "ExpectedArm64ASM": [ - "csel w20, w7, w4, hs", - "csel w20, w7, w20, eq", + "csel w20, w7, w4, ls", "bfxil x4, x20, #0, #16" ] }, "cmovbe eax, ebx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0x0f 0x46", "ExpectedArm64ASM": [ - "csel w20, w7, w4, hs", - "csel w4, w7, w20, eq" + "csel w4, w7, w4, ls" ] }, "cmovbe rax, rbx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0x0f 0x46", "ExpectedArm64ASM": [ - "csel x20, x7, x4, hs", - "csel x4, x7, x20, eq" + "csel x4, x7, x4, ls" ] }, "cmovnbe ax, bx": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x0f 0x47", "ExpectedArm64ASM": [ - "csel w20, w7, w4, lo", - "csel w20, w20, w4, ne", + "csel w20, w7, w4, hi", "bfxil x4, x20, #0, #16" ] }, "cmovnbe eax, ebx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0x0f 0x47", "ExpectedArm64ASM": [ - "csel w20, w7, w4, lo", - "csel w4, w20, w4, ne" + "csel w4, w7, w4, hi" ] }, "cmovnbe rax, rbx": { - "ExpectedInstructionCount": 2, + "ExpectedInstructionCount": 1, "Comment": "0x0f 0x47", "ExpectedArm64ASM": [ - "csel x20, x7, x4, lo", - "csel x4, x20, x4, ne" + "csel x4, x7, x4, hi" ] }, "cmovs ax, bx": { @@ -1175,7 +1169,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0x92", "ExpectedArm64ASM": [ - "cset x20, hs", + "cset x20, lo", "bfxil x4, x20, #0, #8" ] }, @@ -1183,7 +1177,7 @@ "ExpectedInstructionCount": 2, "Comment": "0x0f 0x93", "ExpectedArm64ASM": [ - "cset x20, lo", + "cset x20, hs", "bfxil x4, x20, #0, #8" ] }, @@ -1204,21 +1198,18 @@ ] }, "setbe al": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 2, "Comment": "0x0f 0x96", "ExpectedArm64ASM": [ - "mov w20, #0x1", - "cset x21, hs", - "csel x20, x20, x21, eq", + "cset x20, ls", "bfxil x4, x20, #0, #8" ] }, "setnbe al": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 2, "Comment": "0x0f 0x97", "ExpectedArm64ASM": [ - "cset x20, lo", - "csel x20, x20, xzr, ne", + "cset x20, hi", "bfxil x4, x20, #0, #8" ] }, @@ -1314,70 +1305,76 @@ ] }, "bt ax, bx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "and x20, x7, #0xf", "lsr w20, w4, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt [rax], bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", "sbfx x21, x7, #3, #13", "ldrb w21, [x4, x21, sxtx]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt eax, ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "lsr w20, w4, w7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt [rax], ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", "sbfx x21, x7, #3, #29", "ldrb w21, [x4, x21, sxtx]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "lsr x20, x4, x7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt [rax], rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", "asr x21, x7, #3", "ldrb w21, [x4, x21, sxtx]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" @@ -1389,7 +1386,7 @@ "ExpectedArm64ASM": [] }, "shld ax, bx, 1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 15, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1398,7 +1395,8 @@ "lsr w20, w20, #15", "orr x26, x22, x20", "cmn wzr, w26, lsl #16", - "ubfx x20, x21, #15, #1", + "eor x20, x21, #0x8000", + "ubfx x20, x20, #15, #1", "mrs x22, nzcv", "orr w20, w22, w20, lsl #29", "eor w21, w26, w21", @@ -1409,7 +1407,7 @@ ] }, "shld ax, bx, 15": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1418,7 +1416,8 @@ "lsr w20, w20, #1", "orr x26, x22, x20", "cmn wzr, w26, lsl #16", - "ubfx x20, x21, #1, #1", + "eor x20, x21, #0x2", + "ubfx x20, x20, #1, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", "msr nzcv, x20", @@ -1426,7 +1425,7 @@ ] }, "shld ax, bx, 16": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1434,11 +1433,14 @@ "lsl x21, x21, #16", "orr x26, x21, x20", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "shld ax, bx, 31": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1447,7 +1449,10 @@ "lsr w20, w20, #17", "orr x26, x21, x20", "cmn wzr, w26, lsl #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "shld eax, ebx, 0": { @@ -1458,57 +1463,61 @@ ] }, "shld eax, ebx, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr w26, w4, w7, #31", - "tst w26, w26", - "ubfx x20, x4, #31, #1", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x80000000", + "ubfx x20, x20, #31, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w26, w4", - "ubfx x21, x21, #31, #1", - "orr w20, w20, w21, lsl #28", + "bfi w21, w20, #29, #1", + "eor w20, w26, w4", + "ubfx x20, x20, #31, #1", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20", "mov x4, x26" ] }, "shld eax, ebx, 15": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr w26, w4, w7, #17", - "tst w26, w26", - "ubfx x20, x4, #17, #1", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x20000", + "ubfx x20, x20, #17, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "shld eax, ebx, 16": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr w26, w4, w7, #16", - "tst w26, w26", - "ubfx x20, x4, #16, #1", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x10000", + "ubfx x20, x20, #16, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "shld eax, ebx, 31": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr w26, w4, w7, #1", - "tst w26, w26", - "ubfx x20, x4, #1, #1", + "cmp w26, #0x0 (0)", + "eor x20, x4, #0x2", + "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, @@ -1518,62 +1527,66 @@ "ExpectedArm64ASM": [] }, "shld rax, rbx, 1": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr x26, x4, x7, #63", - "tst x26, x26", - "lsr x20, x4, #63", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x8000000000000000", + "lsr x20, x20, #63", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor x21, x26, x4", - "lsr x21, x21, #63", - "orr w20, w20, w21, lsl #28", + "bfi w21, w20, #29, #1", + "eor x20, x26, x4", + "lsr x20, x20, #63", + "orr w20, w21, w20, lsl #28", "msr nzcv, x20", "mov x4, x26" ] }, "shld rax, rbx, 15": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr x26, x4, x7, #49", - "tst x26, x26", - "ubfx x20, x4, #49, #1", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x2000000000000", + "ubfx x20, x20, #49, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "shld rax, rbx, 32": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr x26, x4, x7, #32", - "tst x26, x26", - "ubfx x20, x4, #32, #1", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x100000000", + "ubfx x20, x20, #32, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "shld rax, rbx, 63": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xac", "ExpectedArm64ASM": [ "extr x26, x4, x7, #1", - "tst x26, x26", - "ubfx x20, x4, #1, #1", + "cmp x26, #0x0 (0)", + "eor x20, x4, #0x2", + "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "mov x4, x26" ] }, "shld ax, bx, cl": { - "ExpectedInstructionCount": 24, + "ExpectedInstructionCount": 25, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1589,12 +1602,13 @@ "csel x20, x21, x20, eq", "msr nzcv, x23", "and w0, w22, #0x1f", - "cbz w0, #+0x28", + "cbz w0, #+0x2c", "cmn wzr, w20, lsl #16", "mov x26, x20", + "mvn x0, x20", "eor w2, w21, w20", "mrs x1, nzcv", - "lsr x0, x20, #16", + "lsr x0, x0, #16", "bfi w1, w0, #29, #1", "lsr w2, w2, #15", "bfi w1, w2, #28, #1", @@ -1603,7 +1617,7 @@ ] }, "shld eax, ebx, cl": { - "ExpectedInstructionCount": 23, + "ExpectedInstructionCount": 24, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "mov w20, w7", @@ -1618,10 +1632,11 @@ "csel x20, x21, x20, eq", "msr nzcv, x23", "and w0, w22, #0x1f", - "cbz w0, #+0x28", + "cbz w0, #+0x2c", "ands w26, w20, w20", "neg w0, w22", "lsr w0, w21, w0", + "mvn x0, x0", "eor w2, w21, w20", "mrs x1, nzcv", "bfi w1, w0, #29, #1", @@ -1632,7 +1647,7 @@ ] }, "shld rax, rbx, cl": { - "ExpectedInstructionCount": 21, + "ExpectedInstructionCount": 22, "Comment": "0x0f 0xad", "ExpectedArm64ASM": [ "and x20, x5, #0x3f", @@ -1645,10 +1660,11 @@ "csel x21, x4, x21, eq", "msr nzcv, x22", "and w0, w20, #0x3f", - "cbz x0, #+0x28", + "cbz x0, #+0x2c", "ands x26, x21, x21", "neg x0, x20", "lsr x0, x4, x0", + "mvn x0, x0", "eor x2, x4, x21", "mrs x1, nzcv", "bfi w1, w0, #29, #1", @@ -1680,11 +1696,12 @@ ] }, "bts ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "and x20, x7, #0xf", "lsr w21, w4, w20", + "eor x21, x21, #0x1", "ubfx x21, x21, #0, #1", "lsl x21, x21, #29", "mov w22, #0x1", @@ -1695,7 +1712,7 @@ ] }, "bts [rax], bx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1706,16 +1723,18 @@ "orr x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bts eax, ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "lsr w20, w4, w7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "mov w21, #0x1", @@ -1725,7 +1744,7 @@ ] }, "bts [rax], ebx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1736,16 +1755,18 @@ "orr x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bts rax, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "lsr x20, x4, x7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "mov w21, #0x1", @@ -1755,7 +1776,7 @@ ] }, "bts [rax], rbx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1766,13 +1787,14 @@ "orr x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock bts [rax], bx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1782,13 +1804,14 @@ "add x21, x4, x21", "ldsetalb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock bts [rax], ebx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1798,13 +1821,14 @@ "add x21, x4, x21", "ldsetalb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock bts [rax], rbx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -1814,6 +1838,7 @@ "add x21, x4, x21", "ldsetalb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" @@ -1830,7 +1855,7 @@ "bfxil x4, x20, #0, #16", "sbfx x20, x20, #15, #1", "cmp x21, x20", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul eax, ebx": { @@ -1842,7 +1867,7 @@ "mul w4, w4, w7", "sbfx x21, x4, #31, #1", "cmp x20, x21", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "imul rax, rbx": { @@ -1853,11 +1878,11 @@ "mul x4, x4, x7", "asr x21, x4, #63", "cmp x20, x21", - "ccmn xzr, #0, #nzCV, eq" + "ccmp xzr, #0, #nzcV, eq" ] }, "cmpxchg al, bl": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xb0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -1867,14 +1892,11 @@ "lsl w0, w22, #24", "cmp w0, w21, lsl #24", "sub w26, w22, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "bfxil x4, x20, #0, #8" ] }, "cmpxchg [rax], bl": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -1886,14 +1908,11 @@ "lsl w0, w21, #24", "cmp w0, w20, lsl #24", "sub w26, w21, w20", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "bfxil x4, x20, #0, #8" ] }, "cmpxchg ax, bx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1903,14 +1922,11 @@ "lsl w0, w22, #16", "cmp w0, w21, lsl #16", "sub w26, w22, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "bfxil x4, x20, #0, #16" ] }, "cmpxchg [rax], bx": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -1922,14 +1938,11 @@ "lsl w0, w21, #16", "cmp w0, w20, lsl #16", "sub w26, w21, w20", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "bfxil x4, x20, #0, #16" ] }, "cmpxchg eax, ebx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", @@ -1937,14 +1950,11 @@ "mov w22, w4", "eor w27, w22, w21", "subs w26, w22, w21", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "mov x4, x20" ] }, "cmpxchg [rax], ebx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w20, w7", @@ -1955,26 +1965,20 @@ "cmp w20, w21", "csel x4, x4, x20, eq", "eor w27, w21, w20", - "subs w26, w21, w20", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20" + "subs w26, w21, w20" ] }, "cmpxchg rax, rbx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 3, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov w27, #0x0", "subs x26, x4, x4", - "mrs x20, nzcv", - "eor w20, w20, #0x20000000", - "msr nzcv, x20", "mov x4, x7" ] }, "cmpxchg [rax], rbx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xb1", "ExpectedArm64ASM": [ "mov x1, x4", @@ -1982,18 +1986,16 @@ "mov x20, x1", "eor w27, w4, w20", "subs x26, x4, x20", - "mrs x21, nzcv", - "eor w21, w21, #0x20000000", - "msr nzcv, x21", "mov x4, x20" ] }, "btr ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "and x20, x7, #0xf", "lsr w21, w4, w20", + "eor x21, x21, #0x1", "ubfx x21, x21, #0, #1", "lsl x21, x21, #29", "mov w22, #0x1", @@ -2004,7 +2006,7 @@ ] }, "btr [rax], bx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2015,16 +2017,18 @@ "bic x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btr eax, ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "lsr w20, w4, w7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "mov w21, #0x1", @@ -2034,7 +2038,7 @@ ] }, "btr [rax], ebx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2045,16 +2049,18 @@ "bic x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btr rax, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "lsr x20, x4, x7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "mov w21, #0x1", @@ -2064,7 +2070,7 @@ ] }, "btr [rax], rbx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2075,6 +2081,7 @@ "bic x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" @@ -2089,7 +2096,7 @@ ] }, "lock btr [rax], bx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2099,13 +2106,14 @@ "add x21, x4, x21", "ldclralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btr [rax], ebx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2115,13 +2123,14 @@ "add x21, x4, x21", "ldclralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btr [rax], rbx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2131,6 +2140,7 @@ "add x21, x4, x21", "ldclralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" @@ -2201,11 +2211,12 @@ ] }, "btc ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "and x20, x7, #0xf", "lsr w21, w4, w20", + "eor x21, x21, #0x1", "ubfx x21, x21, #0, #1", "lsl x21, x21, #29", "mov w22, #0x1", @@ -2216,7 +2227,7 @@ ] }, "btc [rax], bx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2227,16 +2238,18 @@ "eor x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btc eax, ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "lsr w20, w4, w7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "mov w21, #0x1", @@ -2246,7 +2259,7 @@ ] }, "btc [rax], ebx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2257,16 +2270,18 @@ "eor x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btc rax, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "lsr x20, x4, x7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "mov w21, #0x1", @@ -2276,7 +2291,7 @@ ] }, "btc [rax], rbx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2287,13 +2302,14 @@ "eor x22, x23, x22", "strb w22, [x4, x21, sxtx]", "lsr w20, w23, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btc [rax], bx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2303,13 +2319,14 @@ "add x21, x4, x21", "ldeoralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btc [rax], ebx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2319,13 +2336,14 @@ "add x21, x4, x21", "ldeoralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btc [rax], rbx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x7, #0, #3", @@ -2335,13 +2353,14 @@ "add x21, x4, x21", "ldeoralb w22, w21, [x21]", "lsr w20, w21, w20", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bsf ax, bx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xbc", "ExpectedArm64ASM": [ "uxth w20, w4", @@ -2353,7 +2372,10 @@ "csinv w22, w22, wzr, ne", "cmn wzr, w21, lsl #16", "csel x20, x20, x22, eq", - "bfxil x4, x20, #0, #16" + "bfxil x4, x20, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "bsf eax, ebx": { @@ -2366,7 +2388,7 @@ "rbit w0, w0", "clz w21, w0", "csinv w21, w21, wzr, ne", - "tst w20, w20", + "cmp w20, #0x0 (0)", "csel x4, x4, x21, eq" ] }, @@ -2378,12 +2400,12 @@ "cmp x7, #0x0 (0)", "clz x20, x0", "csinv x20, x20, xzr, ne", - "tst x7, x7", + "cmp x7, #0x0 (0)", "csel x4, x4, x20, eq" ] }, "bsr ax, bx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xbd", "ExpectedArm64ASM": [ "uxth w20, w4", @@ -2395,7 +2417,10 @@ "sub x22, x0, x22", "cmn wzr, w21, lsl #16", "csel x20, x20, x22, eq", - "bfxil x4, x20, #0, #16" + "bfxil x4, x20, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "bsr eax, ebx": { @@ -2406,7 +2431,7 @@ "mov x0, #0x1f", "clz w21, w20", "sub x21, x0, x21", - "tst w20, w20", + "cmp w20, #0x0 (0)", "csel x4, x4, x21, eq" ] }, @@ -2417,7 +2442,7 @@ "mov x0, #0x3f", "clz x20, x7", "sub x20, x0, x20", - "tst x7, x7", + "cmp x7, #0x0 (0)", "csel x4, x4, x20, eq" ] }, @@ -2499,7 +2524,7 @@ ] }, "xadd al, bl": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w4", @@ -2509,11 +2534,14 @@ "cmn w0, w21, lsl #24", "add w26, w20, w21", "bfxil x7, x20, #0, #8", - "bfxil x4, x26, #0, #8" + "bfxil x4, x26, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xadd [rax], bl": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xc0", "ExpectedArm64ASM": [ "uxtb w20, w7", @@ -2522,11 +2550,14 @@ "lsl w0, w21, #24", "cmn w0, w20, lsl #24", "add w26, w21, w20", - "bfxil x7, x21, #0, #8" + "bfxil x7, x21, #0, #8", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xadd ax, bx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 11, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w4", @@ -2536,11 +2567,14 @@ "cmn w0, w21, lsl #16", "add w26, w20, w21", "bfxil x7, x20, #0, #16", - "bfxil x4, x26, #0, #16" + "bfxil x4, x26, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xadd [rax], bx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 10, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "uxth w20, w7", @@ -2549,48 +2583,63 @@ "lsl w0, w21, #16", "cmn w0, w20, lsl #16", "add w26, w21, w20", - "bfxil x7, x21, #0, #16" + "bfxil x7, x21, #0, #16", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xadd eax, ebx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w4", "mov w21, w7", "eor w27, w20, w21", "adds w26, w20, w21", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "mov x7, x20", "mov x4, x26" ] }, "xadd [rax], ebx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "mov w20, w7", "ldaddal w20, w7, [x4]", "eor w27, w7, w20", - "adds w26, w7, w20" + "adds w26, w7, w20", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20" ] }, "xadd rax, rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "eor w27, w4, w7", "adds x26, x4, x7", + "mrs x20, nzcv", + "eor w20, w20, #0x20000000", + "msr nzcv, x20", "mov x7, x4", "mov x4, x26" ] }, "xadd [rax], rbx": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 7, "Comment": "0x0f 0xc1", "ExpectedArm64ASM": [ "ldaddal x7, x20, [x4]", "eor w27, w20, w7", "adds x26, x20, x7", + "mrs x21, nzcv", + "eor w21, w21, #0x20000000", + "msr nzcv, x21", "mov x7, x20" ] }, diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index e43ec9ef6..e63a4785d 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -24,127 +24,140 @@ ] }, "bt ax, 0": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt eax, 0": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt rax, 0": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt ax, 15": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "ubfx x20, x4, #15, #1", + "eor x20, x4, #0x8000", + "ubfx x20, x20, #15, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt eax, 31": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "ubfx x20, x4, #31, #1", + "eor x20, x4, #0x80000000", + "ubfx x20, x20, #31, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt rax, 63": { - "ExpectedInstructionCount": 3, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "lsr x20, x4, #63", + "eor x20, x4, #0x8000000000000000", + "lsr x20, x20, #63", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt word [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt dword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt qword [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt word [rax], 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt dword [rax], 31": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bt qword [rax], 63": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bts ax, 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "orr w21, w4, #0x1", "bfxil x4, x21, #0, #16", @@ -152,30 +165,33 @@ ] }, "bts eax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "orr w4, w4, #0x1", "msr nzcv, x20" ] }, "bts rax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "orr x4, x4, #0x1", "msr nzcv, x20" ] }, "bts ax, 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "ubfx x20, x4, #15, #1", + "eor x20, x4, #0x8000", + "ubfx x20, x20, #15, #1", "lsl x20, x20, #29", "orr w21, w4, #0x8000", "bfxil x4, x21, #0, #16", @@ -183,180 +199,195 @@ ] }, "bts eax, 31": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "ubfx x20, x4, #31, #1", + "eor x20, x4, #0x80000000", + "ubfx x20, x20, #31, #1", "lsl x20, x20, #29", "orr w4, w4, #0x80000000", "msr nzcv, x20" ] }, "bts rax, 63": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "lsr x20, x4, #63", + "eor x20, x4, #0x8000000000000000", + "lsr x20, x20, #63", "lsl x20, x20, #29", "orr x4, x4, #0x8000000000000000", "msr nzcv, x20" ] }, "bts word [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "orr x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bts dword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "orr x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bts qword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "orr x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bts word [rax], 15": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", "orr x21, x20, #0x80", "strb w21, [x4, #1]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bts dword [rax], 31": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", "orr x21, x20, #0x80", "strb w21, [x4, #3]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "bts qword [rax], 63": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", "orr x21, x20, #0x80", "strb w21, [x4, #7]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock bts word [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldsetalb w20, w20, [x21]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock bts dword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldsetalb w20, w20, [x21]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock bts qword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldsetalb w20, w20, [x21]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock bts word [rax], 15": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x1 (1)", "ldsetalb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock bts dword [rax], 31": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x3 (3)", "ldsetalb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock bts qword [rax], 63": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x7 (7)", "ldsetalb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btr ax, 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "and w21, w4, #0xfffffffe", "bfxil x4, x21, #0, #16", @@ -364,30 +395,33 @@ ] }, "btr eax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "and w4, w4, #0xfffffffe", "msr nzcv, x20" ] }, "btr rax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "and x4, x4, #0xfffffffffffffffe", "msr nzcv, x20" ] }, "btr ax, 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "ubfx x20, x4, #15, #1", + "eor x20, x4, #0x8000", + "ubfx x20, x20, #15, #1", "lsl x20, x20, #29", "and w21, w4, #0xffff7fff", "bfxil x4, x21, #0, #16", @@ -395,180 +429,195 @@ ] }, "btr eax, 31": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "ubfx x20, x4, #31, #1", + "eor x20, x4, #0x80000000", + "ubfx x20, x20, #31, #1", "lsl x20, x20, #29", "and w4, w4, #0x7fffffff", "msr nzcv, x20" ] }, "btr rax, 63": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "lsr x20, x4, #63", + "eor x20, x4, #0x8000000000000000", + "lsr x20, x20, #63", "lsl x20, x20, #29", "and x4, x4, #0x7fffffffffffffff", "msr nzcv, x20" ] }, "btr word [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "and x21, x20, #0xfffffffffffffffe", "strb w21, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btr dword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "and x21, x20, #0xfffffffffffffffe", "strb w21, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btr qword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "and x21, x20, #0xfffffffffffffffe", "strb w21, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btr word [rax], 15": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", "and x21, x20, #0xffffffffffffff7f", "strb w21, [x4, #1]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btr dword [rax], 31": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", "and x21, x20, #0xffffffffffffff7f", "strb w21, [x4, #3]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btr qword [rax], 63": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", "and x21, x20, #0xffffffffffffff7f", "strb w21, [x4, #7]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btr word [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldclralb w20, w20, [x21]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btr dword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldclralb w20, w20, [x21]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btr qword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldclralb w20, w20, [x21]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btr word [rax], 15": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x1 (1)", "ldclralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btr dword [rax], 31": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x3 (3)", "ldclralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btr qword [rax], 63": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x7 (7)", "ldclralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btc ax, 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "eor w21, w4, #0x1", "bfxil x4, x21, #0, #16", @@ -576,30 +625,33 @@ ] }, "btc eax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "eor w4, w4, #0x1", "msr nzcv, x20" ] }, "btc rax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "ubfx x20, x4, #0, #1", + "eor x20, x4, #0x1", + "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "eor x4, x4, #0x1", "msr nzcv, x20" ] }, "btc ax, 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "ubfx x20, x4, #15, #1", + "eor x20, x4, #0x8000", + "ubfx x20, x20, #15, #1", "lsl x20, x20, #29", "eor w21, w4, #0x8000", "bfxil x4, x21, #0, #16", @@ -607,170 +659,184 @@ ] }, "btc eax, 31": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "ubfx x20, x4, #31, #1", + "eor x20, x4, #0x80000000", + "ubfx x20, x20, #31, #1", "lsl x20, x20, #29", "eor w4, w4, #0x80000000", "msr nzcv, x20" ] }, "btc rax, 63": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 5, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ - "lsr x20, x4, #63", + "eor x20, x4, #0x8000000000000000", + "lsr x20, x20, #63", "lsl x20, x20, #29", "eor x4, x4, #0x8000000000000000", "msr nzcv, x20" ] }, "btc word [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "eor x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btc dword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "eor x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btc qword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "eor x21, x20, #0x1", "strb w21, [x4]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btc word [rax], 15": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", "eor x21, x20, #0x80", "strb w21, [x4, #1]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btc dword [rax], 31": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", "eor x21, x20, #0x80", "strb w21, [x4, #3]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "btc qword [rax], 63": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", "eor x21, x20, #0x80", "strb w21, [x4, #7]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btc word [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldeoralb w20, w20, [x21]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btc dword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldeoralb w20, w20, [x21]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btc qword [rax], 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", "add x21, x4, #0x0 (0)", "ldeoralb w20, w20, [x21]", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btc word [rax], 15": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x1 (1)", "ldeoralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btc dword [rax], 31": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x3 (3)", "ldeoralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" ] }, "lock btc qword [rax], 63": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", "add x21, x4, #0x7 (7)", "ldeoralb w20, w20, [x21]", "lsr w20, w20, #7", + "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "lsl x20, x20, #29", "msr nzcv, x20" @@ -831,86 +897,78 @@ ] }, "rdrand ax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", - "cset x21, ne", - "mov x22, x21", "bfxil x4, x20, #0, #16", - "mov w27, #0x0", "mov w26, #0x1", - "lsl x20, x22, #29", + "mov w27, #0x0", + "cset w20, eq", + "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdrand eax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", - "cset x21, ne", - "mov x22, x21", "mov w4, w20", - "mov w27, #0x0", "mov w26, #0x1", - "lsl x20, x22, #29", + "mov w27, #0x0", + "cset w20, eq", + "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdrand rax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ - "mrs x20, rndr", - "cset x21, ne", - "mov x22, x21", - "mov x4, x20", - "mov w27, #0x0", + "mrs x4, rndr", "mov w26, #0x1", - "lsl x20, x22, #29", + "mov w27, #0x0", + "cset w20, eq", + "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdseed ax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", - "cset x21, ne", - "mov x22, x21", "bfxil x4, x20, #0, #16", - "mov w27, #0x0", "mov w26, #0x1", - "lsl x20, x22, #29", + "mov w27, #0x0", + "cset w20, eq", + "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdseed eax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 7, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", - "cset x21, ne", - "mov x22, x21", "mov w4, w20", - "mov w27, #0x0", "mov w26, #0x1", - "lsl x20, x22, #29", + "mov w27, #0x0", + "cset w20, eq", + "lsl x20, x20, #29", "msr nzcv, x20" ] }, "rdseed rax": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ - "mrs x20, rndrrs", - "cset x21, ne", - "mov x22, x21", - "mov x4, x20", - "mov w27, #0x0", + "mrs x4, rndrrs", "mov w26, #0x1", - "lsl x20, x22, #29", + "mov w27, #0x0", + "cset w20, eq", + "lsl x20, x20, #29", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 611c624b9..1dfa6b736 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -148,13 +148,13 @@ "fcmp d16, d17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -165,13 +165,13 @@ "fcmp d16, d17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 4d5770f24..38502a707 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -409,9 +409,9 @@ "addp v0.8b, v0.8b, v0.8b", "umov w20, v0.b[0]", "bfxil x4, x20, #0, #16", - "tst w20, w20", - "mov w26, #0x1", - "mov w27, #0x0" + "mov w27, #0x0", + "cmp w20, #0x0 (0)", + "mov w26, #0x1" ] }, "popcnt eax, ebx": { @@ -422,9 +422,9 @@ "cnt v0.8b, v0.8b", "addv b0, v0.8b", "umov w4, v0.b[0]", - "tst w4, w4", - "mov w26, #0x1", - "mov w27, #0x0" + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "mov w26, #0x1" ] }, "popcnt rax, rbx": { @@ -435,13 +435,13 @@ "cnt v0.8b, v0.8b", "addv b0, v0.8b", "umov w4, v0.b[0]", - "tst w4, w4", - "mov w26, #0x1", - "mov w27, #0x0" + "mov w27, #0x0", + "cmp w4, #0x0 (0)", + "mov w26, #0x1" ] }, "tzcnt ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0xf3 0x0f 0xbc", "ExpectedArm64ASM": [ "rbit w20, w7", @@ -449,6 +449,7 @@ "clz w20, w20", "bfxil x4, x20, #0, #16", "cmn wzr, w20, lsl #16", + "eor x20, x20, #0x10", "ubfx x20, x20, #4, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -456,33 +457,35 @@ ] }, "tzcnt eax, ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0xf3 0x0f 0xbc", "ExpectedArm64ASM": [ "rbit w4, w7", "clz w4, w4", - "tst w4, w4", - "ubfx x20, x4, #5, #1", + "cmp w4, #0x0 (0)", + "eor x20, x4, #0x20", + "ubfx x20, x20, #5, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "tzcnt rax, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "0xf3 0x0f 0xbc", "ExpectedArm64ASM": [ "rbit x4, x7", "clz x4, x4", - "tst x4, x4", - "ubfx x20, x4, #6, #1", + "cmp x4, #0x0 (0)", + "eor x20, x4, #0x40", + "ubfx x20, x20, #6, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lzcnt ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 10, "Comment": "0xf3 0x0f 0xbd", "ExpectedArm64ASM": [ "lsl w20, w7, #16", @@ -490,6 +493,7 @@ "clz w20, w20", "bfxil x4, x20, #0, #16", "cmn wzr, w20, lsl #16", + "eor x20, x20, #0x10", "ubfx x20, x20, #4, #1", "mrs x21, nzcv", "orr w20, w21, w20, lsl #29", @@ -497,27 +501,29 @@ ] }, "lzcnt eax, ebx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "0xf3 0x0f 0xbd", "ExpectedArm64ASM": [ "clz w4, w7", - "tst w4, w4", - "ubfx x20, x4, #5, #1", + "cmp w4, #0x0 (0)", + "eor x20, x4, #0x20", + "ubfx x20, x20, #5, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lzcnt rax, rbx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "0xf3 0x0f 0xbd", "ExpectedArm64ASM": [ "clz x4, x7", - "tst x4, x4", - "ubfx x20, x4, #6, #1", + "cmp x4, #0x0 (0)", + "eor x20, x4, #0x40", + "ubfx x20, x20, #6, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "cmpss xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 504802124..ca8435dce 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -3361,13 +3361,13 @@ "fcmp s16, s17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -3380,13 +3380,13 @@ "fcmp d16, d17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -3399,13 +3399,13 @@ "fcmp s16, s17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -3418,13 +3418,13 @@ "fcmp d16, d17", "mov w27, #0x0", "cset w20, eq", - "cset w21, lo", + "cset w21, hs", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 2564150c5..9207d21c0 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -519,10 +519,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -545,10 +545,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -571,10 +571,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -597,10 +597,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -677,10 +677,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -699,10 +699,10 @@ "mov w27, #0x0", "mov w26, #0x1", "cmp x21, #0x0 (0)", - "cset x21, eq", - "tst w20, w20", + "cset x21, ne", + "cmp w20, #0x0 (0)", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "msr nzcv, x20" ] }, @@ -4901,7 +4901,7 @@ ], "ExpectedArm64ASM": [ "bic w26, w5, w7", - "tst w26, w26", + "cmp w26, #0x0 (0)", "mov x4, x26" ] }, @@ -4912,7 +4912,7 @@ ], "ExpectedArm64ASM": [ "bic x26, x5, x7", - "tst x26, x26", + "cmp x26, #0x0 (0)", "mov x4, x26" ] }, @@ -4927,11 +4927,11 @@ "bic w20, w7, w20", "tst x5, #0xe0", "csel w4, w7, w20, ne", - "cset w20, ne", - "tst w4, w4", + "cset w20, eq", + "cmp w4, #0x0 (0)", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bzhi rax, rbx, rcx": { @@ -4945,11 +4945,11 @@ "bic x20, x7, x20", "tst x5, #0xc0", "csel x4, x7, x20, ne", - "cset w20, ne", - "tst x4, x4", + "cset w20, eq", + "cmp x4, #0x0 (0)", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "pext eax, ebx, ecx": { @@ -5125,7 +5125,7 @@ "bic w22, w20, w22", "cmp w21, #0x1f (31)", "csel w4, w22, w20, ls", - "tst w4, w4" + "cmp w4, #0x0 (0)" ] }, "bextr rax, rbx, rcx": { @@ -5145,7 +5145,7 @@ "bic x22, x20, x22", "cmp x21, #0x3f (63)", "csel x4, x22, x20, ls", - "tst x4, x4" + "cmp x4, #0x0 (0)" ] }, "shlx eax, ebx, ecx": { diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json index e2dcf5879..73e3e0ab8 100644 --- a/unittests/InstructionCountCI/VEX_map_group.json +++ b/unittests/InstructionCountCI/VEX_map_group.json @@ -616,11 +616,11 @@ "sub w20, w7, #0x1 (1)", "and w4, w20, w7", "cmp x7, #0x0 (0)", - "cset x20, eq", - "tst w4, w4", + "cset x20, ne", + "cmp w4, #0x0 (0)", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "blsr rax, rbx": { @@ -632,11 +632,11 @@ "sub x20, x7, #0x1 (1)", "and x4, x20, x7", "cmp x7, #0x0 (0)", - "cset x20, eq", - "tst x4, x4", + "cset x20, ne", + "cmp x4, #0x0 (0)", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "blsmsk eax, ebx": { @@ -648,11 +648,11 @@ "sub w20, w7, #0x1 (1)", "eor w4, w20, w7", "cmp x7, #0x0 (0)", - "cset x20, eq", - "tst w4, w4", + "cset x20, ne", + "cmp w4, #0x0 (0)", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "blsmsk rax, rbx": { @@ -664,11 +664,11 @@ "sub x20, x7, #0x1 (1)", "eor x4, x20, x7", "cmp x7, #0x0 (0)", - "cset x20, eq", - "tst x4, x4", + "cset x20, ne", + "cmp x4, #0x0 (0)", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "blsi eax, ebx": { @@ -679,11 +679,11 @@ "ExpectedArm64ASM": [ "neg w20, w7", "and w4, w7, w20", - "tst w4, w4", - "cset w20, ne", + "cmp w4, #0x0 (0)", + "cset w20, eq", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "blsi rax, rbx": { @@ -694,11 +694,11 @@ "ExpectedArm64ASM": [ "neg x20, x7", "and x4, x7, x20", - "tst x4, x4", - "cset w20, ne", + "cmp x4, #0x0 (0)", + "cset w20, eq", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] } } diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index eb4bf7c9b..8ce1155c8 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -5964,7 +5964,7 @@ "0xda 11b 0xc0 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -5982,7 +5982,7 @@ "0xda 11b 0xc1 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -6002,7 +6002,7 @@ "0xda 11b 0xc2 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -6022,7 +6022,7 @@ "0xda 11b 0xc3 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -6042,7 +6042,7 @@ "0xda 11b 0xc4 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -6062,7 +6062,7 @@ "0xda 11b 0xc5 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -6082,7 +6082,7 @@ "0xda 11b 0xc6 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -6102,7 +6102,7 @@ "0xda 11b 0xc7 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -6275,14 +6275,12 @@ ] }, "fcmovbe st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xd0 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -6295,14 +6293,12 @@ ] }, "fcmovbe st0, st1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd1 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -6317,14 +6313,12 @@ ] }, "fcmovbe st0, st2": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd2 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -6339,14 +6333,12 @@ ] }, "fcmovbe st0, st3": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd3 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -6361,14 +6353,12 @@ ] }, "fcmovbe st0, st4": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd4 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -6383,14 +6373,12 @@ ] }, "fcmovbe st0, st5": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd5 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -6405,14 +6393,12 @@ ] }, "fcmovbe st0, st6": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd6 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -6427,14 +6413,12 @@ ] }, "fcmovbe st0, st7": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd7 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -6942,7 +6926,7 @@ "0xdb 11b 0xc0 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -6960,7 +6944,7 @@ "0xdb 11b 0xc1 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -6980,7 +6964,7 @@ "0xdb 11b 0xc2 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -7000,7 +6984,7 @@ "0xdb 11b 0xc3 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -7020,7 +7004,7 @@ "0xdb 11b 0xc4 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -7040,7 +7024,7 @@ "0xdb 11b 0xc5 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -7060,7 +7044,7 @@ "0xdb 11b 0xc6 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -7080,7 +7064,7 @@ "0xdb 11b 0xc7 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -7253,13 +7237,12 @@ ] }, "fcmovnbe st0, st0": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xd0 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -7272,13 +7255,12 @@ ] }, "fcmovnbe st0, st1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd1 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -7293,13 +7275,12 @@ ] }, "fcmovnbe st0, st2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd2 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -7314,13 +7295,12 @@ ] }, "fcmovnbe st0, st3": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd3 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -7335,13 +7315,12 @@ ] }, "fcmovnbe st0, st4": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd4 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -7356,13 +7335,12 @@ ] }, "fcmovnbe st0, st5": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd5 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -7377,13 +7355,12 @@ ] }, "fcmovnbe st0, st6": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd6 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -7398,13 +7375,12 @@ ] }, "fcmovnbe st0, st7": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd7 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -7648,7 +7624,7 @@ ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 42, + "ExpectedInstructionCount": 43, "Comment": [ "0xdb 11b 0xe8 /5" ], @@ -7691,6 +7667,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -7698,7 +7675,7 @@ ] }, "fucomi st0, st1": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xe9 /5" ], @@ -7743,6 +7720,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -7750,7 +7728,7 @@ ] }, "fucomi st0, st2": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xea /5" ], @@ -7795,6 +7773,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -7802,7 +7781,7 @@ ] }, "fucomi st0, st3": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xeb /5" ], @@ -7847,6 +7826,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -7854,7 +7834,7 @@ ] }, "fucomi st0, st4": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xec /5" ], @@ -7899,6 +7879,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -7906,7 +7887,7 @@ ] }, "fucomi st0, st5": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xed /5" ], @@ -7951,6 +7932,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -7958,7 +7940,7 @@ ] }, "fucomi st0, st6": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xee /5" ], @@ -8003,6 +7985,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -8010,7 +7993,7 @@ ] }, "fucomi st0, st7": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xef /5" ], @@ -8055,6 +8038,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -8062,7 +8046,7 @@ ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 42, + "ExpectedInstructionCount": 43, "Comment": [ "0xdb 11b 0xf0 /6" ], @@ -8105,6 +8089,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -8112,7 +8097,7 @@ ] }, "fcomi st0, st1": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xf1 /6" ], @@ -8157,6 +8142,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -8164,7 +8150,7 @@ ] }, "fcomi st0, st2": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xf2 /6" ], @@ -8209,6 +8195,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -8216,7 +8203,7 @@ ] }, "fcomi st0, st3": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xf3 /6" ], @@ -8261,6 +8248,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -8268,7 +8256,7 @@ ] }, "fcomi st0, st4": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xf4 /6" ], @@ -8313,6 +8301,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -8320,7 +8309,7 @@ ] }, "fcomi st0, st5": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xf5 /6" ], @@ -8365,6 +8354,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -8372,7 +8362,7 @@ ] }, "fcomi st0, st6": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xf6 /6" ], @@ -8417,6 +8407,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -8424,7 +8415,7 @@ ] }, "fcomi st0, st7": { - "ExpectedInstructionCount": 44, + "ExpectedInstructionCount": 45, "Comment": [ "0xdb 11b 0xf7 /6" ], @@ -8469,6 +8460,7 @@ "ubfx x20, x20, #2, #1", "orr w21, w21, w20", "orr w22, w22, w20", + "eor x21, x21, #0x1", "lsl x21, x21, #29", "orr w21, w21, w22, lsl #30", "eor w26, w20, #0x1", @@ -16787,7 +16779,7 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 50, + "ExpectedInstructionCount": 51, "Comment": [ "0xdf 11b 0xe8 /5" ], @@ -16830,6 +16822,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -16845,7 +16838,7 @@ ] }, "fucomip st1": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xe9 /5" ], @@ -16891,6 +16884,7 @@ "ubfx x22, x22, #2, #1", "orr w23, w23, w22", "orr w24, w24, w22", + "eor x23, x23, #0x1", "lsl x23, x23, #29", "orr w23, w23, w24, lsl #30", "eor w26, w22, #0x1", @@ -16905,7 +16899,7 @@ ] }, "fucomip st2": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xea /5" ], @@ -16950,6 +16944,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -16965,7 +16960,7 @@ ] }, "fucomip st3": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xeb /5" ], @@ -17010,6 +17005,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17025,7 +17021,7 @@ ] }, "fucomip st4": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xec /5" ], @@ -17070,6 +17066,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17085,7 +17082,7 @@ ] }, "fucomip st5": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xed /5" ], @@ -17130,6 +17127,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17145,7 +17143,7 @@ ] }, "fucomip st6": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xee /5" ], @@ -17190,6 +17188,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17205,7 +17204,7 @@ ] }, "fucomip st7": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xef /5" ], @@ -17250,6 +17249,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17265,7 +17265,7 @@ ] }, "fcomip st0": { - "ExpectedInstructionCount": 50, + "ExpectedInstructionCount": 51, "Comment": [ "0xdf 11b 0xf0 /6" ], @@ -17308,6 +17308,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17323,7 +17324,7 @@ ] }, "fcomip st1": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xf1 /6" ], @@ -17369,6 +17370,7 @@ "ubfx x22, x22, #2, #1", "orr w23, w23, w22", "orr w24, w24, w22", + "eor x23, x23, #0x1", "lsl x23, x23, #29", "orr w23, w23, w24, lsl #30", "eor w26, w22, #0x1", @@ -17383,7 +17385,7 @@ ] }, "fcomip st2": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xf2 /6" ], @@ -17428,6 +17430,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17443,7 +17446,7 @@ ] }, "fcomip st3": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xf3 /6" ], @@ -17488,6 +17491,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17503,7 +17507,7 @@ ] }, "fcomip st4": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xf4 /6" ], @@ -17548,6 +17552,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17563,7 +17568,7 @@ ] }, "fcomip st5": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xf5 /6" ], @@ -17608,6 +17613,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17623,7 +17629,7 @@ ] }, "fcomip st6": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xf6 /6" ], @@ -17668,6 +17674,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", @@ -17683,7 +17690,7 @@ ] }, "fcomip st7": { - "ExpectedInstructionCount": 52, + "ExpectedInstructionCount": 53, "Comment": [ "0xdf 11b 0xf7 /6" ], @@ -17728,6 +17735,7 @@ "ubfx x21, x21, #2, #1", "orr w22, w22, w21", "orr w23, w23, w21", + "eor x22, x22, #0x1", "lsl x22, x22, #29", "orr w22, w22, w23, lsl #30", "mov w23, #0x1", diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index 7aeaa94df..c9547a47f 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -3336,7 +3336,7 @@ "0xda 11b 0xc0 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -3354,7 +3354,7 @@ "0xda 11b 0xc1 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -3374,7 +3374,7 @@ "0xda 11b 0xc2 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -3394,7 +3394,7 @@ "0xda 11b 0xc3 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -3414,7 +3414,7 @@ "0xda 11b 0xc4 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -3434,7 +3434,7 @@ "0xda 11b 0xc5 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -3454,7 +3454,7 @@ "0xda 11b 0xc6 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -3474,7 +3474,7 @@ "0xda 11b 0xc7 /0" ], "ExpectedArm64ASM": [ - "csetm x20, hs", + "csetm x20, lo", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -3647,14 +3647,12 @@ ] }, "fcmovbe st0, st0": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 10, "Comment": [ "0xda 11b 0xd0 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -3667,14 +3665,12 @@ ] }, "fcmovbe st0, st1": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd1 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -3689,14 +3685,12 @@ ] }, "fcmovbe st0, st2": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd2 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -3711,14 +3705,12 @@ ] }, "fcmovbe st0, st3": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd3 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -3733,14 +3725,12 @@ ] }, "fcmovbe st0, st4": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd4 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -3755,14 +3745,12 @@ ] }, "fcmovbe st0, st5": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd5 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -3777,14 +3765,12 @@ ] }, "fcmovbe st0, st6": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd6 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -3799,14 +3785,12 @@ ] }, "fcmovbe st0, st7": { - "ExpectedInstructionCount": 14, + "ExpectedInstructionCount": 12, "Comment": [ "0xda 11b 0xd7 /0" ], "ExpectedArm64ASM": [ - "mov x20, #0xffffffffffffffff", - "csetm x21, hs", - "csel x20, x20, x21, eq", + "csetm x20, ls", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -4245,7 +4229,7 @@ "0xdb 11b 0xc0 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -4263,7 +4247,7 @@ "0xdb 11b 0xc1 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -4283,7 +4267,7 @@ "0xdb 11b 0xc2 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -4303,7 +4287,7 @@ "0xdb 11b 0xc3 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -4323,7 +4307,7 @@ "0xdb 11b 0xc4 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -4343,7 +4327,7 @@ "0xdb 11b 0xc5 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -4363,7 +4347,7 @@ "0xdb 11b 0xc6 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -4383,7 +4367,7 @@ "0xdb 11b 0xc7 /0" ], "ExpectedArm64ASM": [ - "csetm x20, lo", + "csetm x20, hs", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -4556,13 +4540,12 @@ ] }, "fcmovnbe st0, st0": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 10, "Comment": [ "0xdb 11b 0xd0 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -4575,13 +4558,12 @@ ] }, "fcmovnbe st0, st1": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd1 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x1 (1)", @@ -4596,13 +4578,12 @@ ] }, "fcmovnbe st0, st2": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd2 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x2 (2)", @@ -4617,13 +4598,12 @@ ] }, "fcmovnbe st0, st3": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd3 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x3 (3)", @@ -4638,13 +4618,12 @@ ] }, "fcmovnbe st0, st4": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd4 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x4 (4)", @@ -4659,13 +4638,12 @@ ] }, "fcmovnbe st0, st5": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd5 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x5 (5)", @@ -4680,13 +4658,12 @@ ] }, "fcmovnbe st0, st6": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd6 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x6 (6)", @@ -4701,13 +4678,12 @@ ] }, "fcmovnbe st0, st7": { - "ExpectedInstructionCount": 13, + "ExpectedInstructionCount": 12, "Comment": [ "0xdb 11b 0xd7 /2" ], "ExpectedArm64ASM": [ - "csetm x20, lo", - "csel x20, x20, xzr, ne", + "csetm x20, hi", "dup v2.2d, x20", "ldrb w20, [x28, #1019]", "add w21, w20, #0x7 (7)", @@ -4973,11 +4949,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -4998,11 +4974,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5023,11 +4999,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5048,11 +5024,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5073,11 +5049,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5098,11 +5074,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5123,11 +5099,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5148,11 +5124,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5171,11 +5147,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5196,11 +5172,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5221,11 +5197,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5246,11 +5222,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5271,11 +5247,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5296,11 +5272,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5321,11 +5297,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -5346,11 +5322,11 @@ "cset w20, eq", "cset w21, lo", "cset w22, vs", - "orr w21, w21, w22", + "cset w26, vc", + "and w21, w21, w26", "lsl x21, x21, #29", "orr w20, w20, w22", "orr w20, w21, w20, lsl #30", - "eor w26, w22, #0x1", "msr nzcv, x20" ] }, @@ -9863,11 +9839,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -9896,11 +9872,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -9929,11 +9905,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -9962,11 +9938,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -9995,11 +9971,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10028,11 +10004,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10061,11 +10037,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10094,11 +10070,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10125,11 +10101,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10158,11 +10134,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10191,11 +10167,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10224,11 +10200,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10257,11 +10233,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10290,11 +10266,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10323,11 +10299,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21", @@ -10356,11 +10332,11 @@ "cset w22, eq", "cset w23, lo", "cset w24, vs", - "orr w23, w23, w24", + "cset w26, vc", + "and w23, w23, w26", "lsl x23, x23, #29", "orr w22, w22, w24", "orr w22, w23, w22, lsl #30", - "eor w26, w24, #0x1", "ldrb w23, [x28, #1298]", "lsl w21, w21, w20", "bic w21, w23, w21",