diff --git a/FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp b/FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
index c7323c8c1..1e222351c 100644
--- a/FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
+++ b/FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
@@ -156,13 +156,6 @@ DeadFlagCalculationEliminination::Classify(IROp_Header *IROp)
     case OP_LOADNZCV:
       return {.Read = FLAG_NZCV};
 
-    case OP_RMIFNZCV: // TODO: Optimize?
-      return {
-        .Read = FLAG_NZCV,
-        .Write = FLAG_NZCV,
-        .CanEliminate = true,
-      };
-
     case OP_ADCNZCV:
     case OP_SBBNZCV:
       return {
@@ -193,6 +186,20 @@ DeadFlagCalculationEliminination::Classify(IROp_Header *IROp)
       };
     }
 
+    case OP_RMIFNZCV: {
+      auto Op = IROp->CW<IR::IROp_RmifNZCV>();
+
+      static_assert(FLAG_N == (1 << 3), "rmif mask lines up with our bits");
+      static_assert(FLAG_Z == (1 << 2), "rmif mask lines up with our bits");
+      static_assert(FLAG_C == (1 << 1), "rmif mask lines up with our bits");
+      static_assert(FLAG_V == (1 << 0), "rmif mask lines up with our bits");
+
+      return {
+        .Write = Op->Mask,
+        .CanEliminate = true,
+      };
+    }
+
     case OP_INVALIDATEFLAGS: {
       auto Op = IROp->CW<IR::IROp_InvalidateFlags>();
       unsigned Flags = 0;