diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index a775f943b..88929fbf4 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -140,13 +140,13 @@ void OpDispatchBuilder::LEAOp(OpcodeArgs) {
                                                                                                                               OpSize::i32Bit;
 
     auto Src = LoadSourceGPR_WithOpSize(Op, Op->Src[0], SrcSize, Op->Flags, {.LoadData = false, .AllowUpperGarbage = SrcSize > DstSize});
-    StoreResultGPR_WithOpSize(Op, Op->Dest, Src, DstSize, OpSize::iInvalid);
+    StoreResultGPR_WithOpSize(Op, Op->Dest, Src, DstSize);
   } else {
     const auto DstSize =
       X86Tables::DecodeFlags::GetOpAddr(Op->Flags, 0) == X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST ? OpSize::i16Bit : OpSize::i32Bit;
 
     auto Src = LoadSourceGPR_WithOpSize(Op, Op->Src[0], SrcSize, Op->Flags, {.LoadData = false, .AllowUpperGarbage = SrcSize > DstSize});
-    StoreResultGPR_WithOpSize(Op, Op->Dest, Src, DstSize, OpSize::iInvalid);
+    StoreResultGPR_WithOpSize(Op, Op->Dest, Src, DstSize);
   }
 }
 
@@ -314,7 +314,7 @@ void OpDispatchBuilder::ADCOp(OpcodeArgs, uint32_t SrcIndex) {
   }
 
   if (!DestIsLockedMem(Op)) {
-    StoreResultGPR(Op, Result, OpSize::iInvalid);
+    StoreResultGPR(Op, Result);
   }
 }
 
@@ -341,7 +341,7 @@ void OpDispatchBuilder::SBBOp(OpcodeArgs, uint32_t SrcIndex) {
   Result = CalculateFlags_SBB(Size, Before, Src);
 
   if (!DestIsLockedMem(Op)) {
-    StoreResultGPR(Op, Result, OpSize::iInvalid);
+    StoreResultGPR(Op, Result);
   }
 }
 
@@ -350,7 +350,7 @@ void OpDispatchBuilder::SALCOp(OpcodeArgs) {
 
   auto Result = NZCVSelect(OpSize::i32Bit, CondClass::UGE /* CF = 1 */, _InlineConstant(0xffffffff), _InlineConstant(0));
 
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 }
 
 void OpDispatchBuilder::PUSHOp(OpcodeArgs) {
@@ -446,7 +446,7 @@ void OpDispatchBuilder::PUSHSegmentOp(OpcodeArgs, uint32_t SegmentReg) {
 
 void OpDispatchBuilder::POPOp(OpcodeArgs) {
   Ref Value = Pop(OpSizeFromSrc(Op));
-  StoreResultGPR(Op, Value, OpSize::iInvalid);
+  StoreResultGPR(Op, Value);
 }
 
 void OpDispatchBuilder::POPAOp(OpcodeArgs) {
@@ -657,7 +657,7 @@ void OpDispatchBuilder::SETccOp(OpcodeArgs) {
     SrcCond = LoadPFRaw(true, ParityJumpIsJP(Op->OP & 0xf));
   }
 
-  StoreResultGPR(Op, SrcCond, OpSize::iInvalid);
+  StoreResultGPR(Op, SrcCond);
 }
 
 void OpDispatchBuilder::CMOVOp(OpcodeArgs) {
@@ -690,7 +690,7 @@ void OpDispatchBuilder::CMOVOp(OpcodeArgs) {
     SrcCond = _NZCVSelect(ResultSize, CondClass::NEQ, Src, Dest);
   }
 
-  StoreResultGPR(Op, SrcCond, OpSize::iInvalid);
+  StoreResultGPR(Op, SrcCond);
 }
 
 void OpDispatchBuilder::CondJUMPOp(OpcodeArgs) {
@@ -836,7 +836,7 @@ void OpDispatchBuilder::LoopOp(OpcodeArgs) {
 
   Ref CondReg = LoadSourceGPR_WithOpSize(Op, Op->Src[0], SrcSize, Op->Flags);
   CondReg = Sub(OpSize, CondReg, 1);
-  StoreResultGPR(Op, Op->Src[0], CondReg, OpSize::iInvalid);
+  StoreResultGPR(Op, Op->Src[0], CondReg);
 
   // If LOOPE then jumps to target if RCX != 0 && ZF == 1
   // If LOOPNE then jumps to target if RCX != 0 && ZF == 0
@@ -1073,14 +1073,14 @@ void OpDispatchBuilder::MOVSXDOp(OpcodeArgs) {
   Ref Src = LoadSourceGPR_WithOpSize(Op, Op->Src[0], Size, Op->Flags, {.AllowUpperGarbage = Sext});
   if (Size == OpSize::i16Bit) {
     // This'll make sure to insert in to the lower 16bits without modifying upper bits
-    StoreResultGPR_WithOpSize(Op, Op->Dest, Src, Size, OpSize::iInvalid);
+    StoreResultGPR_WithOpSize(Op, Op->Dest, Src, Size);
   } else if (Sext) {
     // With REX.W then Sext
     Src = _Sbfe(OpSize::i64Bit, IR::OpSizeAsBits(Size), 0, Src);
-    StoreResultGPR(Op, Src, OpSize::iInvalid);
+    StoreResultGPR(Op, Src);
   } else {
     // Without REX.W then Zext (store result implicitly zero extends)
-    StoreResultGPR(Op, Src, OpSize::iInvalid);
+    StoreResultGPR(Op, Src);
   }
 }
 
@@ -1093,13 +1093,13 @@ void OpDispatchBuilder::MOVSXOp(OpcodeArgs) {
   // path for 32-bit dests where the native 32-bit Sbfe zero extends the top.
   const auto DstSize = OpSizeFromDst(Op);
   Src = _Sbfe(DstSize == OpSize::i64Bit ? OpSize::i64Bit : OpSize::i32Bit, IR::OpSizeAsBits(Size), 0, Src);
-  StoreResultGPR(Op, Op->Dest, Src, OpSize::iInvalid);
+  StoreResultGPR(Op, Op->Dest, Src);
 }
 
 void OpDispatchBuilder::MOVZXOp(OpcodeArgs) {
   Ref Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags);
   // Store result implicitly zero extends
-  StoreResultGPR(Op, Src, OpSize::iInvalid);
+  StoreResultGPR(Op, Src);
 }
 
 void OpDispatchBuilder::CMPOp(OpcodeArgs, uint32_t SrcIndex) {
@@ -1115,7 +1115,7 @@ void OpDispatchBuilder::CQOOp(OpcodeArgs) {
   auto Size = OpSizeFromSrc(Op);
   Ref Upper = _Sbfe(std::max(OpSize::i32Bit, Size), 1, GetSrcBitSize(Op) - 1, Src);
 
-  StoreResultGPR(Op, Upper, OpSize::iInvalid);
+  StoreResultGPR(Op, Upper);
 }
 
 void OpDispatchBuilder::XCHGOp(OpcodeArgs) {
@@ -1158,7 +1158,7 @@ void OpDispatchBuilder::XCHGOp(OpcodeArgs) {
       _MonoBackpatcherWrite(OpSizeFromSrc(Op), Src, Dest);
     } else {
       auto Result = _AtomicSwap(OpSizeFromSrc(Op), Src, Dest);
-      StoreResultGPR(Op, Op->Src[0], Result, OpSize::iInvalid);
+      StoreResultGPR(Op, Op->Src[0], Result);
     }
   } else {
     // AllowUpperGarbage: OK to allow as it will be overwritten by StoreResult.
@@ -1166,8 +1166,8 @@ void OpDispatchBuilder::XCHGOp(OpcodeArgs) {
 
     // Swap the contents
     // Order matters here since we don't want to swap context contents for one that effects the other
-    StoreResultGPR(Op, Op->Dest, Src, OpSize::iInvalid);
-    StoreResultGPR(Op, Op->Src[0], Dest, OpSize::iInvalid);
+    StoreResultGPR(Op, Op->Dest, Src);
+    StoreResultGPR(Op, Op->Src[0], Dest);
   }
 }
 
@@ -1178,7 +1178,7 @@ void OpDispatchBuilder::CDQOp(OpcodeArgs) {
 
   Src = _Sbfe(DstSize <= OpSize::i32Bit ? OpSize::i32Bit : OpSize::i64Bit, IR::OpSizeAsBits(SrcSize), 0, Src);
 
-  StoreResultGPR_WithOpSize(Op, Op->Dest, Src, DstSize, OpSize::iInvalid);
+  StoreResultGPR_WithOpSize(Op, Op->Dest, Src, DstSize);
 }
 
 void OpDispatchBuilder::SAHFOp(OpcodeArgs) {
@@ -1334,10 +1334,10 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs, bool ToSeg) {
     }
     if (DestIsMem(Op)) {
       // If the destination is memory then we always store 16-bits only
-      StoreResultGPR_WithOpSize(Op, Op->Dest, Segment, OpSize::i16Bit, OpSize::iInvalid);
+      StoreResultGPR_WithOpSize(Op, Op->Dest, Segment, OpSize::i16Bit);
     } else {
       // If the destination is a GPR then we follow register storing rules
-      StoreResultGPR(Op, Segment, OpSize::iInvalid);
+      StoreResultGPR(Op, Segment);
     }
   }
 }
@@ -1372,7 +1372,7 @@ void OpDispatchBuilder::MOVOffsetOp(OpcodeArgs) {
       auto A = GenMemSrcFromOp(0);
       Src = _LoadMemGPRAutoTSO(OpSize, A, OpSize::i8Bit);
     }
-    StoreResultGPR(Op, Op->Dest, Src, OpSize::iInvalid);
+    StoreResultGPR(Op, Op->Dest, Src);
     break;
   }
   case 0xA2:
@@ -1384,7 +1384,7 @@ void OpDispatchBuilder::MOVOffsetOp(OpcodeArgs) {
     // This one is a bit special since the destination is a literal
     // So the destination gets stored in Src[1]
     if (Op->Src[1].Data.Literal.Size <= 4) {
-      StoreResultGPR(Op, Op->Src[1], Src, OpSize::iInvalid);
+      StoreResultGPR(Op, Op->Src[1], Src);
     } else {
       const auto OpSize = OpSizeFromSrc(Op);
       auto A = GenMemSrcFromOp(1);
@@ -1456,7 +1456,7 @@ void OpDispatchBuilder::SHLImmediateOp(OpcodeArgs, bool SHL1Bit) {
 
   CalculateFlags_ShiftLeftImmediate(OpSizeFromSrc(Op), Result, Dest, Shift);
   CalculateDeferredFlags();
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 }
 
 void OpDispatchBuilder::SHROp(OpcodeArgs) {
@@ -1477,7 +1477,7 @@ void OpDispatchBuilder::SHRImmediateOp(OpcodeArgs, bool SHR1Bit) {
 
   CalculateFlags_ShiftRightImmediate(OpSizeFromSrc(Op), ALUOp, Dest, Shift);
   CalculateDeferredFlags();
-  StoreResultGPR(Op, ALUOp, OpSize::iInvalid);
+  StoreResultGPR(Op, ALUOp);
 }
 
 void OpDispatchBuilder::SHLDOp(OpcodeArgs) {
@@ -1547,10 +1547,10 @@ void OpDispatchBuilder::SHLDImmediateOp(OpcodeArgs) {
 
     CalculateFlags_ShiftLeftImmediate(OpSizeFromSrc(Op), Res, Dest, Shift);
     CalculateDeferredFlags();
-    StoreResultGPR(Op, Res, OpSize::iInvalid);
+    StoreResultGPR(Op, Res);
   } else if (Shift == 0 && Size == 32) {
     // Ensure Zext still occurs
-    StoreResultGPR(Op, Dest, OpSize::iInvalid);
+    StoreResultGPR(Op, Dest);
   }
 }
 
@@ -1610,11 +1610,11 @@ void OpDispatchBuilder::SHRDImmediateOp(OpcodeArgs) {
       Res = _Extr(OpSizeFromSrc(Op), Src, Dest, Shift);
     }
 
-    StoreResultGPR(Op, Res, OpSize::iInvalid);
+    StoreResultGPR(Op, Res);
     CalculateFlags_ShiftRightDoubleImmediate(OpSizeFromSrc(Op), Res, Dest, Shift);
   } else if (Shift == 0 && Size == 32) {
     // Ensure Zext still occurs
-    StoreResultGPR(Op, Dest, OpSize::iInvalid);
+    StoreResultGPR(Op, Dest);
   }
 }
 
@@ -1638,7 +1638,7 @@ void OpDispatchBuilder::ASHROp(OpcodeArgs, bool Immediate, bool SHR1Bit) {
 
     CalculateFlags_SignShiftRightImmediate(OpSizeFromSrc(Op), Result, Dest, Shift);
     CalculateDeferredFlags();
-    StoreResultGPR(Op, Result, OpSize::iInvalid);
+    StoreResultGPR(Op, Result);
   } else {
     auto Src = LoadSourceGPR(Op, Op->Src[1], Op->Flags, {.AllowUpperGarbage = true});
     Ref Result = _Ashr(OpSize, Dest, Src);
@@ -1679,7 +1679,7 @@ void OpDispatchBuilder::RotateOp(OpcodeArgs, bool Left, bool IsImmediate, bool I
 
   // To rotate 64-bits left, right-rotate by (64 - Shift) = -Shift mod 64.
   auto Res = _Ror(OpSize, Dest, (Left ? Src.Neg() : Src).Ref());
-  StoreResultGPR(Op, Res, OpSize::iInvalid);
+  StoreResultGPR(Op, Res);
 
   if (Is1Bit || IsImmediate) {
     if (UnmaskedSrc.C) {
@@ -1713,7 +1713,7 @@ void OpDispatchBuilder::ANDNBMIOp(OpcodeArgs) {
 
   auto Dest = _Andn(OpSizeFromSrc(Op), Src2, Src1);
 
-  StoreResultGPR(Op, Dest, OpSize::iInvalid);
+  StoreResultGPR(Op, Dest);
   CalculateFlags_Logical(OpSizeFromSrc(Op), Dest);
 }
 
@@ -1752,7 +1752,7 @@ void OpDispatchBuilder::BEXTRBMIOp(OpcodeArgs) {
   auto Dest = _Select(Size, Size, CondClass::ULE, Length, MaxSrcBitOp, Masked, SanitizedShifted);
 
   // Finally store the result.
-  StoreResultGPR(Op, Dest, OpSize::iInvalid);
+  StoreResultGPR(Op, Dest);
 
   // ZF is set properly. CF and OF are defined as being set to zero. SF, PF, and
   // AF are undefined.
@@ -1769,7 +1769,7 @@ void OpDispatchBuilder::BLSIBMIOp(OpcodeArgs) {
   auto NegatedSrc = _Neg(Size, Src);
   auto Result = _And(Size, Src, NegatedSrc);
 
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 
   // CF is cleared if Src is zero, otherwise it's set. However, Src is zero iff
   // Result is zero, so we can test the result instead. So, CF is just the
@@ -1789,7 +1789,7 @@ void OpDispatchBuilder::BLSMSKBMIOp(OpcodeArgs) {
   auto* Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true});
   auto Result = _Xor(Size, Sub(Size, Src, 1), Src);
 
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
   InvalidatePF_AF();
 
   // CF set according to the Src
@@ -1809,7 +1809,7 @@ void OpDispatchBuilder::BLSRBMIOp(OpcodeArgs) {
   auto* Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true});
   auto Result = _And(Size, Sub(Size, Src, 1), Src);
 
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 
   auto CFInv = To01(OpSize::i64Bit, Src);
 
@@ -1841,7 +1841,7 @@ void OpDispatchBuilder::BMI2Shift(OpcodeArgs) {
     Result = _Lshr(Size, Src, Shift);
   }
 
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 }
 
 void OpDispatchBuilder::BZHI(OpcodeArgs) {
@@ -1868,7 +1868,7 @@ void OpDispatchBuilder::BZHI(OpcodeArgs) {
   // shenanigans and use the raw versions here.
   _TestNZ(OpSize::i64Bit, Index, Constant(0xFF & ~(OperandSize - 1)));
   auto Result = _NZCVSelect(Size, CondClass::NEQ, Src, MaskResult);
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 
   auto CFInv = _NZCVSelect01(CondClass::EQ);
 
@@ -1903,7 +1903,7 @@ void OpDispatchBuilder::RORX(OpcodeArgs) {
     Result = _Ror(OpSizeFromSrc(Op), Src, _InlineConstant(Amount));
   }
 
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 }
 
 void OpDispatchBuilder::MULX(OpcodeArgs) {
@@ -1923,13 +1923,13 @@ void OpDispatchBuilder::MULX(OpcodeArgs) {
   // will be the high half of the multiplication result.
   if (Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
     Ref ResultHi = _UMulH(OpSize, Src1, Src2);
-    StoreResultGPR(Op, Op->Dest, ResultHi, OpSize::iInvalid);
+    StoreResultGPR(Op, Op->Dest, ResultHi);
   } else {
     Ref ResultLo = _UMul(OpSize, Src1, Src2);
     Ref ResultHi = _UMulH(OpSize, Src1, Src2);
 
-    StoreResultGPR(Op, Op->Src[0], ResultLo, OpSize::iInvalid);
-    StoreResultGPR(Op, Op->Dest, ResultHi, OpSize::iInvalid);
+    StoreResultGPR(Op, Op->Src[0], ResultLo);
+    StoreResultGPR(Op, Op->Dest, ResultHi);
   }
 }
 
@@ -1939,7 +1939,7 @@ void OpDispatchBuilder::PDEP(OpcodeArgs) {
   auto* Mask = LoadSourceGPR(Op, Op->Src[1], Op->Flags, {.AllowUpperGarbage = true});
   auto Result = _PDep(OpSizeFromSrc(Op), Input, Mask);
 
-  StoreResultGPR(Op, Op->Dest, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Op->Dest, Result);
 }
 
 void OpDispatchBuilder::PEXT(OpcodeArgs) {
@@ -1948,7 +1948,7 @@ void OpDispatchBuilder::PEXT(OpcodeArgs) {
   auto* Mask = LoadSourceGPR(Op, Op->Src[1], Op->Flags, {.AllowUpperGarbage = true});
   auto Result = _PExt(OpSizeFromSrc(Op), Input, Mask);
 
-  StoreResultGPR(Op, Op->Dest, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Op->Dest, Result);
 }
 
 void OpDispatchBuilder::ADXOp(OpcodeArgs) {
@@ -1977,7 +1977,7 @@ void OpDispatchBuilder::ADXOp(OpcodeArgs) {
   // Do the actual add.
   HandleNZCV_RMW();
   auto Result = _AdcWithFlags(OpSize, Src, Before);
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 
   // Now restore all flags except the one we're updating.
   if (CTX->HostFeatures.SupportsFlagM) {
@@ -2026,7 +2026,7 @@ void OpDispatchBuilder::RCROp1Bit(OpcodeArgs) {
     Res = _Orlshl(OpSize::i32Bit, Res, CF, Size - Shift);
   }
 
-  StoreResultGPR(Op, Res, OpSize::iInvalid);
+  StoreResultGPR(Op, Res);
 
   // OF is the top two MSBs XOR'd together
   // Only when Shift == 1, it is undefined otherwise
@@ -2048,7 +2048,7 @@ void OpDispatchBuilder::RCROp8x1Bit(OpcodeArgs) {
   Ref Res = _Bfe(OpSize::i32Bit, 7, 1, Dest);
   Res = _Bfi(OpSize::i32Bit, 1, 7, Res, CF);
 
-  StoreResultGPR(Op, Res, OpSize::iInvalid);
+  StoreResultGPR(Op, Res);
 
   // OF is the top two MSBs XOR'd together
   SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(_XorShift(OpSize::i32Bit, Res, Res, ShiftType::LSR, 1), SizeBit - 2, true);
@@ -2101,7 +2101,7 @@ void OpDispatchBuilder::RCROp(OpcodeArgs) {
       SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(Xor, Size - 2, true);
     }
 
-    StoreResultGPR(Op, Res, OpSize::iInvalid);
+    StoreResultGPR(Op, Res);
     return;
   }
 
@@ -2141,7 +2141,7 @@ void OpDispatchBuilder::RCROp(OpcodeArgs) {
       auto Xor = _XorShift(OpSize, Res, Res, ShiftType::LSR, 1);
       SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(Xor, Size - 2, true);
 
-      StoreResultGPR(Op, Res, OpSize::iInvalid);
+      StoreResultGPR(Op, Res);
     },
     OpSizeFromSrc(Op) == OpSize::i32Bit ? std::make_optional(&OpDispatchBuilder::ZeroShiftResult) : std::nullopt);
 }
@@ -2227,7 +2227,7 @@ void OpDispatchBuilder::RCRSmallerOp(OpcodeArgs) {
     // rather than zeroes.
     Ref Res = _Lshr(OpSize::i64Bit, Tmp, Src.Ref());
 
-    StoreResultGPR(Op, Res, OpSize::iInvalid);
+    StoreResultGPR(Op, Res);
 
     // Our new CF will be bit (Shift - 1) of the source. 32-bit Lshr masks the
     // same as x86, but if we constant fold we must mask ourselves.
@@ -2267,7 +2267,7 @@ void OpDispatchBuilder::RCLOp1Bit(OpcodeArgs) {
   // Top two MSBs is CF and top bit of result
   SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(_Xor(OpSize, Res, Dest), Size - 1, true);
 
-  StoreResultGPR(Op, Res, OpSize::iInvalid);
+  StoreResultGPR(Op, Res);
 }
 
 void OpDispatchBuilder::RCLOp(OpcodeArgs) {
@@ -2317,7 +2317,7 @@ void OpDispatchBuilder::RCLOp(OpcodeArgs) {
       SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(NewOF, Size - 1, true);
     }
 
-    StoreResultGPR(Op, Res, OpSize::iInvalid);
+    StoreResultGPR(Op, Res);
     return;
   }
 
@@ -2356,7 +2356,7 @@ void OpDispatchBuilder::RCLOp(OpcodeArgs) {
       auto NewOF = _XorShift(OpSize, Res, NewCF, ShiftType::LSL, Size - 1);
       SetRFLAG<FEXCore::X86State::RFLAG_OF_RAW_LOC>(NewOF, Size - 1, true);
 
-      StoreResultGPR(Op, Res, OpSize::iInvalid);
+      StoreResultGPR(Op, Res);
     },
     OpSizeFromSrc(Op) == OpSize::i32Bit ? std::make_optional(&OpDispatchBuilder::ZeroShiftResult) : std::nullopt);
 }
@@ -2400,7 +2400,7 @@ void OpDispatchBuilder::RCLSmallerOp(OpcodeArgs) {
     // Which we emulate with a _Ror
     Ref Res = _Ror(OpSize::i64Bit, Tmp, Src.Neg().Ref());
 
-    StoreResultGPR(Op, Res, OpSize::iInvalid);
+    StoreResultGPR(Op, Res);
 
     // Our new CF is now at the bit position that we are shifting
     // Either 0 if CF hasn't changed (CF is living in bit 0)
@@ -2469,13 +2469,13 @@ void OpDispatchBuilder::BTOp(OpcodeArgs, uint32_t SrcIndex, BTAction Action) {
 
     case BTAction::BTClear: {
       Dest = _Andn(LshrOpSize, Dest, BitSelect.MaskBit(LshrOpSize).Ref());
-      StoreResultGPR(Op, Dest, OpSize::iInvalid);
+      StoreResultGPR(Op, Dest);
       break;
     }
 
     case BTAction::BTSet: {
       Dest = _Or(LshrOpSize, Dest, BitSelect.MaskBit(LshrOpSize).Ref());
-      StoreResultGPR(Op, Dest, OpSize::iInvalid);
+      StoreResultGPR(Op, Dest);
       break;
     }
 
@@ -2491,7 +2491,7 @@ void OpDispatchBuilder::BTOp(OpcodeArgs, uint32_t SrcIndex, BTAction Action) {
       SetRFLAG(Value, X86State::RFLAG_CF_RAW_LOC, Src.IsConstant ? Src.C : 0, true);
       CFInverted = true;
 
-      StoreResultGPR(Op, Dest, OpSize::iInvalid);
+      StoreResultGPR(Op, Dest);
       break;
     }
     }
@@ -2606,7 +2606,7 @@ void OpDispatchBuilder::IMUL1SrcOp(OpcodeArgs) {
   default: FEX_UNREACHABLE;
   }
 
-  StoreResultGPR(Op, Dest, OpSize::iInvalid);
+  StoreResultGPR(Op, Dest);
   CalculateFlags_MUL(Size, Dest, ResultHigh);
 }
 
@@ -2645,7 +2645,7 @@ void OpDispatchBuilder::IMUL2SrcOp(OpcodeArgs) {
   default: FEX_UNREACHABLE;
   }
 
-  StoreResultGPR(Op, Dest, OpSize::iInvalid);
+  StoreResultGPR(Op, Dest);
   CalculateFlags_MUL(Size, Dest, ResultHigh);
 }
 
@@ -2772,7 +2772,7 @@ void OpDispatchBuilder::NOTOp(OpcodeArgs) {
     // GPR version plays fast and loose with sizes, be safe for memory tho.
     Ref Src = LoadSourceGPR(Op, Op->Dest, Op->Flags);
     Src = _Xor(OpSize::i64Bit, Src, MaskConst);
-    StoreResultGPR(Op, Src, OpSize::iInvalid);
+    StoreResultGPR(Op, Src);
   } else {
     // Specially handle high bits so we can invert in place with the correct
     // mask and a larger type.
@@ -2801,7 +2801,7 @@ void OpDispatchBuilder::NOTOp(OpcodeArgs) {
 
     // Always store 64-bit, the Not/Xor correctly handle the upper bits and this
     // way we can delete the store.
-    StoreResultGPR_WithOpSize(Op, Dest, Src, GPRSize, OpSize::iInvalid);
+    StoreResultGPR_WithOpSize(Op, Dest, Src, GPRSize);
   }
 }
 
@@ -2815,23 +2815,23 @@ void OpDispatchBuilder::XADDOp(OpcodeArgs) {
     Result = CalculateFlags_ADD(OpSizeFromSrc(Op), Dest, Src);
 
     // Previous value in dest gets stored in src
-    StoreResultGPR(Op, Op->Src[0], Dest, OpSize::iInvalid);
+    StoreResultGPR(Op, Op->Src[0], Dest);
 
     // Calculated value gets stored in dst (order is important if dst is same as src)
-    StoreResultGPR(Op, Result, OpSize::iInvalid);
+    StoreResultGPR(Op, Result);
   } else {
     HandledLock = Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_LOCK;
     Dest = AppendSegmentOffset(Dest, Op->Flags);
     auto Before = _AtomicFetchAdd(OpSizeFromSrc(Op), Src, Dest);
     CalculateFlags_ADD(OpSizeFromSrc(Op), Before, Src);
-    StoreResultGPR(Op, Op->Src[0], Before, OpSize::iInvalid);
+    StoreResultGPR(Op, Op->Src[0], Before);
   }
 }
 
 void OpDispatchBuilder::PopcountOp(OpcodeArgs) {
   Ref Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = CTX->HostFeatures.SupportsCSSC || GetSrcSize(Op) >= 4});
   Src = _Popcount(OpSizeFromSrc(Op), Src);
-  StoreResultGPR(Op, Src, OpSize::iInvalid);
+  StoreResultGPR(Op, Src);
 
   // We need to set ZF while clearing the rest of NZCV. The result of a popcount
   // is in the range [0, 63]. In particular, it is always positive. So a
@@ -2978,7 +2978,7 @@ void OpDispatchBuilder::ReadSegmentReg(OpcodeArgs, OpDispatchBuilder::Segment Se
     Src = _LoadContextGPR(Size, offsetof(FEXCore::Core::CPUState, gs_cached));
   }
 
-  StoreResultGPR(Op, Src, OpSize::iInvalid);
+  StoreResultGPR(Op, Src);
 }
 
 void OpDispatchBuilder::WriteSegmentReg(OpcodeArgs, OpDispatchBuilder::Segment Seg) {
@@ -3106,7 +3106,7 @@ void OpDispatchBuilder::SMSWOp(OpcodeArgs) {
     DstSize = OpSize::i16Bit;
   }
 
-  StoreResultGPR_WithOpSize(Op, Op->Dest, Const, DstSize, OpSize::iInvalid);
+  StoreResultGPR_WithOpSize(Op, Op->Dest, Const, DstSize);
 }
 
 OpDispatchBuilder::CycleCounterPair OpDispatchBuilder::CycleCounter(bool SelfSynchronizingLoads) {
@@ -3168,7 +3168,7 @@ void OpDispatchBuilder::INCOp(OpcodeArgs) {
   }
 
   if (!IsLocked) {
-    StoreResultGPR(Op, Result, OpSize::iInvalid);
+    StoreResultGPR(Op, Result);
   }
 }
 
@@ -3209,7 +3209,7 @@ void OpDispatchBuilder::DECOp(OpcodeArgs) {
   }
 
   if (!IsLocked) {
-    StoreResultGPR(Op, Result, OpSize::iInvalid);
+    StoreResultGPR(Op, Result);
   }
 }
 
@@ -3448,7 +3448,7 @@ void OpDispatchBuilder::LODSOp(OpcodeArgs) {
 
     auto Src = _LoadMemGPRAutoTSO(Size, Dest_RSI, Size);
 
-    StoreResultGPR(Op, Src, OpSize::iInvalid);
+    StoreResultGPR(Op, Src);
 
     // Offset the pointer
     Ref TailDest_RSI = LoadGPRRegister(X86State::REG_RSI);
@@ -3489,7 +3489,7 @@ void OpDispatchBuilder::LODSOp(OpcodeArgs) {
 
         auto Src = _LoadMemGPRAutoTSO(Size, Dest_RSI, Size);
 
-        StoreResultGPR(Op, Src, OpSize::iInvalid);
+        StoreResultGPR(Op, Src);
 
         Ref TailCounter = LoadGPRRegister(X86State::REG_RCX);
         Ref TailDest_RSI = LoadGPRRegister(X86State::REG_RSI);
@@ -3616,7 +3616,7 @@ void OpDispatchBuilder::BSWAPOp(OpcodeArgs) {
     Dest = LoadSourceGPR_WithOpSize(Op, Op->Dest, GetGPROpSize(), Op->Flags);
     Dest = _Rev(Size, Dest);
   }
-  StoreResultGPR(Op, Dest, OpSize::iInvalid);
+  StoreResultGPR(Op, Dest);
 }
 
 void OpDispatchBuilder::PUSHFOp(OpcodeArgs) {
@@ -3656,7 +3656,7 @@ void OpDispatchBuilder::NEGOp(OpcodeArgs) {
     Ref Dest = LoadSourceGPR(Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = true});
     Ref Result = CalculateFlags_SUB(Size, ZeroConst, Dest);
 
-    StoreResultGPR(Op, Result, OpSize::iInvalid);
+    StoreResultGPR(Op, Result);
   }
 }
 
@@ -3763,7 +3763,7 @@ void OpDispatchBuilder::BSFOp(OpcodeArgs) {
   // hardware satisfies it. We provide the stronger AMD behaviour as
   // applications might rely on that in the wild.
   auto SelectOp = NZCVSelect(GPRSize, CondClass::EQ, Dest, Result);
-  StoreResultGPR_WithOpSize(Op, Op->Dest, SelectOp, DstSize, OpSize::iInvalid);
+  StoreResultGPR_WithOpSize(Op, Op->Dest, SelectOp, DstSize);
 }
 
 void OpDispatchBuilder::BSROp(OpcodeArgs) {
@@ -3781,7 +3781,7 @@ void OpDispatchBuilder::BSROp(OpcodeArgs) {
 
   // If Src was zero then the destination doesn't get modified
   auto SelectOp = NZCVSelect(GPRSize, CondClass::EQ, Dest, Result);
-  StoreResultGPR_WithOpSize(Op, Op->Dest, SelectOp, DstSize, OpSize::iInvalid);
+  StoreResultGPR_WithOpSize(Op, Op->Dest, SelectOp, DstSize);
 }
 
 void OpDispatchBuilder::CMPXCHGOp(OpcodeArgs) {
@@ -3851,9 +3851,9 @@ void OpDispatchBuilder::CMPXCHGOp(OpcodeArgs) {
 
     // Store in to GPR Dest
     if (GPRSize == OpSize::i64Bit && Size == OpSize::i32Bit) {
-      StoreResultGPR_WithOpSize(Op, Op->Dest, DestResult, GPRSize, OpSize::iInvalid);
+      StoreResultGPR_WithOpSize(Op, Op->Dest, DestResult, GPRSize);
     } else {
-      StoreResultGPR(Op, DestResult, OpSize::iInvalid);
+      StoreResultGPR(Op, DestResult);
     }
   } else {
     Ref Src2 = LoadSourceGPR(Op, Op->Src[0], Op->Flags);
@@ -4511,7 +4511,7 @@ void OpDispatchBuilder::ALUOp(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::I
     FlushRegisterCache();
 
     // Move 0 into the register
-    StoreResultGPR(Op, Constant(0), OpSize::iInvalid);
+    StoreResultGPR(Op, Constant(0));
     return;
   }
 
@@ -4732,7 +4732,7 @@ void OpDispatchBuilder::TZCNT(OpcodeArgs) {
   Ref Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true});
 
   Src = _FindTrailingZeroes(OpSizeFromSrc(Op), Src);
-  StoreResultGPR(Op, Src, OpSize::iInvalid);
+  StoreResultGPR(Op, Src);
 
   CalculateFlags_ZCNT(OpSizeFromSrc(Op), Src);
 }
@@ -4742,7 +4742,7 @@ void OpDispatchBuilder::LZCNT(OpcodeArgs) {
   Ref Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true});
 
   auto Res = _CountLeadingZeroes(OpSizeFromSrc(Op), Src);
-  StoreResultGPR(Op, Res, OpSize::iInvalid);
+  StoreResultGPR(Op, Res);
   CalculateFlags_ZCNT(OpSizeFromSrc(Op), Res);
 }
 
@@ -4754,7 +4754,7 @@ void OpDispatchBuilder::MOVBEOp(OpcodeArgs) {
 
   if (DestIsMem(Op) || SrcSize != OpSize::i16Bit) {
     Src = _Rev(SrcSize, Src);
-    StoreResultGPR(Op, Op->Dest, Src, OpSize::iInvalid);
+    StoreResultGPR(Op, Op->Dest, Src);
   } else {
     Src = _Rev(std::max(OpSize::i32Bit, SrcSize), Src);
     // 16-bit does an insert.
@@ -4762,7 +4762,7 @@ void OpDispatchBuilder::MOVBEOp(OpcodeArgs) {
     // bfxil the 16-bit result in to the GPR.
     Ref Dest = LoadSourceGPR_WithOpSize(Op, Op->Dest, GPRSize, Op->Flags);
     auto Result = _Bfxil(GPRSize, 16, 16, Dest, Src);
-    StoreResultGPR_WithOpSize(Op, Op->Dest, Result, GPRSize, OpSize::iInvalid);
+    StoreResultGPR_WithOpSize(Op, Op->Dest, Result, GPRSize);
   }
 }
 
@@ -4876,7 +4876,7 @@ void OpDispatchBuilder::RDTSCPOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::RDPIDOp(OpcodeArgs) {
-  StoreResultGPR(Op, _ProcessorID(), OpSize::iInvalid);
+  StoreResultGPR(Op, _ProcessorID());
 }
 
 void OpDispatchBuilder::CRC32(OpcodeArgs) {
@@ -4898,7 +4898,7 @@ void OpDispatchBuilder::CRC32(OpcodeArgs) {
     Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags, {.Align = OpSize::i8Bit});
   }
   auto Result = _CRC32(Dest, Src, OpSizeFromSrc(Op));
-  StoreResultGPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultGPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template<bool Reseed>
@@ -4908,7 +4908,7 @@ void OpDispatchBuilder::RDRANDOp(OpcodeArgs) {
     return;
   }
 
-  StoreResultGPR(Op, _RDRAND(Reseed), OpSize::iInvalid);
+  StoreResultGPR(Op, _RDRAND(Reseed));
 
   // If the rng number is valid then NZCV is 0b0000, otherwise NZCV is 0b0100
   auto CF_inv = GetRFLAG(X86State::RFLAG_ZF_RAW_LOC);
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
index 37c4784a6..d7c0f04c1 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h
@@ -1114,8 +1114,8 @@ public:
   // End of AVX 128-bit implementation
 
   // AVX 256-bit operations
-  void StoreResult_WithAVXInsert(VectorOpType Type, RegClass Class, FEXCore::X86Tables::DecodedOp Op, Ref Value, IR::OpSize Align,
-                                 MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
+  void StoreResult_WithAVXInsert(VectorOpType Type, RegClass Class, FEXCore::X86Tables::DecodedOp Op, Ref Value,
+                                 IR::OpSize Align = IR::OpSize::iInvalid, MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
     if (Op->Dest.IsGPR() && Op->Dest.Data.GPR.GPR >= X86State::REG_XMM_0 && Op->Dest.Data.GPR.GPR <= X86State::REG_XMM_15 &&
         GetGuestVectorLength() == OpSize::i256Bit && Type == VectorOpType::SSE) {
       const auto gpr = Op->Dest.Data.GPR.GPR;
@@ -1584,30 +1584,30 @@ private:
   void StoreResult_WithOpSize(RegClass Class, X86Tables::DecodedOp Op, const X86Tables::DecodedOperand& Operand, Ref Src, IR::OpSize OpSize,
                               IR::OpSize Align, MemoryAccessType AccessType = MemoryAccessType::DEFAULT);
   void StoreResultGPR_WithOpSize(X86Tables::DecodedOp Op, const X86Tables::DecodedOperand& Operand, Ref Src, IR::OpSize OpSize,
-                                 IR::OpSize Align, MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
+                                 IR::OpSize Align = IR::OpSize::iInvalid, MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
     StoreResult_WithOpSize(RegClass::GPR, Op, Operand, Src, OpSize, Align, AccessType);
   }
   void StoreResultFPR_WithOpSize(X86Tables::DecodedOp Op, const X86Tables::DecodedOperand& Operand, Ref Src, IR::OpSize OpSize,
-                                 IR::OpSize Align, MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
+                                 IR::OpSize Align = IR::OpSize::iInvalid, MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
     StoreResult_WithOpSize(RegClass::FPR, Op, Operand, Src, OpSize, Align, AccessType);
   }
 
   void StoreResult(RegClass Class, X86Tables::DecodedOp Op, const X86Tables::DecodedOperand& Operand, Ref Src, OpSize Align,
                    MemoryAccessType AccessType = MemoryAccessType::DEFAULT);
-  void StoreResultGPR(X86Tables::DecodedOp Op, const X86Tables::DecodedOperand& Operand, Ref Src, OpSize Align,
+  void StoreResultGPR(X86Tables::DecodedOp Op, const X86Tables::DecodedOperand& Operand, Ref Src, OpSize Align = OpSize::iInvalid,
                       MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
     StoreResult(RegClass::GPR, Op, Operand, Src, Align, AccessType);
   }
-  void StoreResultFPR(X86Tables::DecodedOp Op, const X86Tables::DecodedOperand& Operand, Ref Src, OpSize Align,
+  void StoreResultFPR(X86Tables::DecodedOp Op, const X86Tables::DecodedOperand& Operand, Ref Src, OpSize Align = OpSize::iInvalid,
                       MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
     StoreResult(RegClass::FPR, Op, Operand, Src, Align, AccessType);
   }
 
   void StoreResult(RegClass Class, X86Tables::DecodedOp Op, Ref Src, OpSize Align, MemoryAccessType AccessType = MemoryAccessType::DEFAULT);
-  void StoreResultGPR(X86Tables::DecodedOp Op, Ref Src, OpSize Align, MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
+  void StoreResultGPR(X86Tables::DecodedOp Op, Ref Src, OpSize Align = OpSize::iInvalid, MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
     StoreResult(RegClass::GPR, Op, Src, Align, AccessType);
   }
-  void StoreResultFPR(X86Tables::DecodedOp Op, Ref Src, OpSize Align, MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
+  void StoreResultFPR(X86Tables::DecodedOp Op, Ref Src, OpSize Align = OpSize::iInvalid, MemoryAccessType AccessType = MemoryAccessType::DEFAULT) {
     StoreResult(RegClass::FPR, Op, Src, Align, AccessType);
   }
 
@@ -2226,7 +2226,7 @@ private:
 
     HandleNZCV_RMW();
     CalculatePF(_ShiftFlags(OpSizeFromSrc(Op), Result, Dest, Shift, Src, OldPF, CFInverted));
-    StoreResultGPR(Op, Result, OpSize::iInvalid);
+    StoreResultGPR(Op, Result);
   }
 
   // Helper to derive Dest by a given builder-using Expression with the opcode
@@ -2315,7 +2315,7 @@ private:
       return;
     }
     auto Dest = LoadSourceGPR(Op, Op->Dest, Op->Flags);
-    StoreResultGPR(Op, Dest, OpSize::iInvalid);
+    StoreResultGPR(Op, Dest);
   }
 
   using ZeroShiftFunctionPtr = void (OpDispatchBuilder::*)(FEXCore::X86Tables::DecodedOp Op);
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp
index ed2223733..50cecdad8 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp
@@ -157,7 +157,7 @@ void OpDispatchBuilder::AVX128_VMOVScalarImpl(OpcodeArgs, IR::OpSize ElementSize
   } else {
     // VMOVSS/SD mem32/mem64, xmm1
     auto Src = AVX128_LoadSource_WithOpSize(Op, Op->Src[1], Op->Flags, false);
-    StoreResultFPR_WithOpSize(Op, Op->Dest, Src.Low, ElementSize, OpSize::iInvalid);
+    StoreResultFPR_WithOpSize(Op, Op->Dest, Src.Low, ElementSize);
   }
 }
 
@@ -593,7 +593,7 @@ void OpDispatchBuilder::AVX128_CVTFPR_To_GPR(OpcodeArgs, IR::OpSize SrcElementSi
   }
 
   Ref Result = CVTFPR_To_GPRImpl(Op, Src.Low, SrcElementSize, HostRoundingMode);
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 }
 
 void OpDispatchBuilder::AVX128_VANDN(OpcodeArgs) {
@@ -726,7 +726,7 @@ void OpDispatchBuilder::AVX128_MOVBetweenGPR_FPR(OpcodeArgs) {
       auto ElementSize = OpSizeFromDst(Op);
       // Extract element from GPR. Zero extending in the process.
       Src.Low = _VExtractToGPR(OpSizeFromSrc(Op), ElementSize, Src.Low, 0);
-      StoreResultGPR(Op, Op->Dest, Src.Low, OpSize::iInvalid);
+      StoreResultGPR(Op, Op->Dest, Src.Low);
     } else {
       // Storing first element to memory.
       Ref Dest = LoadSourceGPR(Op, Op->Dest, Op->Flags, {.LoadData = false});
@@ -758,7 +758,7 @@ void OpDispatchBuilder::AVX128_PExtr(OpcodeArgs, IR::OpSize ElementSize) {
     const auto GPRSize = GetGPROpSize();
     // Extract already zero extends the result.
     Ref Result = _VExtractToGPR(OpSize::i128Bit, OverridenElementSize, Src.Low, Index);
-    StoreResultGPR_WithOpSize(Op, Op->Dest, Result, GPRSize, OpSize::iInvalid);
+    StoreResultGPR_WithOpSize(Op, Op->Dest, Result, GPRSize);
     return;
   }
 
@@ -868,7 +868,7 @@ void OpDispatchBuilder::AVX128_MOVMSK(OpcodeArgs, IR::OpSize ElementSize) {
     auto GPRHigh = Mask8Byte(Src.High);
     GPR = _Orlshl(OpSize::i64Bit, GPRLow, GPRHigh, 2);
   }
-  StoreResultGPR_WithOpSize(Op, Op->Dest, GPR, GetGPROpSize(), OpSize::iInvalid);
+  StoreResultGPR_WithOpSize(Op, Op->Dest, GPR, GetGPROpSize());
 }
 
 void OpDispatchBuilder::AVX128_MOVMSKB(OpcodeArgs) {
@@ -897,7 +897,7 @@ void OpDispatchBuilder::AVX128_MOVMSKB(OpcodeArgs) {
     Result = _Orlshl(OpSize::i64Bit, Result, ResultHigh, 16);
   }
 
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 }
 
 void OpDispatchBuilder::AVX128_PINSRImpl(OpcodeArgs, IR::OpSize ElementSize, const X86Tables::DecodedOperand& Src1Op,
@@ -2295,7 +2295,7 @@ void OpDispatchBuilder::AVX128_VCVTPS2PH(OpcodeArgs) {
   }
 
   if (!Op->Dest.IsGPR()) {
-    StoreResultFPR_WithOpSize(Op, Op->Dest, Result.Low, StoreSize, OpSize::iInvalid);
+    StoreResultFPR_WithOpSize(Op, Op->Dest, Result.Low, StoreSize);
   } else {
     AVX128_StoreResult_WithOpSize(Op, Op->Dest, Result);
   }
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
index 623b82be9..1cd2948d7 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Crypto.cpp
@@ -36,7 +36,7 @@ void OpDispatchBuilder::SHA1NEXTEOp(OpcodeArgs) {
   auto Tmp = _VAdd(OpSize::i128Bit, OpSize::i32Bit, Src, RotatedNode);
   auto Result = _VInsElement(OpSize::i128Bit, OpSize::i32Bit, 3, 3, Src, Tmp);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::SHA1MSG1Op(OpcodeArgs) {
@@ -52,7 +52,7 @@ void OpDispatchBuilder::SHA1MSG1Op(OpcodeArgs) {
   // [W0, W1, W2, W3] ^ [W2, W3, W4, W5]
   Ref Result = _VXor(OpSize::i128Bit, OpSize::i8Bit, Dest, NewVec);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::SHA1MSG2Op(OpcodeArgs) {
@@ -70,7 +70,7 @@ void OpDispatchBuilder::SHA1MSG2Op(OpcodeArgs) {
   // The result is swizzled differently than expected
   auto Result = SHADataShuffle(_VSha1SU1(Src1, Src2));
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
@@ -112,7 +112,7 @@ void OpDispatchBuilder::SHA1RNDS4Op(OpcodeArgs) {
   case 3: Result = SHADataShuffle(_VSha1P(Src1, ZeroRegister, Src2)); break;
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::SHA256MSG1Op(OpcodeArgs) {
@@ -125,7 +125,7 @@ void OpDispatchBuilder::SHA256MSG1Op(OpcodeArgs) {
 
   auto Result = _VSha256U0(Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::SHA256MSG2Op(OpcodeArgs) {
@@ -142,7 +142,7 @@ void OpDispatchBuilder::SHA256MSG2Op(OpcodeArgs) {
 
   auto Result = _VSha256U1(Src1, Src2);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) {
@@ -177,7 +177,7 @@ void OpDispatchBuilder::SHA256RNDS2Op(OpcodeArgs) {
   auto B = _VSha256H2(EFGH, ABCD, Key);
   auto Result = shuffle_abcd(A, B);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::AESImcOp(OpcodeArgs) {
@@ -187,7 +187,7 @@ void OpDispatchBuilder::AESImcOp(OpcodeArgs) {
   }
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = _VAESImc(Src);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::AESEncOp(OpcodeArgs) {
@@ -198,7 +198,7 @@ void OpDispatchBuilder::AESEncOp(OpcodeArgs) {
   Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = _VAESEnc(OpSize::i128Bit, Dest, Src, LoadZeroVector(OpSize::i128Bit));
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VAESEncOp(OpcodeArgs) {
@@ -212,7 +212,7 @@ void OpDispatchBuilder::VAESEncOp(OpcodeArgs) {
   Ref Key = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
   Ref Result = _VAESEnc(DstSize, State, Key, LoadZeroVector(DstSize));
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::AESEncLastOp(OpcodeArgs) {
@@ -223,7 +223,7 @@ void OpDispatchBuilder::AESEncLastOp(OpcodeArgs) {
   Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = _VAESEncLast(OpSize::i128Bit, Dest, Src, LoadZeroVector(OpSize::i128Bit));
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VAESEncLastOp(OpcodeArgs) {
@@ -237,7 +237,7 @@ void OpDispatchBuilder::VAESEncLastOp(OpcodeArgs) {
   Ref Key = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
   Ref Result = _VAESEncLast(DstSize, State, Key, LoadZeroVector(DstSize));
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::AESDecOp(OpcodeArgs) {
@@ -248,7 +248,7 @@ void OpDispatchBuilder::AESDecOp(OpcodeArgs) {
   Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = _VAESDec(OpSize::i128Bit, Dest, Src, LoadZeroVector(OpSize::i128Bit));
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VAESDecOp(OpcodeArgs) {
@@ -262,7 +262,7 @@ void OpDispatchBuilder::VAESDecOp(OpcodeArgs) {
   Ref Key = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
   Ref Result = _VAESDec(DstSize, State, Key, LoadZeroVector(DstSize));
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::AESDecLastOp(OpcodeArgs) {
@@ -273,7 +273,7 @@ void OpDispatchBuilder::AESDecLastOp(OpcodeArgs) {
   Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = _VAESDecLast(OpSize::i128Bit, Dest, Src, LoadZeroVector(OpSize::i128Bit));
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VAESDecLastOp(OpcodeArgs) {
@@ -287,7 +287,7 @@ void OpDispatchBuilder::VAESDecLastOp(OpcodeArgs) {
   Ref Key = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
   Ref Result = _VAESDecLast(DstSize, State, Key, LoadZeroVector(DstSize));
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::AESKeyGenAssistImpl(OpcodeArgs) {
@@ -305,7 +305,7 @@ void OpDispatchBuilder::AESKeyGenAssist(OpcodeArgs) {
   }
 
   Ref Result = AESKeyGenAssistImpl(Op);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PCLMULQDQOp(OpcodeArgs) {
@@ -318,7 +318,7 @@ void OpDispatchBuilder::PCLMULQDQOp(OpcodeArgs) {
   const auto Selector = static_cast<uint8_t>(Op->Src[1].Literal());
 
   auto Res = _PCLMUL(OpSize::i128Bit, Dest, Src, Selector & 0b1'0001);
-  StoreResultFPR(Op, Res, OpSize::iInvalid);
+  StoreResultFPR(Op, Res);
 }
 
 void OpDispatchBuilder::VPCLMULQDQOp(OpcodeArgs) {
@@ -333,7 +333,7 @@ void OpDispatchBuilder::VPCLMULQDQOp(OpcodeArgs) {
   const auto Selector = static_cast<uint8_t>(Op->Src[2].Literal());
 
   Ref Res = _PCLMUL(DstSize, Src1, Src2, Selector & 0b1'0001);
-  StoreResultFPR(Op, Res, OpSize::iInvalid);
+  StoreResultFPR(Op, Res);
 }
 
 } // namespace FEXCore::IR
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
index c2d0d9eb5..1f1234b89 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -30,7 +30,7 @@ void OpDispatchBuilder::MOVVectorAlignedOp(OpcodeArgs) {
     return;
   }
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
-  StoreResultFPR(Op, Src, OpSize::iInvalid);
+  StoreResultFPR(Op, Src);
 }
 
 void OpDispatchBuilder::MOVVectorUnalignedOp(OpcodeArgs) {
@@ -80,7 +80,7 @@ void OpDispatchBuilder::VMOVAPS_VMOVAPDOp(OpcodeArgs) {
   if (Is128Bit && Op->Dest.IsGPR()) {
     Src = VZeroExtendOperand(OpSize::i128Bit, Op->Src[0], Src);
   }
-  StoreResultFPR(Op, Src, OpSize::iInvalid);
+  StoreResultFPR(Op, Src);
 }
 
 void OpDispatchBuilder::VMOVUPS_VMOVUPDOp(OpcodeArgs) {
@@ -102,14 +102,14 @@ void OpDispatchBuilder::MOVHPDOp(OpcodeArgs) {
       Ref Src = LoadSourceGPR(Op, Op->Src[0], Op->Flags);
       Ref Dest = LoadSourceFPR_WithOpSize(Op, Op->Dest, OpSize::i128Bit, Op->Flags);
       auto Result = _VInsElement(OpSize::i128Bit, OpSize::i64Bit, 1, 0, Dest, Src);
-      StoreResultFPR(Op, Result, OpSize::iInvalid);
+      StoreResultFPR(Op, Result);
     } else {
       // If the destination is a GPR then the source is memory
       // xmm1[127:64] = src
       Ref Src = MakeSegmentAddress(Op, Op->Src[0]);
       Ref Dest = LoadSourceFPR_WithOpSize(Op, Op->Dest, OpSize::i128Bit, Op->Flags);
       auto Result = _VLoadVectorElement(OpSize::i128Bit, OpSize::i64Bit, Dest, 1, Src);
-      StoreResultFPR(Op, Result, OpSize::iInvalid);
+      StoreResultFPR(Op, Result);
     }
   } else {
     // In this case memory is the destination and the high bits of the XMM are source
@@ -126,7 +126,7 @@ void OpDispatchBuilder::VMOVHPOp(OpcodeArgs) {
     Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags, {.Align = OpSize::i64Bit});
     Ref Result = _VInsElement(OpSize::i128Bit, OpSize::i64Bit, 1, 0, Src1, Src2);
 
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
   } else {
     Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags, {.Align = OpSize::i128Bit});
     Ref Result = _VInsElement(OpSize::i128Bit, OpSize::i64Bit, 0, 1, Src, Src);
@@ -147,7 +147,7 @@ void OpDispatchBuilder::MOVLPOp(OpcodeArgs) {
       Ref Src = MakeSegmentAddress(Op, Op->Src[0]);
       Ref Dest = LoadSourceFPR_WithOpSize(Op, Op->Dest, DstSize, Op->Flags);
       auto Result = _VLoadVectorElement(OpSize::i128Bit, OpSize::i64Bit, Dest, 0, Src);
-      StoreResultFPR(Op, Result, OpSize::iInvalid);
+      StoreResultFPR(Op, Result);
     }
   } else {
     Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags, {.Align = OpSize::i64Bit});
@@ -167,12 +167,12 @@ void OpDispatchBuilder::VMOVLPOp(OpcodeArgs) {
     // Bits[127:64] come from Src1[127:64]
     Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags, {.Align = OpSize::i64Bit});
     Ref Result = _VInsElement(OpSize::i128Bit, OpSize::i64Bit, 1, 1, Src2, Src1);
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
   } else {
     ///< VMOVHLPS/PD xmm1, xmm2, xmm3
     Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags, {.Align = OpSize::i128Bit});
     Ref Result = _VInsElement(OpSize::i128Bit, OpSize::i64Bit, 0, 1, Src1, Src2);
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
   }
 }
 
@@ -180,14 +180,14 @@ void OpDispatchBuilder::VMOVSHDUPOp(OpcodeArgs) {
   const auto SrcSize = OpSizeFromSrc(Op);
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = _VTrn2(SrcSize, OpSize::i32Bit, Src, Src);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VMOVSLDUPOp(OpcodeArgs) {
   const auto SrcSize = OpSizeFromSrc(Op);
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = _VTrn(SrcSize, OpSize::i32Bit, Src, Src);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::MOVScalarOpImpl(OpcodeArgs, IR::OpSize ElementSize) {
@@ -196,16 +196,16 @@ void OpDispatchBuilder::MOVScalarOpImpl(OpcodeArgs, IR::OpSize ElementSize) {
     Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
     Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
     auto Result = _VInsElement(OpSize::i128Bit, ElementSize, 0, 0, Dest, Src);
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
   } else if (Op->Dest.IsGPR()) {
     // MOVSS/SD xmm1, mem32/mem64
     // xmm1[127:0] <- zext(mem32/mem64)
     Ref Src = LoadSourceFPR_WithOpSize(Op, Op->Src[0], ElementSize, Op->Flags);
-    StoreResultFPR(Op, Src, OpSize::iInvalid);
+    StoreResultFPR(Op, Src);
   } else {
     // MOVSS/SD mem32/mem64, xmm1
     Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
-    StoreResultFPR_WithOpSize(Op, Op->Dest, Src, ElementSize, OpSize::iInvalid);
+    StoreResultFPR_WithOpSize(Op, Op->Dest, Src, ElementSize);
   }
 }
 
@@ -223,15 +223,15 @@ void OpDispatchBuilder::VMOVScalarOpImpl(OpcodeArgs, IR::OpSize ElementSize) {
     Ref Src1 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
     Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
     Ref Result = _VInsElement(OpSize::i128Bit, ElementSize, 0, 0, Src1, Src2);
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
   } else if (Op->Dest.IsGPR()) {
     // VMOVSS/SD xmm1, mem32/mem64
     Ref Src = LoadSourceFPR_WithOpSize(Op, Op->Src[1], ElementSize, Op->Flags);
-    StoreResultFPR(Op, Src, OpSize::iInvalid);
+    StoreResultFPR(Op, Src);
   } else {
     // VMOVSS/SD mem32/mem64, xmm1
     Ref Src = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
-    StoreResultFPR_WithOpSize(Op, Op->Dest, Src, ElementSize, OpSize::iInvalid);
+    StoreResultFPR_WithOpSize(Op, Op->Dest, Src, ElementSize);
   }
 }
 
@@ -250,7 +250,7 @@ void OpDispatchBuilder::VectorALUOp(OpcodeArgs, IROps IROp, IR::OpSize ElementSi
 
   DeriveOp(ALUOp, IROp, _VAdd(Size, ElementSize, Dest, Src));
 
-  StoreResultFPR(Op, ALUOp, OpSize::iInvalid);
+  StoreResultFPR(Op, ALUOp);
 }
 
 void OpDispatchBuilder::VectorXOROp(OpcodeArgs) {
@@ -259,7 +259,7 @@ void OpDispatchBuilder::VectorXOROp(OpcodeArgs) {
   // Special case for vector xor with itself being the optimal way for x86 to zero vector registers.
   if (Op->Dest.IsGPR() && Op->Src[0].IsGPR() && Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
     const auto ZeroRegister = LoadZeroVector(Size);
-    StoreResultFPR(Op, ZeroRegister, OpSize::iInvalid);
+    StoreResultFPR(Op, ZeroRegister);
     return;
   }
 
@@ -275,7 +275,7 @@ void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs, IROps IROp, IR::OpSize Elemen
 
   DeriveOp(ALUOp, IROp, _VAdd(Size, ElementSize, Src1, Src2));
 
-  StoreResultFPR(Op, ALUOp, OpSize::iInvalid);
+  StoreResultFPR(Op, ALUOp);
 }
 
 void OpDispatchBuilder::AVXVectorXOROp(OpcodeArgs) {
@@ -283,7 +283,7 @@ void OpDispatchBuilder::AVXVectorXOROp(OpcodeArgs) {
   if (Op->Src[0].IsGPR() && Op->Src[1].IsGPR() && Op->Src[0].Data.GPR.GPR == Op->Src[1].Data.GPR.GPR) {
     const auto DstSize = OpSizeFromDst(Op);
     const auto ZeroRegister = LoadZeroVector(DstSize);
-    StoreResultFPR(Op, ZeroRegister, OpSize::iInvalid);
+    StoreResultFPR(Op, ZeroRegister);
     return;
   }
 
@@ -298,7 +298,7 @@ void OpDispatchBuilder::VectorALUROp(OpcodeArgs, IROps IROp, IR::OpSize ElementS
 
   DeriveOp(ALUOp, IROp, _VAdd(Size, ElementSize, Src, Dest));
 
-  StoreResultFPR(Op, ALUOp, OpSize::iInvalid);
+  StoreResultFPR(Op, ALUOp);
 }
 
 Ref OpDispatchBuilder::VectorScalarInsertALUOpImpl(OpcodeArgs, IROps IROp, IR::OpSize DstSize, IR::OpSize ElementSize,
@@ -321,7 +321,7 @@ template<IROps IROp, IR::OpSize ElementSize>
 void OpDispatchBuilder::VectorScalarInsertALUOp(OpcodeArgs) {
   const auto DstSize = GetGuestVectorLength();
   auto Result = VectorScalarInsertALUOpImpl(Op, IROp, DstSize, ElementSize, Op->Dest, Op->Src[0], false);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::VectorScalarInsertALUOp<IR::OP_VFADDSCALARINSERT, OpSize::i32Bit>(OpcodeArgs);
@@ -341,7 +341,7 @@ template<IROps IROp, IR::OpSize ElementSize>
 void OpDispatchBuilder::AVXVectorScalarInsertALUOp(OpcodeArgs) {
   const auto DstSize = GetGuestVectorLength();
   auto Result = VectorScalarInsertALUOpImpl(Op, IROp, DstSize, ElementSize, Op->Src[0], Op->Src[1], true);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::AVXVectorScalarInsertALUOp<IR::OP_VFADDSCALARINSERT, OpSize::i32Bit>(OpcodeArgs);
@@ -377,7 +377,7 @@ template<IROps IROp, IR::OpSize ElementSize>
 void OpDispatchBuilder::VectorScalarUnaryInsertALUOp(OpcodeArgs) {
   const auto DstSize = GetGuestVectorLength();
   auto Result = VectorScalarInsertALUOpImpl(Op, IROp, DstSize, ElementSize, Op->Dest, Op->Src[0], false);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::VectorScalarUnaryInsertALUOp<IR::OP_VFSQRTSCALARINSERT, OpSize::i32Bit>(OpcodeArgs);
@@ -393,7 +393,7 @@ template<IROps IROp, IR::OpSize ElementSize>
 void OpDispatchBuilder::AVXVectorScalarUnaryInsertALUOp(OpcodeArgs) {
   const auto DstSize = GetGuestVectorLength();
   auto Result = VectorScalarInsertALUOpImpl(Op, IROp, DstSize, ElementSize, Op->Src[0], Op->Src[1], true);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::AVXVectorScalarUnaryInsertALUOp<IR::OP_VFSQRTSCALARINSERT, OpSize::i32Bit>(OpcodeArgs);
@@ -420,7 +420,7 @@ void OpDispatchBuilder::InsertMMX_To_XMM_Vector_CVT_Int_To_Float(OpcodeArgs) {
   // Always signed
   Dest = _VSToFVectorInsert(DstSize, ElementSize, ElementSize, Dest, Src, true, false);
 
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Dest, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Dest, DstSize);
 }
 
 Ref OpDispatchBuilder::InsertCVTGPR_To_FPRImpl(OpcodeArgs, IR::OpSize DstSize, IR::OpSize DstElementSize, const X86Tables::DecodedOperand& Src1Op,
@@ -455,7 +455,7 @@ template<IR::OpSize DstElementSize>
 void OpDispatchBuilder::InsertCVTGPR_To_FPR(OpcodeArgs) {
   const auto DstSize = GetGuestVectorLength();
   auto Result = InsertCVTGPR_To_FPRImpl(Op, DstSize, DstElementSize, Op->Dest, Op->Src[0], false);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::InsertCVTGPR_To_FPR<OpSize::i32Bit>(OpcodeArgs);
@@ -465,7 +465,7 @@ template<IR::OpSize DstElementSize>
 void OpDispatchBuilder::AVXInsertCVTGPR_To_FPR(OpcodeArgs) {
   const auto DstSize = GetGuestVectorLength();
   Ref Result = InsertCVTGPR_To_FPRImpl(Op, DstSize, DstElementSize, Op->Src[0], Op->Src[1], true);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 template void OpDispatchBuilder::AVXInsertCVTGPR_To_FPR<OpSize::i32Bit>(OpcodeArgs);
 template void OpDispatchBuilder::AVXInsertCVTGPR_To_FPR<OpSize::i64Bit>(OpcodeArgs);
@@ -489,7 +489,7 @@ template<IR::OpSize DstElementSize, IR::OpSize SrcElementSize>
 void OpDispatchBuilder::InsertScalar_CVT_Float_To_Float(OpcodeArgs) {
   const auto DstSize = GetGuestVectorLength();
   Ref Result = InsertScalar_CVT_Float_To_FloatImpl(Op, DstSize, DstElementSize, SrcElementSize, Op->Dest, Op->Src[0], false);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::InsertScalar_CVT_Float_To_Float<OpSize::i32Bit, OpSize::i64Bit>(OpcodeArgs);
@@ -499,7 +499,7 @@ template<IR::OpSize DstElementSize, IR::OpSize SrcElementSize>
 void OpDispatchBuilder::AVXInsertScalar_CVT_Float_To_Float(OpcodeArgs) {
   const auto DstSize = GetGuestVectorLength();
   Ref Result = InsertScalar_CVT_Float_To_FloatImpl(Op, DstSize, DstElementSize, SrcElementSize, Op->Src[0], Op->Src[1], true);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::AVXInsertScalar_CVT_Float_To_Float<OpSize::i32Bit, OpSize::i64Bit>(OpcodeArgs);
@@ -541,7 +541,7 @@ void OpDispatchBuilder::InsertScalarRound(OpcodeArgs) {
   const auto DstSize = GetGuestVectorLength();
 
   Ref Result = InsertScalarRoundImpl(Op, DstSize, ElementSize, Op->Dest, Op->Src[0], Mode, false);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::InsertScalarRound<OpSize::i32Bit>(OpcodeArgs);
@@ -553,7 +553,7 @@ void OpDispatchBuilder::AVXInsertScalarRound(OpcodeArgs) {
   const auto DstSize = GetGuestVectorLength();
 
   Ref Result = InsertScalarRoundImpl(Op, DstSize, ElementSize, Op->Dest, Op->Src[0], Mode, true);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::AVXInsertScalarRound<OpSize::i32Bit>(OpcodeArgs);
@@ -601,7 +601,7 @@ void OpDispatchBuilder::InsertScalarFCMPOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR_WithOpSize(Op, Op->Src[0], SrcSize, Op->Flags, {.AllowUpperGarbage = true});
 
   Ref Result = InsertScalarFCMPOpImpl(DstSize, OpSizeFromDst(Op), ElementSize, Src1, Src2, CompType, false);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::InsertScalarFCMPOp<OpSize::i32Bit>(OpcodeArgs);
@@ -620,7 +620,7 @@ void OpDispatchBuilder::AVXInsertScalarFCMPOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR_WithOpSize(Op, Op->Src[1], SrcSize, Op->Flags, {.AllowUpperGarbage = true});
 
   Ref Result = InsertScalarFCMPOpImpl(DstSize, OpSizeFromDst(Op), ElementSize, Src1, Src2, CompType, true);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::AVXInsertScalarFCMPOp<OpSize::i32Bit>(OpcodeArgs);
@@ -643,7 +643,7 @@ void OpDispatchBuilder::RSqrt3DNowOp(OpcodeArgs, bool Duplicate) {
     Result = _VDupElement(Size, ElementSize, Result, 0);
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VectorUnaryOp(OpcodeArgs, IROps IROp, IR::OpSize ElementSize) {
@@ -656,7 +656,7 @@ void OpDispatchBuilder::VectorUnaryOp(OpcodeArgs, IROps IROp, IR::OpSize Element
   Ref Src = LoadSourceFPR_WithOpSize(Op, Op->Src[0], Size, Op->Flags);
 
   DeriveOp(ALUOp, IROp, _VFSqrt(Size, ElementSize, Src));
-  StoreResultFPR(Op, ALUOp, OpSize::iInvalid);
+  StoreResultFPR(Op, ALUOp);
 }
 
 void OpDispatchBuilder::AVXVectorUnaryOp(OpcodeArgs, IROps IROp, IR::OpSize ElementSize) {
@@ -675,7 +675,7 @@ void OpDispatchBuilder::AVXVectorUnaryOp(OpcodeArgs, IROps IROp, IR::OpSize Elem
   //       which, on hardware with SVE, zero-extends as part of
   //       storing into the destination.
 
-  StoreResultFPR(Op, ALUOp, OpSize::iInvalid);
+  StoreResultFPR(Op, ALUOp);
 }
 
 void OpDispatchBuilder::VectorUnaryDuplicateOpImpl(OpcodeArgs, IROps IROp, IR::OpSize ElementSize) {
@@ -687,7 +687,7 @@ void OpDispatchBuilder::VectorUnaryDuplicateOpImpl(OpcodeArgs, IROps IROp, IR::O
 
   // Duplicate the lower bits
   auto Result = _VDupElement(Size, ElementSize, ALUOp, 0);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template<IROps IROp, IR::OpSize ElementSize>
@@ -710,7 +710,7 @@ void OpDispatchBuilder::MOVQOp(OpcodeArgs, VectorOpType VectorType) {
     StoreXMMRegister_WithAVXInsert(VectorType, gprIndex, Reg);
   } else {
     // This is simple, just store the result
-    StoreResultFPR(Op, Src, OpSize::iInvalid);
+    StoreResultFPR(Op, Src);
   }
 }
 
@@ -741,7 +741,7 @@ void OpDispatchBuilder::MOVMSKOp(OpcodeArgs, IR::OpSize ElementSize) {
     GPR = _Bfi(OpSize::i64Bit, 32, 31, GPR, GPR);
     // Shift right to only get the two sign bits we care about.
     GPR = _Lshr(OpSize::i64Bit, GPR, Constant(62));
-    StoreResultGPR_WithOpSize(Op, Op->Dest, GPR, GetGPROpSize(), OpSize::iInvalid);
+    StoreResultGPR_WithOpSize(Op, Op->Dest, GPR, GetGPROpSize());
   } else if (Size == OpSize::i128Bit && ElementSize == OpSize::i32Bit) {
     // Shift all the sign bits to the bottom of their respective elements.
     Src = _VUShrI(Size, OpSize::i32Bit, Src, 31);
@@ -753,7 +753,7 @@ void OpDispatchBuilder::MOVMSKOp(OpcodeArgs, IR::OpSize ElementSize) {
     Src = _VAddV(Size, OpSize::i32Bit, Src);
     // Extract to a GPR.
     Ref GPR = _VExtractToGPR(Size, OpSize::i32Bit, Src, 0);
-    StoreResultGPR_WithOpSize(Op, Op->Dest, GPR, GetGPROpSize(), OpSize::iInvalid);
+    StoreResultGPR_WithOpSize(Op, Op->Dest, GPR, GetGPROpSize());
   } else {
     Ref CurrentVal = Constant(0);
 
@@ -769,7 +769,7 @@ void OpDispatchBuilder::MOVMSKOp(OpcodeArgs, IR::OpSize ElementSize) {
         CurrentVal = Tmp;
       }
     }
-    StoreResultGPR(Op, CurrentVal, OpSize::iInvalid);
+    StoreResultGPR(Op, CurrentVal);
   }
 }
 
@@ -795,7 +795,7 @@ void OpDispatchBuilder::MOVMSKOpOne(OpcodeArgs) {
 
   auto Result = _VExtractToGPR(SrcSize, ExtractSize, VAdd3, 0);
 
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 }
 
 void OpDispatchBuilder::PUNPCKLOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -805,7 +805,7 @@ void OpDispatchBuilder::PUNPCKLOp(OpcodeArgs, IR::OpSize ElementSize) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   auto ALUOp = _VZip(Size, ElementSize, Dest, Src);
-  StoreResultFPR(Op, ALUOp, OpSize::iInvalid);
+  StoreResultFPR(Op, ALUOp);
 }
 
 void OpDispatchBuilder::VPUNPCKLOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -825,7 +825,7 @@ void OpDispatchBuilder::VPUNPCKLOp(OpcodeArgs, IR::OpSize ElementSize) {
     Result = _VInsElement(SrcSize, OpSize::i128Bit, 1, 0, ZipLo, ZipHi);
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PUNPCKHOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -834,7 +834,7 @@ void OpDispatchBuilder::PUNPCKHOp(OpcodeArgs, IR::OpSize ElementSize) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   auto ALUOp = _VZip2(Size, ElementSize, Dest, Src);
-  StoreResultFPR(Op, ALUOp, OpSize::iInvalid);
+  StoreResultFPR(Op, ALUOp);
 }
 
 void OpDispatchBuilder::VPUNPCKHOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -853,7 +853,7 @@ void OpDispatchBuilder::VPUNPCKHOp(OpcodeArgs, IR::OpSize ElementSize) {
     Result = _VInsElement(SrcSize, OpSize::i128Bit, 0, 1, ZipHi, ZipLo);
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::GeneratePSHUFBMask(IR::OpSize SrcSize) {
@@ -895,7 +895,7 @@ void OpDispatchBuilder::PSHUFBOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   Ref Result = PSHUFBOpImpl(SrcSize, Src1, Src2, GeneratePSHUFBMask(SrcSize));
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPSHUFBOp(OpcodeArgs) {
@@ -904,7 +904,7 @@ void OpDispatchBuilder::VPSHUFBOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
 
   Ref Result = PSHUFBOpImpl(SrcSize, Src1, Src2, GeneratePSHUFBMask(SrcSize));
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::PShufWLane(IR::OpSize Size, FEXCore::IR::IndexNamedVectorConstant IndexConstant, bool LowLane, Ref IncomingLane,
@@ -956,7 +956,7 @@ void OpDispatchBuilder::PSHUFW8ByteOp(OpcodeArgs) {
   const auto Size = OpSizeFromSrc(Op);
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Dest = PShufWLane(Size, FEXCore::IR::INDEXED_NAMED_VECTOR_PSHUFLW, true, Src, Shuffle);
-  StoreResultFPR(Op, Dest, OpSize::iInvalid);
+  StoreResultFPR(Op, Dest);
 }
 
 void OpDispatchBuilder::PSHUFWOp(OpcodeArgs, bool Low) {
@@ -968,7 +968,7 @@ void OpDispatchBuilder::PSHUFWOp(OpcodeArgs, bool Low) {
 
   Ref Dest = PShufWLane(Size, IndexedVectorConstant, Low, Src, Shuffle);
 
-  StoreResultFPR(Op, Dest, OpSize::iInvalid);
+  StoreResultFPR(Op, Dest);
 }
 
 Ref OpDispatchBuilder::Single128Bit4ByteVectorShuffle(Ref Src, uint8_t Shuffle) {
@@ -1200,7 +1200,7 @@ Ref OpDispatchBuilder::Single128Bit4ByteVectorShuffle(Ref Src, uint8_t Shuffle)
 void OpDispatchBuilder::PSHUFDOp(OpcodeArgs) {
   uint16_t Shuffle = Op->Src[1].Data.Literal.Value;
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
-  StoreResultFPR(Op, Single128Bit4ByteVectorShuffle(Src, Shuffle), OpSize::iInvalid);
+  StoreResultFPR(Op, Single128Bit4ByteVectorShuffle(Src, Shuffle));
 }
 
 void OpDispatchBuilder::VPSHUFWOp(OpcodeArgs, IR::OpSize ElementSize, bool Low) {
@@ -1249,7 +1249,7 @@ void OpDispatchBuilder::VPSHUFWOp(OpcodeArgs, IR::OpSize ElementSize, bool Low)
     }
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::SHUFOpImpl(OpcodeArgs, IR::OpSize DstSize, IR::OpSize ElementSize, Ref Src1, Ref Src2, uint8_t Shuffle) {
@@ -1449,7 +1449,7 @@ void OpDispatchBuilder::SHUFOp(OpcodeArgs, IR::OpSize ElementSize) {
   uint8_t Shuffle = Op->Src[1].Literal();
 
   Ref Result = SHUFOpImpl(Op, OpSizeFromDst(Op), ElementSize, Src1Node, Src2Node, Shuffle);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VSHUFOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -1458,7 +1458,7 @@ void OpDispatchBuilder::VSHUFOp(OpcodeArgs, IR::OpSize ElementSize) {
   uint8_t Shuffle = Op->Src[2].Literal();
 
   Ref Result = SHUFOpImpl(Op, OpSizeFromDst(Op), ElementSize, Src1Node, Src2Node, Shuffle);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VANDNOp(OpcodeArgs) {
@@ -1468,7 +1468,7 @@ void OpDispatchBuilder::VANDNOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
   Ref Dest = _VAndn(SrcSize, SrcSize, Src2, Src1);
 
-  StoreResultFPR(Op, Dest, OpSize::iInvalid);
+  StoreResultFPR(Op, Dest);
 }
 
 template<IROps IROp, IR::OpSize ElementSize>
@@ -1487,7 +1487,7 @@ void OpDispatchBuilder::VHADDPOp(OpcodeArgs) {
     Dest = _VInsElement(SrcSize, OpSize::i64Bit, 2, 1, Dest, Res);
   }
 
-  StoreResultFPR(Op, Dest, OpSize::iInvalid);
+  StoreResultFPR(Op, Dest);
 }
 
 template void OpDispatchBuilder::VHADDPOp<IR::OP_VADDP, OpSize::i16Bit>(OpcodeArgs);
@@ -1511,7 +1511,7 @@ void OpDispatchBuilder::VBROADCASTOp(OpcodeArgs, IR::OpSize ElementSize) {
   // No need to zero-extend result, since implementations
   // use zero extending AdvSIMD or zeroing SVE loads internally.
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::PINSROpImpl(OpcodeArgs, IR::OpSize ElementSize, const X86Tables::DecodedOperand& Src1Op,
@@ -1535,7 +1535,7 @@ Ref OpDispatchBuilder::PINSROpImpl(OpcodeArgs, IR::OpSize ElementSize, const X86
 template<IR::OpSize ElementSize>
 void OpDispatchBuilder::PINSROp(OpcodeArgs) {
   Ref Result = PINSROpImpl(Op, ElementSize, Op->Dest, Op->Src[0], Op->Src[1]);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::PINSROp<OpSize::i8Bit>(OpcodeArgs);
@@ -1548,7 +1548,7 @@ void OpDispatchBuilder::VPINSRBOp(OpcodeArgs) {
   if (Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPINSRDQOp(OpcodeArgs) {
@@ -1557,7 +1557,7 @@ void OpDispatchBuilder::VPINSRDQOp(OpcodeArgs) {
   if (Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPINSRWOp(OpcodeArgs) {
@@ -1565,7 +1565,7 @@ void OpDispatchBuilder::VPINSRWOp(OpcodeArgs) {
   if (Op->Dest.Data.GPR.GPR == Op->Src[0].Data.GPR.GPR) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::InsertPSOpImpl(OpcodeArgs, const X86Tables::DecodedOperand& Src1, const X86Tables::DecodedOperand& Src2,
@@ -1616,12 +1616,12 @@ Ref OpDispatchBuilder::InsertPSOpImpl(OpcodeArgs, const X86Tables::DecodedOperan
 
 void OpDispatchBuilder::InsertPSOp(OpcodeArgs) {
   Ref Result = InsertPSOpImpl(Op, Op->Dest, Op->Src[0], Op->Src[1]);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VINSERTPSOp(OpcodeArgs) {
   Ref Result = InsertPSOpImpl(Op, Op->Src[0], Op->Src[1], Op->Src[2]);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PExtrOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -1647,7 +1647,7 @@ void OpDispatchBuilder::PExtrOp(OpcodeArgs, IR::OpSize ElementSize) {
     const auto GPRSize = GetGPROpSize();
     // Extract already zero extends the result.
     Ref Result = _VExtractToGPR(OpSize::i128Bit, OverridenElementSize, Src, Index);
-    StoreResultGPR_WithOpSize(Op, Op->Dest, Result, GPRSize, OpSize::iInvalid);
+    StoreResultGPR_WithOpSize(Op, Op->Dest, Result, GPRSize);
     return;
   }
 
@@ -1666,7 +1666,7 @@ void OpDispatchBuilder::VEXTRACT128Op(OpcodeArgs) {
   // A selector of zero is the same as doing a 128-bit vector move.
   if (Selector == 0) {
     Ref Result = DstIsXMM ? _VMov(OpSize::i128Bit, Src) : Src;
-    StoreResultFPR_WithOpSize(Op, Op->Dest, Result, StoreSize, OpSize::iInvalid);
+    StoreResultFPR_WithOpSize(Op, Op->Dest, Result, StoreSize);
     return;
   }
 
@@ -1675,7 +1675,7 @@ void OpDispatchBuilder::VEXTRACT128Op(OpcodeArgs) {
   if (DstIsXMM) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, StoreSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, StoreSize);
 }
 
 Ref OpDispatchBuilder::PSIGNImpl(OpcodeArgs, IR::OpSize ElementSize, Ref Src1, Ref Src2) {
@@ -1692,7 +1692,7 @@ void OpDispatchBuilder::PSIGN(OpcodeArgs) {
   Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Res = PSIGNImpl(Op, ElementSize, Dest, Src);
 
-  StoreResultFPR(Op, Res, OpSize::iInvalid);
+  StoreResultFPR(Op, Res);
 }
 
 template void OpDispatchBuilder::PSIGN<OpSize::i8Bit>(OpcodeArgs);
@@ -1705,7 +1705,7 @@ void OpDispatchBuilder::VPSIGN(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
   Ref Res = PSIGNImpl(Op, ElementSize, Src1, Src2);
 
-  StoreResultFPR(Op, Res, OpSize::iInvalid);
+  StoreResultFPR(Op, Res);
 }
 
 template void OpDispatchBuilder::VPSIGN<OpSize::i8Bit>(OpcodeArgs);
@@ -1724,7 +1724,7 @@ void OpDispatchBuilder::PSRLDOp(OpcodeArgs, IR::OpSize ElementSize) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = PSRLDOpImpl(Op, ElementSize, Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPSRLDOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -1738,7 +1738,7 @@ void OpDispatchBuilder::VPSRLDOp(OpcodeArgs, IR::OpSize ElementSize) {
   if (Is128Bit) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PSRLI(OpcodeArgs, IR::OpSize ElementSize) {
@@ -1752,7 +1752,7 @@ void OpDispatchBuilder::PSRLI(OpcodeArgs, IR::OpSize ElementSize) {
 
   Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Shift = _VUShrI(Size, ElementSize, Dest, ShiftConstant);
-  StoreResultFPR(Op, Shift, OpSize::iInvalid);
+  StoreResultFPR(Op, Shift);
 }
 
 void OpDispatchBuilder::VPSRLIOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -1771,7 +1771,7 @@ void OpDispatchBuilder::VPSRLIOp(OpcodeArgs, IR::OpSize ElementSize) {
     }
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::PSLLIImpl(OpcodeArgs, IR::OpSize ElementSize, Ref Src, uint64_t Shift) {
@@ -1793,7 +1793,7 @@ void OpDispatchBuilder::PSLLI(OpcodeArgs, IR::OpSize ElementSize) {
   Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Result = PSLLIImpl(Op, ElementSize, Dest, ShiftConstant);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPSLLIOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -1807,7 +1807,7 @@ void OpDispatchBuilder::VPSLLIOp(OpcodeArgs, IR::OpSize ElementSize) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::PSLLImpl(OpcodeArgs, IR::OpSize ElementSize, Ref Src, Ref ShiftVec) {
@@ -1822,7 +1822,7 @@ void OpDispatchBuilder::PSLL(OpcodeArgs, IR::OpSize ElementSize) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = PSLLImpl(Op, ElementSize, Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPSLLOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -1836,7 +1836,7 @@ void OpDispatchBuilder::VPSLLOp(OpcodeArgs, IR::OpSize ElementSize) {
   if (Is128Bit) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::PSRAOpImpl(OpcodeArgs, IR::OpSize ElementSize, Ref Src, Ref ShiftVec) {
@@ -1851,7 +1851,7 @@ void OpDispatchBuilder::PSRAOp(OpcodeArgs, IR::OpSize ElementSize) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = PSRAOpImpl(Op, ElementSize, Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPSRAOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -1865,7 +1865,7 @@ void OpDispatchBuilder::VPSRAOp(OpcodeArgs, IR::OpSize ElementSize) {
   if (Is128Bit) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PSRLDQ(OpcodeArgs) {
@@ -1883,7 +1883,7 @@ void OpDispatchBuilder::PSRLDQ(OpcodeArgs) {
   if (Shift < IR::OpSizeToSize(Size)) {
     Result = _VExtr(Size, OpSize::i8Bit, Result, Dest, Shift);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPSRLDQOp(OpcodeArgs) {
@@ -1917,7 +1917,7 @@ void OpDispatchBuilder::VPSRLDQOp(OpcodeArgs) {
     }
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PSLLDQ(OpcodeArgs) {
@@ -1935,7 +1935,7 @@ void OpDispatchBuilder::PSLLDQ(OpcodeArgs) {
     Result = _VExtr(Size, OpSize::i8Bit, Dest, Result, IR::OpSizeToSize(Size) - Shift);
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPSLLDQOp(OpcodeArgs) {
@@ -1967,7 +1967,7 @@ void OpDispatchBuilder::VPSLLDQOp(OpcodeArgs) {
       }
     }
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PSRAIOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -1981,7 +1981,7 @@ void OpDispatchBuilder::PSRAIOp(OpcodeArgs, IR::OpSize ElementSize) {
 
   Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Result = _VSShrI(Size, ElementSize, Dest, Shift);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPSRAIOp(OpcodeArgs, IR::OpSize ElementSize) {
@@ -2000,7 +2000,7 @@ void OpDispatchBuilder::VPSRAIOp(OpcodeArgs, IR::OpSize ElementSize) {
     }
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::AVXVariableShiftImpl(OpcodeArgs, IROps IROp) {
@@ -2012,7 +2012,7 @@ void OpDispatchBuilder::AVXVariableShiftImpl(OpcodeArgs, IROps IROp) {
 
   DeriveOp(Shift, IROp, _VUShr(DstSize, SrcSize, Vector, ShiftVector, true));
 
-  StoreResultFPR(Op, Shift, OpSize::iInvalid);
+  StoreResultFPR(Op, Shift);
 }
 
 void OpDispatchBuilder::VPSLLVOp(OpcodeArgs) {
@@ -2035,7 +2035,7 @@ void OpDispatchBuilder::MOVDDUPOp(OpcodeArgs) {
   Ref Src = LoadSourceFPR_WithOpSize(Op, Op->Src[0], SrcSize, Op->Flags);
   Ref Res = _VDupElement(OpSize::i128Bit, OpSizeFromSrc(Op), Src, 0);
 
-  StoreResultFPR(Op, Res, OpSize::iInvalid);
+  StoreResultFPR(Op, Res);
 }
 
 void OpDispatchBuilder::VMOVDDUPOp(OpcodeArgs) {
@@ -2054,7 +2054,7 @@ void OpDispatchBuilder::VMOVDDUPOp(OpcodeArgs) {
     Res = _VDupElement(SrcSize, OpSize::i64Bit, Src, 0);
   }
 
-  StoreResultFPR(Op, Res, OpSize::iInvalid);
+  StoreResultFPR(Op, Res);
 }
 
 Ref OpDispatchBuilder::CVTGPR_To_FPRImpl(OpcodeArgs, IR::OpSize DstElementSize, const X86Tables::DecodedOperand& Src1Op,
@@ -2086,7 +2086,7 @@ Ref OpDispatchBuilder::CVTGPR_To_FPRImpl(OpcodeArgs, IR::OpSize DstElementSize,
 template<IR::OpSize DstElementSize>
 void OpDispatchBuilder::CVTGPR_To_FPR(OpcodeArgs) {
   Ref Result = CVTGPR_To_FPRImpl(Op, DstElementSize, Op->Dest, Op->Src[0]);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::CVTGPR_To_FPR<OpSize::i32Bit>(OpcodeArgs);
@@ -2095,7 +2095,7 @@ template void OpDispatchBuilder::CVTGPR_To_FPR<OpSize::i64Bit>(OpcodeArgs);
 template<IR::OpSize DstElementSize>
 void OpDispatchBuilder::AVXCVTGPR_To_FPR(OpcodeArgs) {
   Ref Result = CVTGPR_To_FPRImpl(Op, DstElementSize, Op->Src[0], Op->Src[1]);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 template void OpDispatchBuilder::AVXCVTGPR_To_FPR<OpSize::i32Bit>(OpcodeArgs);
 template void OpDispatchBuilder::AVXCVTGPR_To_FPR<OpSize::i64Bit>(OpcodeArgs);
@@ -2137,7 +2137,7 @@ void OpDispatchBuilder::CVTFPR_To_GPR(OpcodeArgs) {
   const auto SrcSize = Op->Src[0].IsGPR() ? OpSize::i128Bit : SrcElementSize;
   Ref Src = LoadSourceFPR_WithOpSize(Op, Op->Src[0], SrcSize, Op->Flags);
   Ref Result = CVTFPR_To_GPRImpl(Op, Src, SrcElementSize, HostRoundingMode);
-  StoreResultGPR(Op, Result, OpSize::iInvalid);
+  StoreResultGPR(Op, Result);
 }
 
 template void OpDispatchBuilder::CVTFPR_To_GPR<OpSize::i32Bit, true>(OpcodeArgs);
@@ -2173,7 +2173,7 @@ Ref OpDispatchBuilder::Vector_CVT_Int_To_FloatImpl(OpcodeArgs, IR::OpSize SrcEle
 template<IR::OpSize SrcElementSize, bool Widen>
 void OpDispatchBuilder::Vector_CVT_Int_To_Float(OpcodeArgs) {
   Ref Result = Vector_CVT_Int_To_FloatImpl(Op, SrcElementSize, Widen);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::Vector_CVT_Int_To_Float<OpSize::i32Bit, true>(OpcodeArgs);
@@ -2222,7 +2222,7 @@ void OpDispatchBuilder::Vector_CVT_Float_To_Int(OpcodeArgs) {
 
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = Vector_CVT_Float_To_Int32Impl(Op, DstSize, Src, OpSizeFromSrc(Op), SrcElementSize, HostRoundingMode, true);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::Vector_CVT_Float_To_Int<OpSize::i32Bit, false>(OpcodeArgs);
@@ -2249,7 +2249,7 @@ Ref OpDispatchBuilder::Scalar_CVT_Float_To_FloatImpl(OpcodeArgs, IR::OpSize DstE
 template<IR::OpSize DstElementSize, IR::OpSize SrcElementSize>
 void OpDispatchBuilder::Scalar_CVT_Float_To_Float(OpcodeArgs) {
   Ref Result = Scalar_CVT_Float_To_FloatImpl(Op, DstElementSize, SrcElementSize, Op->Dest, Op->Src[0]);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::Scalar_CVT_Float_To_Float<OpSize::i32Bit, OpSize::i64Bit>(OpcodeArgs);
@@ -2258,7 +2258,7 @@ template void OpDispatchBuilder::Scalar_CVT_Float_To_Float<OpSize::i64Bit, OpSiz
 template<IR::OpSize DstElementSize, IR::OpSize SrcElementSize>
 void OpDispatchBuilder::AVXScalar_CVT_Float_To_Float(OpcodeArgs) {
   Ref Result = Scalar_CVT_Float_To_FloatImpl(Op, DstElementSize, SrcElementSize, Op->Src[0], Op->Src[1]);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::AVXScalar_CVT_Float_To_Float<OpSize::i32Bit, OpSize::i64Bit>(OpcodeArgs);
@@ -2290,7 +2290,7 @@ void OpDispatchBuilder::Vector_CVT_Float_To_Float(OpcodeArgs, IR::OpSize DstElem
       Result = _VMov(OpSize::i128Bit, Result);
     }
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::MMX_To_XMM_Vector_CVT_Int_To_Float(OpcodeArgs) {
@@ -2306,7 +2306,7 @@ void OpDispatchBuilder::MMX_To_XMM_Vector_CVT_Int_To_Float(OpcodeArgs) {
   // Always signed
   Src = _Vector_SToF(DstSize, ElementSize, Src);
 
-  StoreResultFPR(Op, Src, OpSize::iInvalid);
+  StoreResultFPR(Op, Src);
 }
 
 template<IR::OpSize SrcElementSize, bool HostRoundingMode>
@@ -2323,7 +2323,7 @@ void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int(OpcodeArgs) {
   const auto DstSize = OpSizeFromDst(Op);
   Ref Src = LoadSourceFPR_WithOpSize(Op, Op->Src[0], SrcSize, Op->Flags);
   Ref Result = Vector_CVT_Float_To_Int32Impl(Op, DstSize, Src, SrcSize, SrcElementSize, HostRoundingMode, false /* TODO? */);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, DstSize);
 }
 
 template void OpDispatchBuilder::XMM_To_MMX_Vector_CVT_Float_To_Int<OpSize::i32Bit, false>(OpcodeArgs);
@@ -2373,7 +2373,7 @@ void OpDispatchBuilder::VMASKMOVOpImpl(OpcodeArgs, IR::OpSize ElementSize, IR::O
     if (Is128Bit) {
       Result = _VMov(OpSize::i128Bit, Result);
     }
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
   }
 }
 
@@ -2406,7 +2406,7 @@ void OpDispatchBuilder::MOVBetweenGPR_FPR(OpcodeArgs, VectorOpType VectorType) {
       Result = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
     }
 
-    StoreResult_WithAVXInsert(VectorType, RegClass::FPR, Op, Result, OpSize::iInvalid);
+    StoreResult_WithAVXInsert(VectorType, RegClass::FPR, Op, Result);
   } else {
     Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
@@ -2414,7 +2414,7 @@ void OpDispatchBuilder::MOVBetweenGPR_FPR(OpcodeArgs, VectorOpType VectorType) {
       const auto ElementSize = OpSizeFromDst(Op);
       // Extract element from GPR. Zero extending in the process.
       Src = _VExtractToGPR(OpSizeFromSrc(Op), ElementSize, Src, 0);
-      StoreResultGPR(Op, Op->Dest, Src, OpSize::iInvalid);
+      StoreResultGPR(Op, Op->Dest, Src);
     } else {
       // Storing first element to memory.
       Ref Dest = LoadSourceGPR(Op, Op->Dest, Op->Flags, {.LoadData = false});
@@ -2461,7 +2461,7 @@ void OpDispatchBuilder::VFCMPOp(OpcodeArgs) {
 
   Ref Result = VFCMPOpImpl(OpSizeFromSrc(Op), ElementSize, Dest, Src, CompType);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::VFCMPOp<OpSize::i32Bit>(OpcodeArgs);
@@ -2479,7 +2479,7 @@ void OpDispatchBuilder::AVXVFCMPOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR_WithOpSize(Op, Op->Src[1], SrcSize, Op->Flags);
   Ref Result = VFCMPOpImpl(OpSizeFromSrc(Op), ElementSize, Src1, Src2, CompType);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::AVXVFCMPOp<OpSize::i32Bit>(OpcodeArgs);
@@ -2879,12 +2879,12 @@ Ref OpDispatchBuilder::PALIGNROpImpl(OpcodeArgs, const X86Tables::DecodedOperand
 
 void OpDispatchBuilder::PAlignrOp(OpcodeArgs) {
   Ref Result = PALIGNROpImpl(Op, Op->Dest, Op->Src[0], Op->Src[1], false);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPALIGNROp(OpcodeArgs) {
   Ref Result = PALIGNROpImpl(Op, Op->Src[0], Op->Src[1], Op->Src[2], true);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template<IR::OpSize ElementSize>
@@ -2905,7 +2905,7 @@ void OpDispatchBuilder::LDMXCSR(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::STMXCSR(OpcodeArgs) {
-  StoreResultGPR_WithOpSize(Op, Op->Dest, GetMXCSR(), OpSize::i32Bit, OpSize::iInvalid);
+  StoreResultGPR_WithOpSize(Op, Op->Dest, GetMXCSR(), OpSize::i32Bit);
 }
 
 template<IR::OpSize ElementSize>
@@ -2914,7 +2914,7 @@ void OpDispatchBuilder::PACKUSOp(OpcodeArgs) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = _VSQXTUNPair(OpSizeFromSrc(Op), ElementSize, Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::PACKUSOp<OpSize::i16Bit>(OpcodeArgs);
@@ -2933,7 +2933,7 @@ void OpDispatchBuilder::VPACKUSOp(OpcodeArgs, IR::OpSize ElementSize) {
     Ref Swapped = _VInsElement(DstSize, OpSize::i64Bit, 2, 1, Result, Result);
     Result = _VInsElement(DstSize, OpSize::i64Bit, 1, 2, Swapped, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template<IR::OpSize ElementSize>
@@ -2942,7 +2942,7 @@ void OpDispatchBuilder::PACKSSOp(OpcodeArgs) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = _VSQXTNPair(OpSizeFromSrc(Op), ElementSize, Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::PACKSSOp<OpSize::i16Bit>(OpcodeArgs);
@@ -2961,7 +2961,7 @@ void OpDispatchBuilder::VPACKSSOp(OpcodeArgs, IR::OpSize ElementSize) {
     Ref Swapped = _VInsElement(DstSize, OpSize::i64Bit, 2, 1, Result, Result);
     Result = _VInsElement(DstSize, OpSize::i64Bit, 1, 2, Swapped, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::PMULLOpImpl(OpSize Size, IR::OpSize ElementSize, bool Signed, Ref Src1, Ref Src2) {
@@ -2991,7 +2991,7 @@ void OpDispatchBuilder::PMULLOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Res = PMULLOpImpl(OpSizeFromSrc(Op), ElementSize, Signed, Src1, Src2);
 
-  StoreResultFPR(Op, Res, OpSize::iInvalid);
+  StoreResultFPR(Op, Res);
 }
 
 template void OpDispatchBuilder::PMULLOp<OpSize::i32Bit, false>(OpcodeArgs);
@@ -3005,7 +3005,7 @@ void OpDispatchBuilder::VPMULLOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
   Ref Result = PMULLOpImpl(OpSizeFromSrc(Op), ElementSize, Signed, Src1, Src2);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::VPMULLOp<OpSize::i32Bit, false>(OpcodeArgs);
@@ -3023,7 +3023,7 @@ void OpDispatchBuilder::MOVQ2DQ(OpcodeArgs) {
     StoreXMMRegister(Index, Src);
   } else {
     // This is simple, just store the result
-    StoreResultFPR(Op, Src, OpSize::iInvalid);
+    StoreResultFPR(Op, Src);
   }
 }
 
@@ -3053,7 +3053,7 @@ void OpDispatchBuilder::ADDSUBPOp(OpcodeArgs) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = ADDSUBPOpImpl(OpSizeFromSrc(Op), ElementSize, Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::ADDSUBPOp<OpSize::i32Bit>(OpcodeArgs);
@@ -3065,7 +3065,7 @@ void OpDispatchBuilder::VADDSUBPOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
   Ref Result = ADDSUBPOpImpl(OpSizeFromSrc(Op), ElementSize, Src1, Src2);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::VADDSUBPOp<OpSize::i32Bit>(OpcodeArgs);
@@ -3081,7 +3081,7 @@ void OpDispatchBuilder::PFNACCOp(OpcodeArgs) {
   auto SrcUnzip = _VUnZip2(Size, OpSize::i32Bit, Dest, Src);
   auto Result = _VFSub(Size, OpSize::i32Bit, DestUnzip, SrcUnzip);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PFPNACCOp(OpcodeArgs) {
@@ -3099,7 +3099,7 @@ void OpDispatchBuilder::PFPNACCOp(OpcodeArgs) {
 
   auto Result = _VInsElement(OpSize::i64Bit, OpSize::i32Bit, 1, 0, ResSub, ResAdd);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PSWAPDOp(OpcodeArgs) {
@@ -3107,7 +3107,7 @@ void OpDispatchBuilder::PSWAPDOp(OpcodeArgs) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   auto Result = _VRev64(Size, OpSize::i32Bit, Src);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PI2FWOp(OpcodeArgs) {
@@ -3125,7 +3125,7 @@ void OpDispatchBuilder::PI2FWOp(OpcodeArgs) {
   // int32_t to float
   Src = _Vector_SToF(Size, OpSize::i32Bit, Src);
 
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Src, Size, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Src, Size);
 }
 
 void OpDispatchBuilder::PF2IWOp(OpcodeArgs) {
@@ -3142,7 +3142,7 @@ void OpDispatchBuilder::PF2IWOp(OpcodeArgs) {
 
   // Now we need to sign extend the 16bit value to 32-bit
   Src = _VSXTL(Size, OpSize::i16Bit, Src);
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Src, Size, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Src, Size);
 }
 
 void OpDispatchBuilder::PMULHRWOp(OpcodeArgs) {
@@ -3165,7 +3165,7 @@ void OpDispatchBuilder::PMULHRWOp(OpcodeArgs) {
   // Now shift and narrow to convert 32-bit values to 16bit, storing the top 16bits
   Res = _VUShrNI(Size << 1, OpSize::i32Bit, Res, 16);
 
-  StoreResultFPR(Op, Res, OpSize::iInvalid);
+  StoreResultFPR(Op, Res);
 }
 
 template<uint8_t CompType>
@@ -3190,7 +3190,7 @@ void OpDispatchBuilder::VPFCMPOp(OpcodeArgs) {
   default: LOGMAN_MSG_A_FMT("Unknown Comparison type: {}", CompType); break;
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::VPFCMPOp<0>(OpcodeArgs);
@@ -3227,7 +3227,7 @@ void OpDispatchBuilder::PMADDWD(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   Ref Result = PMADDWDOpImpl(Size, Src1, Src2);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPMADDWDOp(OpcodeArgs) {
@@ -3237,7 +3237,7 @@ void OpDispatchBuilder::VPMADDWDOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
 
   Ref Result = PMADDWDOpImpl(Size, Src1, Src2);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::PMADDUBSWOpImpl(IR::OpSize Size, Ref Src1, Ref Src2) {
@@ -3289,7 +3289,7 @@ void OpDispatchBuilder::PMADDUBSW(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   Ref Result = PMADDUBSWOpImpl(Size, Src1, Src2);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPMADDUBSWOp(OpcodeArgs) {
@@ -3299,7 +3299,7 @@ void OpDispatchBuilder::VPMADDUBSWOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
 
   Ref Result = PMADDUBSWOpImpl(Size, Src1, Src2);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::PMULHWOpImpl(OpcodeArgs, bool Signed, Ref Src1, Ref Src2) {
@@ -3317,7 +3317,7 @@ void OpDispatchBuilder::PMULHW(OpcodeArgs) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = PMULHWOpImpl(Op, Signed, Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::PMULHW<false>(OpcodeArgs);
@@ -3335,7 +3335,7 @@ void OpDispatchBuilder::VPMULHWOp(OpcodeArgs) {
   if (Is128Bit) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::VPMULHWOp<false>(OpcodeArgs);
@@ -3376,7 +3376,7 @@ void OpDispatchBuilder::PMULHRSW(OpcodeArgs) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = PMULHRSWOpImpl(OpSizeFromSrc(Op), Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPMULHRSWOp(OpcodeArgs) {
@@ -3384,7 +3384,7 @@ void OpDispatchBuilder::VPMULHRSWOp(OpcodeArgs) {
   Ref Src = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
   Ref Result = PMULHRSWOpImpl(OpSizeFromSrc(Op), Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::HSUBPOpImpl(OpSize SrcSize, IR::OpSize ElementSize, Ref Src1, Ref Src2) {
@@ -3398,7 +3398,7 @@ void OpDispatchBuilder::HSUBP(OpcodeArgs) {
   Ref Src1 = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Src2 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = HSUBPOpImpl(OpSizeFromSrc(Op), ElementSize, Src1, Src2);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::HSUBP<OpSize::i32Bit>(OpcodeArgs);
@@ -3418,7 +3418,7 @@ void OpDispatchBuilder::VHSUBPOp(OpcodeArgs, IR::OpSize ElementSize) {
     Dest = _VInsElement(DstSize, OpSize::i64Bit, 2, 1, Dest, Result);
   }
 
-  StoreResultFPR(Op, Dest, OpSize::iInvalid);
+  StoreResultFPR(Op, Dest);
 }
 
 Ref OpDispatchBuilder::PHSUBOpImpl(OpSize Size, Ref Src1, Ref Src2, IR::OpSize ElementSize) {
@@ -3432,7 +3432,7 @@ void OpDispatchBuilder::PHSUB(OpcodeArgs) {
   Ref Src1 = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Src2 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = PHSUBOpImpl(OpSizeFromSrc(Op), Src1, Src2, ElementSize);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::PHSUB<OpSize::i16Bit>(OpcodeArgs);
@@ -3449,7 +3449,7 @@ void OpDispatchBuilder::VPHSUBOp(OpcodeArgs, IR::OpSize ElementSize) {
     Ref Inserted = _VInsElement(DstSize, OpSize::i64Bit, 1, 2, Result, Result);
     Result = _VInsElement(DstSize, OpSize::i64Bit, 2, 1, Inserted, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::PHADDSOpImpl(OpSize Size, Ref Src1, Ref Src2) {
@@ -3467,7 +3467,7 @@ void OpDispatchBuilder::PHADDS(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   Ref Result = PHADDSOpImpl(OpSizeFromSrc(Op), Src1, Src2);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPHADDSWOp(OpcodeArgs) {
@@ -3485,7 +3485,7 @@ void OpDispatchBuilder::VPHADDSWOp(OpcodeArgs) {
     Dest = _VInsElement(SrcSize, OpSize::i64Bit, 2, 1, Dest, Result);
   }
 
-  StoreResultFPR(Op, Dest, OpSize::iInvalid);
+  StoreResultFPR(Op, Dest);
 }
 
 Ref OpDispatchBuilder::PHSUBSOpImpl(OpSize Size, Ref Src1, Ref Src2) {
@@ -3502,7 +3502,7 @@ void OpDispatchBuilder::PHSUBS(OpcodeArgs) {
   Ref Src1 = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Src2 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Ref Result = PHSUBSOpImpl(OpSizeFromSrc(Op), Src1, Src2);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPHSUBSWOp(OpcodeArgs) {
@@ -3519,7 +3519,7 @@ void OpDispatchBuilder::VPHSUBSWOp(OpcodeArgs) {
     Dest = _VInsElement(DstSize, OpSize::i64Bit, 2, 1, Dest, Result);
   }
 
-  StoreResultFPR(Op, Dest, OpSize::iInvalid);
+  StoreResultFPR(Op, Dest);
 }
 
 Ref OpDispatchBuilder::PSADBWOpImpl(IR::OpSize Size, Ref Src1, Ref Src2) {
@@ -3568,7 +3568,7 @@ void OpDispatchBuilder::PSADBW(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   Ref Result = PSADBWOpImpl(Size, Src1, Src2);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPSADBWOp(OpcodeArgs) {
@@ -3578,7 +3578,7 @@ void OpDispatchBuilder::VPSADBWOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
 
   Ref Result = PSADBWOpImpl(Size, Src1, Src2);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::ExtendVectorElementsImpl(OpcodeArgs, IR::OpSize ElementSize, IR::OpSize DstElementSize, bool Signed) {
@@ -3614,7 +3614,7 @@ Ref OpDispatchBuilder::ExtendVectorElementsImpl(OpcodeArgs, IR::OpSize ElementSi
 template<IR::OpSize ElementSize, IR::OpSize DstElementSize, bool Signed>
 void OpDispatchBuilder::ExtendVectorElements(OpcodeArgs) {
   Ref Result = ExtendVectorElementsImpl(Op, ElementSize, DstElementSize, Signed);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::ExtendVectorElements<OpSize::i8Bit, OpSize::i16Bit, false>(OpcodeArgs);
@@ -3645,7 +3645,7 @@ void OpDispatchBuilder::VectorRound(OpcodeArgs) {
   const uint64_t Mode = Op->Src[1].Literal();
   Src = VectorRoundImpl(OpSizeFromDst(Op), ElementSize, Src, Mode);
 
-  StoreResultFPR(Op, Src, OpSize::iInvalid);
+  StoreResultFPR(Op, Src);
 }
 
 template void OpDispatchBuilder::VectorRound<OpSize::i32Bit>(OpcodeArgs);
@@ -3662,7 +3662,7 @@ void OpDispatchBuilder::AVXVectorRound(OpcodeArgs) {
   Ref Src = LoadSourceFPR_WithOpSize(Op, Op->Src[0], SrcSize, Op->Flags);
   Ref Result = VectorRoundImpl(OpSizeFromDst(Op), ElementSize, Src, Mode);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::AVXVectorRound<OpSize::i32Bit>(OpcodeArgs);
@@ -3911,7 +3911,7 @@ void OpDispatchBuilder::VectorBlend(OpcodeArgs) {
   Ref Dest = LoadSourceFPR(Op, Op->Dest, Op->Flags);
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
   Dest = VectorBlend(OpSize::i128Bit, ElementSize, Dest, Src, Select);
-  StoreResultFPR(Op, Dest, OpSize::iInvalid);
+  StoreResultFPR(Op, Dest);
 }
 
 template void OpDispatchBuilder::VectorBlend<OpSize::i16Bit>(OpcodeArgs);
@@ -3935,7 +3935,7 @@ void OpDispatchBuilder::VectorVariableBlend(OpcodeArgs, IR::OpSize ElementSize)
 
   auto Result = _VBSL(Size, Mask, Src, Dest);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::AVXVectorVariableBlend(OpcodeArgs, IR::OpSize ElementSize) {
@@ -3951,7 +3951,7 @@ void OpDispatchBuilder::AVXVectorVariableBlend(OpcodeArgs, IR::OpSize ElementSiz
 
   Ref Shifted = _VSShrI(SrcSize, ElementSize, Mask, ElementSizeBits - 1);
   Ref Result = _VBSL(SrcSize, Shifted, Src2, Src1);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::PTestOpImpl(OpSize Size, Ref Dest, Ref Src) {
@@ -4061,7 +4061,7 @@ Ref OpDispatchBuilder::PHMINPOSUWOpImpl(OpcodeArgs) {
 
 void OpDispatchBuilder::PHMINPOSUWOp(OpcodeArgs) {
   Ref Result = PHMINPOSUWOpImpl(Op);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::DPPOpImpl(IR::OpSize DstSize, Ref Src1, Ref Src2, uint8_t Mask, IR::OpSize ElementSize) {
@@ -4247,7 +4247,7 @@ void OpDispatchBuilder::DPPOp(OpcodeArgs) {
   Ref Src = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   Ref Result = DPPOpImpl(OpSizeFromDst(Op), Dest, Src, Op->Src[1].Literal(), ElementSize);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::DPPOp<OpSize::i32Bit>(OpcodeArgs);
@@ -4320,7 +4320,7 @@ void OpDispatchBuilder::VDPPOp(OpcodeArgs) {
 
   // We don't need to emit a _VMov to clear the upper lane, since DPPOpImpl uses a zero vector
   // to construct the results, so the upper lane will always be cleared for the 128-bit version.
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::VDPPOp<OpSize::i32Bit>(OpcodeArgs);
@@ -4420,7 +4420,7 @@ void OpDispatchBuilder::MPSADBWOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[0], Op->Flags);
 
   Ref Result = MPSADBWOpImpl(SrcSize, Src1, Src2, Select);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VMPSADBWOp(OpcodeArgs) {
@@ -4430,7 +4430,7 @@ void OpDispatchBuilder::VMPSADBWOp(OpcodeArgs) {
   Ref Src2 = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
 
   Ref Result = MPSADBWOpImpl(SrcSize, Src1, Src2, Select);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VINSERTOp(OpcodeArgs) {
@@ -4441,7 +4441,7 @@ void OpDispatchBuilder::VINSERTOp(OpcodeArgs) {
   const auto Selector = Op->Src[2].Literal() & 1;
   Ref Result = _VInsElement(DstSize, OpSize::i128Bit, Selector, 0, Src1, Src2);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VCVTPH2PSOp(OpcodeArgs) {
@@ -4454,7 +4454,7 @@ void OpDispatchBuilder::VCVTPH2PSOp(OpcodeArgs) {
   Ref Src = LoadSourceFPR_WithOpSize(Op, Op->Src[0], SrcLoadSize, Op->Flags);
   Ref Result = _Vector_FToF(DstSize, OpSize::i32Bit, Src, OpSize::i16Bit);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VCVTPS2PHOp(OpcodeArgs) {
@@ -4487,7 +4487,7 @@ void OpDispatchBuilder::VCVTPS2PHOp(OpcodeArgs) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
 
-  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, StoreSize, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Dest, Result, StoreSize);
 }
 
 void OpDispatchBuilder::VPERM2Op(OpcodeArgs) {
@@ -4515,7 +4515,7 @@ void OpDispatchBuilder::VPERM2Op(OpcodeArgs) {
     Result = SelectElement(1, (Selector >> 4) & 0b11);
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::VPERMDIndices(OpSize DstSize, Ref Indices, Ref IndexMask, Ref Repeating3210) {
@@ -4596,7 +4596,7 @@ void OpDispatchBuilder::VPERMDOp(OpcodeArgs) {
   // Now lets finally shuffle this bad boy around.
   Ref Result = _VTBL1(DstSize, Src, FinalIndices);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPERMQOp(OpcodeArgs) {
@@ -4618,7 +4618,7 @@ void OpDispatchBuilder::VPERMQOp(OpcodeArgs) {
       Result = _VInsElement(DstSize, OpSize::i64Bit, i, SrcIndex, Result, Src);
     }
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::VBLENDOpImpl(IR::OpSize VecSize, IR::OpSize ElementSize, Ref Src1, Ref Src2, Ref ZeroRegister, uint64_t Selector) {
@@ -4645,19 +4645,19 @@ void OpDispatchBuilder::VBLENDPDOp(OpcodeArgs) {
 
   if (Selector == 0) {
     Ref Result = Is256Bit ? Src1 : _VMov(OpSize::i128Bit, Src1);
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
     return;
   }
   // Only the first four bits of the 8-bit immediate are used, so only check them.
   if (((Selector & 0b11) == 0b11 && !Is256Bit) || (Selector & 0b1111) == 0b1111) {
     Ref Result = Is256Bit ? Src2 : _VMov(OpSize::i128Bit, Src2);
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
     return;
   }
 
   const auto ZeroRegister = LoadZeroVector(DstSize);
   Ref Result = VBLENDOpImpl(DstSize, OpSize::i64Bit, Src1, Src2, ZeroRegister, Selector);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPBLENDDOp(OpcodeArgs) {
@@ -4679,11 +4679,11 @@ void OpDispatchBuilder::VPBLENDDOp(OpcodeArgs) {
 
   if (Selector == 0) {
     Ref Result = Is256Bit ? Src1 : _VMov(OpSize::i128Bit, Src1);
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
     return;
   }
   if (Selector == 0xFF && Is256Bit) {
-    StoreResultFPR(Op, Src2, OpSize::iInvalid);
+    StoreResultFPR(Op, Src2);
     return;
   }
   // The only bits we care about from the 8-bit immediate for 128-bit operations
@@ -4691,7 +4691,7 @@ void OpDispatchBuilder::VPBLENDDOp(OpcodeArgs) {
   // silliness is going on and the upper bits are being set even when they'll
   // be ignored
   if ((Selector & 0xF) == 0xF && !Is256Bit) {
-    StoreResultFPR(Op, _VMov(OpSize::i128Bit, Src2), OpSize::iInvalid);
+    StoreResultFPR(Op, _VMov(OpSize::i128Bit, Src2));
     return;
   }
 
@@ -4700,7 +4700,7 @@ void OpDispatchBuilder::VPBLENDDOp(OpcodeArgs) {
   if (!Is256Bit) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VPBLENDWOp(OpcodeArgs) {
@@ -4713,12 +4713,12 @@ void OpDispatchBuilder::VPBLENDWOp(OpcodeArgs) {
 
   if (Selector == 0) {
     Ref Result = Is128Bit ? _VMov(OpSize::i128Bit, Src1) : Src1;
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
     return;
   }
   if (Selector == 0xFF) {
     Ref Result = Is128Bit ? _VMov(OpSize::i128Bit, Src2) : Src2;
-    StoreResultFPR(Op, Result, OpSize::iInvalid);
+    StoreResultFPR(Op, Result);
     return;
   }
 
@@ -4732,7 +4732,7 @@ void OpDispatchBuilder::VPBLENDWOp(OpcodeArgs) {
   if (Is128Bit) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VZEROOp(OpcodeArgs) {
@@ -4790,7 +4790,7 @@ void OpDispatchBuilder::VPERMILImmOp(OpcodeArgs, IR::OpSize ElementSize) {
     }
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 Ref OpDispatchBuilder::VPERMILRegOpImpl(OpSize DstSize, IR::OpSize ElementSize, Ref Src, Ref Indices) {
@@ -4846,7 +4846,7 @@ void OpDispatchBuilder::VPERMILRegOp(OpcodeArgs) {
   Ref Indices = LoadSourceFPR(Op, Op->Src[1], Op->Flags);
 
   Ref Result = VPERMILRegOpImpl(OpSizeFromDst(Op), ElementSize, Src, Indices);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 template void OpDispatchBuilder::VPERMILRegOp<OpSize::i32Bit>(OpcodeArgs);
@@ -4978,7 +4978,7 @@ void OpDispatchBuilder::VFMAImpl(OpcodeArgs, IROps IROp, bool Scalar, uint8_t Sr
   if (!Is256Bit) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::VFMAddSubImpl(OpcodeArgs, bool AddSub, uint8_t Src1Idx, uint8_t Src2Idx, uint8_t AddendIdx) {
@@ -5012,7 +5012,7 @@ void OpDispatchBuilder::VFMAddSubImpl(OpcodeArgs, bool AddSub, uint8_t Src1Idx,
   if (!Is256Bit) {
     Result = _VMov(OpSize::i128Bit, Result);
   }
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 OpDispatchBuilder::RefVSIB OpDispatchBuilder::LoadVSIB(const X86Tables::DecodedOp& Op, const X86Tables::DecodedOperand& Operand, uint32_t Flags) {
@@ -5122,11 +5122,11 @@ void OpDispatchBuilder::VPGATHER(OpcodeArgs) {
     }
   }
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 
   ///< Assume non-faulting behaviour and clear the mask register.
   auto Zero = LoadZeroVector(Size);
-  StoreResultFPR_WithOpSize(Op, Op->Src[1], Zero, Size, OpSize::iInvalid);
+  StoreResultFPR_WithOpSize(Op, Op->Src[1], Zero, Size);
 }
 
 template void OpDispatchBuilder::VPGATHER<OpSize::i32Bit>(OpcodeArgs);
@@ -5146,7 +5146,7 @@ void OpDispatchBuilder::Extrq_imm(OpcodeArgs) {
   const Ref MaskVector = _VCastFromGPR(OpSize::i128Bit, OpSize::i64Bit, _Constant(Mask));
   Result = _VAnd(OpSize::i128Bit, OpSize::i64Bit, Result, MaskVector);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::Insertq_imm(OpcodeArgs) {
@@ -5174,7 +5174,7 @@ void OpDispatchBuilder::Insertq_imm(OpcodeArgs) {
   Dest = _VAnd(OpSize::i64Bit, OpSize::i64Bit, Dest, MaskVector);
   const Ref Result = _VOr(OpSize::i64Bit, OpSize::i64Bit, Dest, Src);
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::Extrq(OpcodeArgs) {
@@ -5199,7 +5199,7 @@ void OpDispatchBuilder::Extrq(OpcodeArgs) {
 
   Result = _VAnd(OpSize::i128Bit, OpSize::i64Bit, Result, GenerateMask(MaskWidthBits));
 
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 void OpDispatchBuilder::Insertq(OpcodeArgs) {
@@ -5231,7 +5231,7 @@ void OpDispatchBuilder::Insertq(OpcodeArgs) {
 
   Ref Result = _VAnd(OpSize::i64Bit, OpSize::i64Bit, Dest, DstMask);
   Result = _VOr(OpSize::i64Bit, OpSize::i64Bit, Result, SrcData);
-  StoreResultFPR(Op, Result, OpSize::iInvalid);
+  StoreResultFPR(Op, Result);
 }
 
 } // namespace FEXCore::IR
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
index c7cf987f4..657f86ffb 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp
@@ -602,7 +602,7 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) {
 // Load / Store Control Word
 void OpDispatchBuilder::X87FSTCW(OpcodeArgs) {
   auto FCW = _LoadContextGPR(OpSize::i16Bit, offsetof(FEXCore::Core::CPUState, FCW));
-  StoreResultGPR(Op, FCW, OpSize::iInvalid);
+  StoreResultGPR(Op, FCW);
 }
 
 void OpDispatchBuilder::X87FLDCW(OpcodeArgs) {
@@ -766,7 +766,7 @@ Ref OpDispatchBuilder::ReconstructFSW_Helper(Ref T) {
 void OpDispatchBuilder::X87FNSTSW(OpcodeArgs) {
   Ref TopValue = _SyncStackToSlow();
   Ref StatusWord = ReconstructFSW_Helper(TopValue);
-  StoreResultGPR(Op, StatusWord, OpSize::iInvalid);
+  StoreResultGPR(Op, StatusWord);
 }
 
 void OpDispatchBuilder::FNCLEX(OpcodeArgs) {