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IR: Change StoreContext to use IR::OpSize
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@@ -507,8 +507,8 @@ void OpDispatchBuilder::POPAOp(OpcodeArgs) {
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}
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void OpDispatchBuilder::POPSegmentOp(OpcodeArgs, uint32_t SegmentReg) {
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const uint8_t SrcSize = GetSrcSize(Op);
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const uint8_t DstSize = GetDstSize(Op);
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const auto SrcSize = OpSizeFromSrc(Op);
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const auto DstSize = OpSizeFromDst(Op);
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auto NewSegment = Pop(SrcSize);
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@@ -2946,7 +2946,7 @@ void OpDispatchBuilder::ReadSegmentReg(OpcodeArgs, OpDispatchBuilder::Segment Se
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void OpDispatchBuilder::WriteSegmentReg(OpcodeArgs, OpDispatchBuilder::Segment Seg) {
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// Documentation claims that the 32-bit version of this instruction inserts in to the lower 32-bits of the segment
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// This is incorrect and it instead zero extends the 32-bit value to 64-bit
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auto Size = GetDstSize(Op);
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const auto Size = OpSizeFromDst(Op);
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Ref Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags);
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if (Seg == Segment::FS) {
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_StoreContext(Size, GPRClass, Src, offsetof(FEXCore::Core::CPUState, fs_cached));
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@@ -4686,7 +4686,7 @@ void OpDispatchBuilder::INTOp(OpcodeArgs) {
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// Calculate flags early.
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FlushRegisterCache();
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const uint8_t GPRSize = CTX->GetGPRSize();
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const auto GPRSize = CTX->GetGPROpSize();
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if (SetRIPToNext) {
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BlockSetRIP = SetRIPToNext;
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@@ -4876,7 +4876,7 @@ void OpDispatchBuilder::RDRANDOp(OpcodeArgs) {
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}
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void OpDispatchBuilder::BreakOp(OpcodeArgs, FEXCore::IR::BreakDefinition BreakDefinition) {
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const uint8_t GPRSize = CTX->GetGPRSize();
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const auto GPRSize = CTX->GetGPROpSize();
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// We don't actually support this instruction
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// Multiblock may hit it though
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