diff --git a/FEXCore/Scripts/json_ir_generator.py b/FEXCore/Scripts/json_ir_generator.py index 73dbd5577..51d98f5fa 100755 --- a/FEXCore/Scripts/json_ir_generator.py +++ b/FEXCore/Scripts/json_ir_generator.py @@ -58,6 +58,7 @@ class OpDefinition: JITDispatch: bool JITDispatchOverride: str TiedSource: int + Inline: list Arguments: list EmitValidation: list Desc: list @@ -278,6 +279,12 @@ def parse_ops(ops): if "TiedSource" in op_val: OpDef.TiedSource = op_val["TiedSource"] + # Pad Inline out to the argument count + OpDef.Inline = [''] * len(OpDef.Arguments) + if "Inline" in op_val: + Value = op_val["Inline"] + OpDef.Inline[0:len(Value)] = Value + # Do some fixups of the data here if len(OpDef.EmitValidation) != 0: for i in range(len(OpDef.EmitValidation)): @@ -773,9 +780,29 @@ def print_ir_allocator_helpers(): output_file.write(") {\n") output_file.write("\t\tauto ListDataBegin = DualListData.ListBegin();\n") + idx = 0 for arg in op.Arguments: if arg.IsSSA: - output_file.write("\t\t{}->AddUse();\n".format(arg.Name)) + # Inline an immediate if we can + inline = op.Inline[idx] + idx += 1 + + if inline != '': + Sized = "Size" in [x.Name for x in op.Arguments] + P = ["Size" if Sized else "OpSize::i64Bit", arg.Name] + + # A few cases need extra info plumbed. + if inline == "SubtractZero": + P += ["Src2"] + elif inline == "Mem": + P += ["OffsetType", "OffsetScale"] + elif inline == "Memtso": + P += ["OffsetType", "OffsetScale", "true /* TSO */"] + inline = "Mem" + + output_file.write(f"\t\t{arg.Name} = Inline{inline}({', '.join(P)});\n") + + output_file.write(f"\t\t{arg.Name}->AddUse();\n") # Insert validation here. This is skipped for the # OrderedNodeWrapper version because validation can depend on diff --git a/FEXCore/Source/CMakeLists.txt b/FEXCore/Source/CMakeLists.txt index 92687366d..5af3fe154 100644 --- a/FEXCore/Source/CMakeLists.txt +++ b/FEXCore/Source/CMakeLists.txt @@ -65,7 +65,6 @@ set (SRCS Interface/IR/IRDumper.cpp Interface/IR/IREmitter.cpp Interface/IR/PassManager.cpp - Interface/IR/Passes/ConstProp.cpp Interface/IR/Passes/IRDumperPass.cpp Interface/IR/Passes/IRValidation.cpp Interface/IR/Passes/RedundantFlagCalculationElimination.cpp diff --git a/FEXCore/Source/Interface/Core/Addressing.cpp b/FEXCore/Source/Interface/Core/Addressing.cpp index c585d3b54..43ac1d27c 100644 --- a/FEXCore/Source/Interface/Core/Addressing.cpp +++ b/FEXCore/Source/Interface/Core/Addressing.cpp @@ -11,8 +11,7 @@ Ref LoadEffectiveAddress(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSize, b Ref Tmp = A.Base; if (A.Offset) { - Ref Offset = IREmit->Constant(A.Offset); - Tmp = Tmp ? IREmit->_Add(GPRSize, Tmp, Offset) : Offset; + Tmp = Tmp ? IREmit->Add(GPRSize, Tmp, A.Offset) : IREmit->Constant(A.Offset); } if (A.Index) { @@ -25,7 +24,7 @@ Ref LoadEffectiveAddress(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSize, b Tmp = IREmit->_Lshl(GPRSize, A.Index, IREmit->Constant(Log2)); } } else { - Tmp = Tmp ? IREmit->_Add(GPRSize, Tmp, A.Index) : A.Index; + Tmp = Tmp ? IREmit->Add(GPRSize, Tmp, A.Index) : A.Index; } } @@ -46,7 +45,7 @@ Ref LoadEffectiveAddress(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSize, b } if (A.Segment && AddSegmentBase) { - Tmp = Tmp ? IREmit->_Add(GPRSize, Tmp, A.Segment) : A.Segment; + Tmp = Tmp ? IREmit->Add(GPRSize, Tmp, A.Segment) : A.Segment; } return Tmp ?: IREmit->Constant(0); @@ -115,7 +114,7 @@ AddressMode SelectAddressMode(IREmitter* IREmit, AddressMode A, IR::OpSize GPRSi auto ScaledRegisterLoadstore = [IREmit, GPRSize](AddressMode A) -> AddressMode { if (A.Index && A.Segment) { - A.Base = IREmit->_Add(GPRSize, A.Base, A.Segment); + A.Base = IREmit->Add(GPRSize, A.Base, A.Segment); } else if (A.Segment) { A.Index = A.Segment; A.IndexScale = 1; diff --git a/FEXCore/Source/Interface/Core/Core.cpp b/FEXCore/Source/Interface/Core/Core.cpp index 163d17950..0d451f1f4 100644 --- a/FEXCore/Source/Interface/Core/Core.cpp +++ b/FEXCore/Source/Interface/Core/Core.cpp @@ -613,7 +613,7 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue if (InstsInBlock == 0) { // Special case for an empty instruction block. - Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_EntrypointOffset(GPRSize, Block.Entry - GuestRIP)); + Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_InlineEntrypointOffset(GPRSize, Block.Entry - GuestRIP)); } for (size_t i = 0; i < InstsInBlock; ++i) { @@ -657,7 +657,7 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue Thread->OpDispatcher->SetCurrentCodeBlock(CodeWasChangedBlock); Thread->OpDispatcher->_ThreadRemoveCodeEntry(); - Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_EntrypointOffset(GPRSize, InstAddress - GuestRIP)); + Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_InlineEntrypointOffset(GPRSize, InstAddress - GuestRIP)); auto NextOpBlock = Thread->OpDispatcher->CreateNewCodeBlockAfter(CurrentBlock); @@ -723,7 +723,8 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue if (NeedsBlockEnd) { // We had some instructions. Early exit - Thread->OpDispatcher->ExitFunction(Thread->OpDispatcher->_EntrypointOffset(GPRSize, Block.Entry + BlockInstructionsLength - GuestRIP)); + Thread->OpDispatcher->ExitFunction( + Thread->OpDispatcher->_InlineEntrypointOffset(GPRSize, Block.Entry + BlockInstructionsLength - GuestRIP)); break; } diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index 605bc6542..7eab787c8 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -166,7 +166,7 @@ void OpDispatchBuilder::RETOp(OpcodeArgs) { if (Op->OP == 0xC2) { auto Offset = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); - SP = _Add(GPRSize, SP, Offset); + SP = Add(GPRSize, SP, Offset); } // Store the new stack pointer @@ -453,7 +453,7 @@ void OpDispatchBuilder::POPAOp(OpcodeArgs) { StoreGPRRegister(X86State::REG_RBP, Pop(Size, SP), Size); // Skip loading RSP because it'll be correct at the end - SP = _RMWHandle(_Add(OpSize::i64Bit, SP, _InlineConstant(IR::OpSizeToSize(Size)))); + SP = _RMWHandle(Add(OpSize::i64Bit, SP, IR::OpSizeToSize(Size))); StoreGPRRegister(X86State::REG_RBX, Pop(Size, SP), Size); StoreGPRRegister(X86State::REG_RDX, Pop(Size, SP), Size); @@ -524,7 +524,7 @@ void OpDispatchBuilder::CALLOp(OpcodeArgs) { int64_t TargetOffset = Op->Src[0].Literal(); auto NewRIP = GetRelocatedPC(Op, TargetOffset); - auto ConstantPC = _Sub(GPRSize, NewRIP, Constant(TargetOffset)); + auto ConstantPC = Sub(GPRSize, NewRIP, TargetOffset); // Push the return address. Push(GPRSize, ConstantPC); @@ -534,7 +534,7 @@ void OpDispatchBuilder::CALLOp(OpcodeArgs) { if (NextRIP != TargetRIP) { // Store the RIP - ExitFunction(NewRIP, BranchHint::Call, ConstantPC, [&]() { + ExitRelocatedPC(Op, TargetOffset, BranchHint::Call, ConstantPC, [&]() { auto CallReturnJumpTarget = JumpTargets.find(NextRIP); if (CallReturnJumpTarget != JumpTargets.end() && CallReturnJumpTarget->second.IsEntryPoint) { return CallReturnJumpTarget->second.BlockEntry; @@ -567,27 +567,6 @@ void OpDispatchBuilder::CALLAbsoluteOp(OpcodeArgs) { }()); } -Ref OpDispatchBuilder::SelectPF(bool Invert, IR::OpSize ResultSize, Ref TrueValue, Ref FalseValue) { - uint64_t TrueConst, FalseConst; - if (IsValueConstant(WrapNode(TrueValue), &TrueConst) && IsValueConstant(WrapNode(FalseValue), &FalseConst) && FalseConst == 0) { - if (TrueConst == 1) { - return LoadPFRaw(true, Invert); - } else if (TrueConst == 0xffffffff) { - return _Sbfe(OpSize::i32Bit, 1, 0, LoadPFRaw(false, Invert)); - } else if (TrueConst == 0xffffffffffffffffull) { - return _Sbfe(OpSize::i64Bit, 1, 0, LoadPFRaw(false, Invert)); - } - } - - Ref Cmp = LoadPFRaw(false, Invert); - SaveNZCV(); - - // Because we're only clobbering NZCV internally, we ignore all carry flag - // shenanigans and just use the raw test and raw select. - _TestNZ(OpSize::i32Bit, Cmp, _InlineConstant(1)); - return _NZCVSelect(ResultSize, {COND_NEQ}, TrueValue, FalseValue); -} - std::optional OpDispatchBuilder::DecodeNZCVCondition(uint8_t OP) { switch (OP) { case 0x0: { // JO - Jump if OF == 1 @@ -643,51 +622,64 @@ std::optional OpDispatchBuilder::DecodeNZCVCondition(uint8_t OP) } } -Ref OpDispatchBuilder::SelectCC(uint8_t OP, IR::OpSize ResultSize, Ref TrueValue, Ref FalseValue) { - auto Cond = DecodeNZCVCondition(OP); - if (Cond) { - // Use raw select since DecodeNZCVCondition handles the carry invert - return _NZCVSelect(ResultSize, *Cond, TrueValue, FalseValue); - } +static bool ParityJumpIsJP(uint8_t OP) { + LOGMAN_THROW_A_FMT(OP == 0xA || OP == 0xB, "JP or JNP"); + return OP == 0xA; +} - switch (OP) { - case 0xA: // JP - Jump if PF == 1 - case 0xB: { // JNP - Jump if PF == 0 +Ref OpDispatchBuilder::SelectCC0All1(uint8_t OP) { + if (auto Cond = DecodeNZCVCondition(OP); Cond) { + // Use raw select since DecodeNZCVCondition handles the carry invert + return _NZCVSelect(OpSize::i64Bit, *Cond, _InlineConstant(~0ULL), _InlineConstant(0)); + } else { // Raw value contains inverted PF in bottom bit - return SelectPF(OP == 0xA, ResultSize, TrueValue, FalseValue); - } - default: LOGMAN_MSG_A_FMT("Unknown CC Op: 0x{:x}\n", OP); return nullptr; + return _Sbfe(OpSize::i64Bit, 1, 0, LoadPFRaw(false, ParityJumpIsJP(OP))); } } void OpDispatchBuilder::SETccOp(OpcodeArgs) { - // Calculate flags early. CalculateDeferredFlags(); - auto ZeroConst = Constant(0); - auto OneConst = Constant(1); - - auto SrcCond = SelectCC(Op->OP & 0xF, OpSize::i64Bit, OneConst, ZeroConst); + Ref SrcCond; + if (auto Cond = DecodeNZCVCondition(Op->OP & 0xf); Cond) { + // Use raw select since DecodeNZCVCondition handles the carry invert + SrcCond = _NZCVSelect01(*Cond); + } else { + SrcCond = LoadPFRaw(true, ParityJumpIsJP(Op->OP & 0xf)); + } StoreResult(GPRClass, Op, SrcCond, OpSize::iInvalid); } void OpDispatchBuilder::CMOVOp(OpcodeArgs) { const auto GPRSize = GetGPROpSize(); + const auto OP = Op->OP & 0xF; + const auto ResultSize = std::max(OpSize::i32Bit, OpSizeFromSrc(Op)); - // Calculate flags early. CalculateDeferredFlags(); // Destination is always a GPR. Ref Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, GPRSize, Op->Flags); - Ref Src {}; + Ref Src {}, SrcCond {}; if (Op->Src[0].IsGPR()) { Src = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], GPRSize, Op->Flags); } else { Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags); } - auto SrcCond = SelectCC(Op->OP & 0xF, std::max(OpSize::i32Bit, OpSizeFromSrc(Op)), Src, Dest); + if (auto Cond = DecodeNZCVCondition(OP); Cond) { + // Use raw select since DecodeNZCVCondition handles the carry invert + SrcCond = _NZCVSelect(ResultSize, *Cond, Src, Dest); + } else { + // Raw value contains inverted PF in bottom bit + Ref Cmp = LoadPFRaw(false, ParityJumpIsJP(OP)); + SaveNZCV(); + + // Because we're only clobbering NZCV internally, we ignore all carry flag + // shenanigans and just use the raw test and raw select. + _TestNZ(OpSize::i32Bit, Cmp, _InlineConstant(1)); + SrcCond = _NZCVSelect(ResultSize, {COND_NEQ}, Src, Dest); + } StoreResult(GPRClass, Op, SrcCond, OpSize::iInvalid); } @@ -742,10 +734,8 @@ void OpDispatchBuilder::CondJUMPOp(OpcodeArgs) { SetCurrentCodeBlock(JumpTarget); StartNewBlock(); - auto NewRIP = GetRelocatedPC(Op, TargetOffset); - // Store the new RIP - ExitFunction(NewRIP); + ExitRelocatedPC(Op, TargetOffset); } // Failure to take branch @@ -759,11 +749,8 @@ void OpDispatchBuilder::CondJUMPOp(OpcodeArgs) { SetCurrentCodeBlock(JumpTarget); StartNewBlock(); - // Leave block - auto RIPTargetConst = GetRelocatedPC(Op); - - // Store the new RIP - ExitFunction(RIPTargetConst); + // Leave block & store the new RIP + ExitRelocatedPC(Op); } } } @@ -798,10 +785,8 @@ void OpDispatchBuilder::CondJUMPRCXOp(OpcodeArgs) { SetCurrentCodeBlock(JumpTarget); StartNewBlock(); - auto NewRIP = GetRelocatedPC(Op, Op->Src[0].Data.Literal.Value); - // Store the new RIP - ExitFunction(NewRIP); + ExitRelocatedPC(Op, Op->Src[0].Data.Literal.Value); } // Failure to take branch @@ -815,11 +800,8 @@ void OpDispatchBuilder::CondJUMPRCXOp(OpcodeArgs) { SetCurrentCodeBlock(JumpTarget); StartNewBlock(); - // Leave block - auto RIPTargetConst = GetRelocatedPC(Op); - - // Store the new RIP - ExitFunction(RIPTargetConst); + // Leave block & store the new RIP + ExitRelocatedPC(Op); } } } @@ -844,7 +826,7 @@ void OpDispatchBuilder::LoopOp(OpcodeArgs) { uint64_t Target = Op->PC + Op->InstSize + Op->Src[1].Literal(); Ref CondReg = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], SrcSize, Op->Flags); - CondReg = _Sub(OpSize, CondReg, _InlineConstant(1)); + CondReg = Sub(OpSize, CondReg, 1); StoreResult(GPRClass, Op, Op->Src[0], CondReg, OpSize::iInvalid); // If LOOPE then jumps to target if RCX != 0 && ZF == 1 @@ -872,10 +854,8 @@ void OpDispatchBuilder::LoopOp(OpcodeArgs) { SetCurrentCodeBlock(JumpTarget); StartNewBlock(); - auto NewRIP = GetRelocatedPC(Op, Op->Src[1].Data.Literal.Value); - // Store the new RIP - ExitFunction(NewRIP); + ExitRelocatedPC(Op, Op->Src[1].Data.Literal.Value); } // Failure to take branch @@ -889,11 +869,8 @@ void OpDispatchBuilder::LoopOp(OpcodeArgs) { SetCurrentCodeBlock(JumpTarget); StartNewBlock(); - // Leave block - auto RIPTargetConst = GetRelocatedPC(Op); - - // Store the new RIP - ExitFunction(RIPTargetConst); + // Leave block & store the new RIP + ExitRelocatedPC(Op); } } } @@ -937,10 +914,10 @@ void OpDispatchBuilder::JUMPOp(OpcodeArgs) { SetJumpTarget(Jump_, JumpTarget); SetCurrentCodeBlock(JumpTarget); StartNewBlock(); - ExitFunction(GetRelocatedPC(Op, TargetOffset)); + ExitRelocatedPC(Op, TargetOffset); } } else { - ExitFunction(GetRelocatedPC(Op, TargetOffset)); + ExitRelocatedPC(Op, TargetOffset); } } @@ -1416,7 +1393,7 @@ void OpDispatchBuilder::SHLDOp(OpcodeArgs) { // a64 masks the bottom bits, so if we're using a native 32/64-bit shift, we // can negate to do the subtract (it's congruent), which saves a constant. - auto ShiftRight = Size >= 32 ? _Neg(OpSize::i64Bit, Shift) : _Sub(OpSize::i64Bit, Constant(Size), Shift); + auto ShiftRight = Size >= 32 ? _Neg(OpSize::i64Bit, Shift) : Sub(OpSize::i64Bit, Constant(Size), Shift); auto Tmp1 = _Lshl(OpSize::i64Bit, Dest, Shift); auto Tmp2 = _Lshr(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Src, ShiftRight); @@ -1487,7 +1464,7 @@ void OpDispatchBuilder::SHRDOp(OpcodeArgs) { Shift = _And(OpSize::i64Bit, Shift, _InlineConstant(0x1F)); } - auto ShiftLeft = _Sub(OpSize::i64Bit, Constant(Size), Shift); + auto ShiftLeft = Sub(OpSize::i64Bit, Constant(Size), Shift); auto Tmp1 = _Lshr(Size == 64 ? OpSize::i64Bit : OpSize::i32Bit, Dest, Shift); auto Tmp2 = _Lshl(OpSize::i64Bit, Src, ShiftLeft); @@ -1701,15 +1678,13 @@ void OpDispatchBuilder::BLSMSKBMIOp(OpcodeArgs) { const auto Size = OpSizeFromSrc(Op); auto* Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true}); - auto Result = _Xor(Size, _Sub(Size, Src, _InlineConstant(1)), Src); + auto Result = _Xor(Size, Sub(Size, Src, 1), Src); StoreResult(GPRClass, Op, Result, OpSize::iInvalid); InvalidatePF_AF(); // CF set according to the Src - auto Zero = Constant(0); - auto One = Constant(1); - auto CFInv = _Select(IR::COND_NEQ, Src, Zero, One, Zero); + auto CFInv = To01(OpSize::i64Bit, Src); // The output of BLSMSK is always nonzero, so TST will clear Z (along with C // and O) while setting S. @@ -1723,13 +1698,11 @@ void OpDispatchBuilder::BLSRBMIOp(OpcodeArgs) { const auto Size = OpSizeFromSrc(Op); auto* Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true}); - auto Result = _And(Size, _Sub(Size, Src, _InlineConstant(1)), Src); + auto Result = _And(Size, Sub(Size, Src, 1), Src); StoreResult(GPRClass, Op, Result, OpSize::iInvalid); - auto Zero = Constant(0); - auto One = Constant(1); - auto CFInv = _Select(IR::COND_NEQ, Src, Zero, One, Zero); + auto CFInv = To01(OpSize::i64Bit, Src); SetNZ_ZeroCV(Size, Result); SetCFInverted(CFInv); @@ -1788,9 +1761,7 @@ void OpDispatchBuilder::BZHI(OpcodeArgs) { auto Result = _NZCVSelect(Size, {COND_NEQ}, Src, MaskResult); StoreResult(GPRClass, Op, Result, OpSize::iInvalid); - auto Zero = _InlineConstant(0); - auto One = _InlineConstant(1); - auto CFInv = _NZCVSelect(OpSize::i32Bit, {COND_EQ}, One, Zero); + auto CFInv = _NZCVSelect01({COND_EQ}); InvalidatePF_AF(); SetNZ_ZeroCV(Size, Result); @@ -2050,7 +2021,7 @@ void OpDispatchBuilder::RCROp(OpcodeArgs) { // Our new CF will be bit (Shift - 1) of the source. this is hoisted up to // avoid the need to copy the source. Again, the Lshr absorbs the masking. - auto NewCF = _Lshr(OpSize, Dest, _Sub(OpSize, Src, _InlineConstant(1))); + auto NewCF = _Lshr(OpSize, Dest, Sub(OpSize, Src, 1)); SetCFDirect(NewCF, 0, true); // Since shift != 0 we can inject the CF @@ -2154,7 +2125,7 @@ void OpDispatchBuilder::RCRSmallerOp(OpcodeArgs) { if (Src.IsConstant) { SetCFDirect(Tmp, (Src.C & 0x1f) - 1, true); } else { - auto NewCF = _Lshr(OpSize::i32Bit, Tmp, _Sub(OpSize::i32Bit, Src.Ref(), _InlineConstant(1))); + auto NewCF = _Lshr(OpSize::i32Bit, Tmp, Sub(OpSize::i32Bit, Src.Ref(), 1)); SetCFDirect(NewCF, 0, true); } @@ -2264,7 +2235,7 @@ void OpDispatchBuilder::RCLOp(OpcodeArgs) { SetCFDirect(NewCF, 0, true); // Since Shift != 0 we can inject the CF. Shift absorbs the masking. - Ref CFShl = _Sub(OpSize, Src, _InlineConstant(1)); + Ref CFShl = Sub(OpSize, Src, 1); auto TmpCF = _Lshl(OpSize, CF, CFShl); Res = _Or(OpSize, Res, TmpCF); @@ -2762,7 +2733,7 @@ void OpDispatchBuilder::PopcountOp(OpcodeArgs) { Ref OpDispatchBuilder::CalculateAFForDecimal(Ref A) { auto Nibble = _And(OpSize::i64Bit, A, Constant(0xF)); - auto Greater = _Select(FEXCore::IR::COND_UGT, Nibble, Constant(9), Constant(1), Constant(0)); + auto Greater = Select01(OpSize::i64Bit, CondClassType {COND_UGT}, Nibble, Constant(9)); return _Or(OpSize::i64Bit, LoadAF(), Greater); } @@ -2774,13 +2745,13 @@ void OpDispatchBuilder::DAAOp(OpcodeArgs) { auto AF = CalculateAFForDecimal(AL); // CF |= (AL > 0x99); - CFInv = _And(OpSize::i64Bit, CFInv, _Select(FEXCore::IR::COND_ULE, AL, Constant(0x99), Constant(1), Constant(0))); + CFInv = _And(OpSize::i64Bit, CFInv, Select01(OpSize::i64Bit, CondClassType {COND_ULE}, AL, Constant(0x99))); // AL = AF ? (AL + 0x6) : AL; - AL = _Select(FEXCore::IR::COND_NEQ, AF, Constant(0), _Add(OpSize::i64Bit, AL, Constant(0x6)), AL); + AL = _Select(FEXCore::IR::COND_NEQ, AF, Constant(0), Add(OpSize::i64Bit, AL, 0x6), AL); // AL = CF ? (AL + 0x60) : AL; - AL = _Select(FEXCore::IR::COND_EQ, CFInv, Constant(0), _Add(OpSize::i64Bit, AL, Constant(0x60)), AL); + AL = _Select(FEXCore::IR::COND_EQ, CFInv, Constant(0), Add(OpSize::i64Bit, AL, 0x60), AL); // SF, ZF, PF set according to result. CF set per above. OF undefined. StoreGPRRegister(X86State::REG_RAX, AL, OpSize::i8Bit); @@ -2797,16 +2768,16 @@ void OpDispatchBuilder::DASOp(OpcodeArgs) { auto AF = CalculateAFForDecimal(AL); // CF |= (AL > 0x99); - CF = _Or(OpSize::i64Bit, CF, _Select(FEXCore::IR::COND_UGT, AL, Constant(0x99), Constant(1), Constant(0))); + CF = _Or(OpSize::i64Bit, CF, Select01(OpSize::i64Bit, CondClassType {COND_UGT}, AL, Constant(0x99))); // NewCF = CF | (AF && (Borrow from AL - 6)) auto NewCF = _Or(OpSize::i32Bit, CF, _Select(FEXCore::IR::COND_ULT, AL, Constant(6), AF, CF)); // AL = AF ? (AL - 0x6) : AL; - AL = _Select(FEXCore::IR::COND_NEQ, AF, Constant(0), _Sub(OpSize::i64Bit, AL, Constant(0x6)), AL); + AL = _Select(FEXCore::IR::COND_NEQ, AF, Constant(0), Sub(OpSize::i64Bit, AL, 0x6), AL); // AL = CF ? (AL - 0x60) : AL; - AL = _Select(FEXCore::IR::COND_NEQ, CF, Constant(0), _Sub(OpSize::i64Bit, AL, Constant(0x60)), AL); + AL = _Select(FEXCore::IR::COND_NEQ, CF, Constant(0), Sub(OpSize::i64Bit, AL, 0x60), AL); // SF, ZF, PF set according to result. CF set per above. OF undefined. StoreGPRRegister(X86State::REG_RAX, AL, OpSize::i8Bit); @@ -2826,7 +2797,7 @@ void OpDispatchBuilder::AAAOp(OpcodeArgs) { CalculateDeferredFlags(); // AX = CF ? (AX + 0x106) : 0 - A = NZCVSelect(OpSize::i32Bit, {COND_UGE} /* CF = 1 */, _Add(OpSize::i32Bit, A, Constant(0x106)), A); + A = NZCVSelect(OpSize::i32Bit, {COND_UGE} /* CF = 1 */, Add(OpSize::i32Bit, A, 0x106), A); // AL = AL & 0x0F A = _And(OpSize::i32Bit, A, Constant(0xFF0F)); @@ -2843,7 +2814,7 @@ void OpDispatchBuilder::AASOp(OpcodeArgs) { CalculateDeferredFlags(); // AX = CF ? (AX - 0x106) : 0 - A = NZCVSelect(OpSize::i32Bit, {COND_UGE} /* CF = 1 */, _Sub(OpSize::i32Bit, A, Constant(0x106)), A); + A = NZCVSelect(OpSize::i32Bit, {COND_UGE} /* CF = 1 */, Sub(OpSize::i32Bit, A, 0x106), A); // AL = AL & 0x0F A = _And(OpSize::i32Bit, A, Constant(0xFF0F)); @@ -2868,7 +2839,7 @@ void OpDispatchBuilder::AADOp(OpcodeArgs) { auto A = LoadGPRRegister(X86State::REG_RAX); auto AH = _Lshr(OpSize::i32Bit, A, Constant(8)); auto Imm8 = Constant(Op->Src[0].Data.Literal.Value & 0xFF); - auto NewAL = _Add(OpSize::i64Bit, A, _Mul(OpSize::i64Bit, AH, Imm8)); + auto NewAL = Add(OpSize::i64Bit, A, _Mul(OpSize::i64Bit, AH, Imm8)); auto Result = _And(OpSize::i64Bit, NewAL, Constant(0xFF)); StoreGPRRegister(X86State::REG_RAX, Result, OpSize::i16Bit); @@ -2937,14 +2908,13 @@ void OpDispatchBuilder::EnterOp(OpcodeArgs) { if (Level > 0) { for (uint8_t i = 1; i < Level; ++i) { - auto Offset = Constant(i * IR::OpSizeToSize(GPRSize)); - auto MemLoc = _Sub(GPRSize, OldBP, Offset); + auto MemLoc = Sub(GPRSize, OldBP, i * IR::OpSizeToSize(GPRSize)); auto Mem = _LoadMem(GPRClass, GPRSize, MemLoc, GPRSize); NewSP = PushValue(GPRSize, Mem); } NewSP = PushValue(GPRSize, temp_RBP); } - NewSP = _Sub(GPRSize, NewSP, Constant(AllocSpace)); + NewSP = Sub(GPRSize, NewSP, AllocSpace); StoreGPRRegister(X86State::REG_RSP, NewSP); StoreGPRRegister(X86State::REG_RBP, temp_RBP); } @@ -3074,7 +3044,7 @@ void OpDispatchBuilder::INCOp(OpcodeArgs) { if (Size < 32 && CTX->HostFeatures.SupportsFlagM) { // Addition producing upper garbage - Result = _Add(OpSize::i32Bit, Dest, _InlineConstant(1)); + Result = Add(OpSize::i32Bit, Dest, 1); CalculatePF(Result); CalculateAF(Dest, Constant(1)); @@ -3115,7 +3085,7 @@ void OpDispatchBuilder::DECOp(OpcodeArgs) { if (Size < 32 && CTX->HostFeatures.SupportsFlagM) { // Subtraction producing upper garbage - Result = _Sub(OpSize::i32Bit, Dest, _InlineConstant(1)); + Result = Sub(OpSize::i32Bit, Dest, 1); CalculatePF(Result); CalculateAF(Dest, Constant(1)); @@ -3195,11 +3165,11 @@ void OpDispatchBuilder::MOVSOp(OpcodeArgs) { auto SrcSegment = GetSegment(Op->Flags, FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX); if (DstSegment) { - DstAddr = _Add(OpSize::i64Bit, DstAddr, DstSegment); + DstAddr = Add(OpSize::i64Bit, DstAddr, DstSegment); } if (SrcSegment) { - SrcAddr = _Add(OpSize::i64Bit, SrcAddr, SrcSegment); + SrcAddr = Add(OpSize::i64Bit, SrcAddr, SrcSegment); } Ref Result_Src = _AllocateGPR(false); @@ -3207,11 +3177,11 @@ void OpDispatchBuilder::MOVSOp(OpcodeArgs) { _MemCpy(CTX->IsAtomicTSOEnabled(), Size, DstAddr, SrcAddr, Counter, LoadDir(1), Result_Dst, Result_Src); if (DstSegment) { - Result_Dst = _Sub(OpSize::i64Bit, Result_Dst, DstSegment); + Result_Dst = Sub(OpSize::i64Bit, Result_Dst, DstSegment); } if (SrcSegment) { - Result_Src = _Sub(OpSize::i64Bit, Result_Src, SrcSegment); + Result_Src = Sub(OpSize::i64Bit, Result_Src, SrcSegment); } StoreGPRRegister(X86State::REG_RCX, Constant(0)); @@ -3227,8 +3197,8 @@ void OpDispatchBuilder::MOVSOp(OpcodeArgs) { _StoreMemAutoTSO(GPRClass, Size, RDI, Src, Size); auto PtrDir = LoadDir(IR::OpSizeToSize(Size)); - RSI = _Add(OpSize::i64Bit, RSI, PtrDir); - RDI = _Add(OpSize::i64Bit, RDI, PtrDir); + RSI = Add(OpSize::i64Bit, RSI, PtrDir); + RDI = Add(OpSize::i64Bit, RDI, PtrDir); StoreGPRRegister(X86State::REG_RSI, RSI); StoreGPRRegister(X86State::REG_RDI, RDI); @@ -3259,11 +3229,11 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) { auto PtrDir = LoadDir(IR::OpSizeToSize(Size)); // Offset the pointer - Dest_RDI = _Add(OpSize::i64Bit, Dest_RDI, PtrDir); + Dest_RDI = Add(OpSize::i64Bit, Dest_RDI, PtrDir); StoreGPRRegister(X86State::REG_RDI, Dest_RDI); // Offset second pointer - Dest_RSI = _Add(OpSize::i64Bit, Dest_RSI, PtrDir); + Dest_RSI = Add(OpSize::i64Bit, Dest_RSI, PtrDir); StoreGPRRegister(X86State::REG_RSI, Dest_RSI); } else { // Calculate flags early. @@ -3307,17 +3277,17 @@ void OpDispatchBuilder::CMPSOp(OpcodeArgs) { Ref TailCounter = LoadGPRRegister(X86State::REG_RCX); // Decrement counter - TailCounter = _SubWithFlags(OpSize::i64Bit, TailCounter, Constant(1)); + TailCounter = SubWithFlags(OpSize::i64Bit, TailCounter, 1); // Store the counter since we don't have phis StoreGPRRegister(X86State::REG_RCX, TailCounter); // Offset the pointer - Dest_RDI = _Add(OpSize::i64Bit, Dest_RDI, Constant(PtrDir * static_cast(IR::OpSizeToSize(Size)))); + Dest_RDI = Add(OpSize::i64Bit, Dest_RDI, PtrDir * static_cast(IR::OpSizeToSize(Size))); StoreGPRRegister(X86State::REG_RDI, Dest_RDI); // Offset second pointer - Dest_RSI = _Add(OpSize::i64Bit, Dest_RSI, Constant(PtrDir * static_cast(IR::OpSizeToSize(Size)))); + Dest_RSI = Add(OpSize::i64Bit, Dest_RSI, PtrDir * static_cast(IR::OpSizeToSize(Size))); StoreGPRRegister(X86State::REG_RSI, Dest_RSI); // If TailCounter != 0, compare sources. @@ -3417,13 +3387,13 @@ void OpDispatchBuilder::LODSOp(OpcodeArgs) { Ref TailDest_RSI = LoadGPRRegister(X86State::REG_RSI); // Decrement counter - TailCounter = _Sub(OpSize::i64Bit, TailCounter, Constant(1)); + TailCounter = Sub(OpSize::i64Bit, TailCounter, 1); // Store the counter since we don't have phis StoreGPRRegister(X86State::REG_RCX, TailCounter); // Offset the pointer - TailDest_RSI = _Add(OpSize::i64Bit, TailDest_RSI, Constant(PtrDir * static_cast(IR::OpSizeToSize(Size)))); + TailDest_RSI = Add(OpSize::i64Bit, TailDest_RSI, PtrDir * static_cast(IR::OpSizeToSize(Size))); StoreGPRRegister(X86State::REG_RSI, TailDest_RSI); // Jump back to the start, we have more work to do @@ -3501,13 +3471,13 @@ void OpDispatchBuilder::SCASOp(OpcodeArgs) { Ref TailDest_RDI = LoadGPRRegister(X86State::REG_RDI); // Decrement counter - TailCounter = _Sub(OpSize::i64Bit, TailCounter, Constant(1)); + TailCounter = Sub(OpSize::i64Bit, TailCounter, 1); // Store the counter since we don't have phis StoreGPRRegister(X86State::REG_RCX, TailCounter); // Offset the pointer - TailDest_RDI = _Add(OpSize::i64Bit, TailDest_RDI, Constant(Dir * static_cast(IR::OpSizeToSize(Size)))); + TailDest_RDI = Add(OpSize::i64Bit, TailDest_RDI, Dir * static_cast(IR::OpSizeToSize(Size))); StoreGPRRegister(X86State::REG_RDI, TailDest_RDI); CalculateDeferredFlags(); @@ -3895,7 +3865,7 @@ void OpDispatchBuilder::Finalize() { // We haven't emitted. Dump out to the dispatcher SetCurrentCodeBlock(Handler.second.BlockEntry); - ExitFunction(_EntrypointOffset(GPRSize, Handler.first - Entry)); + ExitFunction(_InlineEntrypointOffset(GPRSize, Handler.first - Entry)); } } @@ -3970,7 +3940,7 @@ Ref OpDispatchBuilder::GetSegment(uint32_t Flags, uint32_t DefaultPrefix, bool O Ref OpDispatchBuilder::AppendSegmentOffset(Ref Value, uint32_t Flags, uint32_t DefaultPrefix, bool Override) { auto Segment = GetSegment(Flags, DefaultPrefix, Override); if (Segment) { - Value = _Add(std::max(OpSize::i32Bit, std::max(GetOpSize(Value), GetOpSize(Segment))), Value, Segment); + Value = Add(std::max(OpSize::i32Bit, std::max(GetOpSize(Value), GetOpSize(Segment))), Value, Segment); } return Value; @@ -4198,7 +4168,7 @@ Ref OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, const X86T } else { // For X87 extended doubles, Split the load. auto Res = _LoadMem(Class, OpSize::i64Bit, MemSrc, Align == OpSize::iInvalid ? OpSize : Align); - return _VLoadVectorElement(OpSize::i128Bit, OpSize::i16Bit, Res, 4, _Add(OpSize::i64Bit, MemSrc, _InlineConstant(8))); + return _VLoadVectorElement(OpSize::i128Bit, OpSize::i16Bit, Res, 4, Add(OpSize::i64Bit, MemSrc, 8)); } } @@ -4208,11 +4178,6 @@ Ref OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, const X86T } } -Ref OpDispatchBuilder::GetRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset) { - const auto GPRSize = GetGPROpSize(); - return _EntrypointOffset(GPRSize, Op->PC + Op->InstSize + Offset - Entry); -} - Ref OpDispatchBuilder::LoadGPRRegister(uint32_t GPR, IR::OpSize Size, uint8_t Offset, bool AllowUpperGarbage) { const auto GPRSize = GetGPROpSize(); if (Size == OpSize::iInvalid) { @@ -4351,7 +4316,7 @@ void OpDispatchBuilder::StoreResult(FEXCore::IR::RegisterClassType Class, FEXCor } OpDispatchBuilder::OpDispatchBuilder(FEXCore::Context::ContextImpl* ctx) - : IREmitter {ctx->OpDispatcherAllocator} + : IREmitter {ctx->OpDispatcherAllocator, ctx->HostFeatures.SupportsTSOImm9} , CTX {ctx} { ResetWorkingList(); InstallHostSpecificOpcodeHandlers(); @@ -4366,9 +4331,6 @@ OpDispatchBuilder::OpDispatchBuilder(FEXCore::Context::ContextImpl* ctx) DefaultAVXStateFunc = &OpDispatchBuilder::AVX128_DefaultAVXState; } } -OpDispatchBuilder::OpDispatchBuilder(FEXCore::Utils::IntrusivePooledAllocator& Allocator) - : IREmitter {Allocator} - , CTX {nullptr} {} void OpDispatchBuilder::ResetWorkingList() { IREmitter::ResetWorkingList(); @@ -4409,7 +4371,7 @@ void OpDispatchBuilder::ALUOp(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::I auto Zero = LoadGPR(Op->Dest.Data.GPR.GPR); HandleNZ00Write(); InvalidateAF(); - CalculatePF(_SubWithFlags(OpSize::i32Bit, Zero, Zero)); + CalculatePF(SubWithFlags(OpSize::i32Bit, Zero, Zero)); CFInverted = true; FlushRegisterCache(); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index ea137a015..081e2807b 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -201,8 +201,7 @@ public: const auto GPRSize = GetGPROpSize(); // If we don't have a jump target to a new block then we have to leave // Set the RIP to the next instruction and leave - auto RelocatedNextRIP = _EntrypointOffset(GPRSize, NextRIP - Entry); - ExitFunction(RelocatedNextRIP); + ExitFunction(_InlineEntrypointOffset(GPRSize, NextRIP - Entry)); } else if (it != JumpTargets.end()) { Jump(it->second.BlockEntry); return true; @@ -266,7 +265,6 @@ public: } OpDispatchBuilder(FEXCore::Context::ContextImpl* ctx); - OpDispatchBuilder(FEXCore::Utils::IntrusivePooledAllocator& Allocator); void ResetWorkingList(); void ResetDecodeFailure() { @@ -1189,6 +1187,33 @@ public: } } + void StoreContextHelper(IR::OpSize Size, RegisterClassType Class, Ref Value, uint32_t Offset) { + // For i128Bit, we won't see a normal Constant to inline, but as a special + // case we can replace with a 2x64-bit store which can use inline zeroes. + if (Size == OpSize::i128Bit) { + auto Header = GetOpHeader(WrapNode(Value)); + const auto MAX_STP_OFFSET = (252 * 4); + + if (Offset <= MAX_STP_OFFSET && Header->Op == OP_LOADNAMEDVECTORCONSTANT) { + auto Const = Header->C(); + + if (Const->Constant == IR::NamedVectorConstant::NAMED_VECTOR_ZERO) { + Ref Zero = _Constant(0); + Ref STP = _StoreContextPair(IR::OpSize::i64Bit, GPRClass, Zero, Zero, Offset); + + // XXX: This works around InlineConstant not having an associated + // register class, else we'd just do InlineConstant above. + Ref InlineZero = _InlineConstant(0); + ReplaceNodeArgument(STP, 0, InlineZero); + ReplaceNodeArgument(STP, 1, InlineZero); + return; + } + } + } + + _StoreContext(Size, Class, Value, Offset); + } + void FlushRegisterCache(bool SRAOnly = false) { // At block boundaries, fix up the carry flag. if (!SRAOnly) { @@ -1254,7 +1279,7 @@ public: _StoreContextPair(Size, Class, ValueNext, Value, Offset - SizeInt); Bits &= ~NextBit; } else { - _StoreContext(Size, Class, Value, Offset); + StoreContextHelper(Size, Class, Value, Offset); // If Partial and MMX register, then we need to store all 1s in bits 64-80 if (Partial && Index >= MM0Index && Index <= MM7Index) { _StoreContext(OpSize::i16Bit, IR::GPRClass, Constant(0xFFFF), Offset + 8); @@ -1521,7 +1546,23 @@ private: void StoreGPRRegister(uint32_t GPR, const Ref Src, IR::OpSize Size = OpSize::iInvalid, uint8_t Offset = 0); void StoreXMMRegister(uint32_t XMM, const Ref Src); - Ref GetRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset = 0); + Ref _GetRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset, bool Inline) { + const auto GPRSize = GetGPROpSize(); + const auto Offs = Op->PC + Op->InstSize + Offset - Entry; + return Inline ? _InlineEntrypointOffset(GPRSize, Offs) : _EntrypointOffset(GPRSize, Offs); + } + + Ref GetRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset = 0) { + return _GetRelocatedPC(Op, Offset, false); + } + + void ExitRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset = 0) { + ExitFunction(_GetRelocatedPC(Op, Offset, true /* Inline */)); + } + + void ExitRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset, BranchHint Hint, Ref CallReturnAddress, Ref CallReturnBlock) { + ExitFunction(_GetRelocatedPC(Op, Offset, true /* Inline */), Hint, CallReturnAddress, CallReturnBlock); + } [[nodiscard]] static bool IsOperandMem(const X86Tables::DecodedOperand& Operand, bool Load) { @@ -1650,7 +1691,7 @@ private: // This is currently worse for 8/16-bit, but that should be optimized. TODO if (SrcSize >= OpSize::i32Bit) { if (SetPF) { - CalculatePF(_SubWithFlags(SrcSize, Res, Constant(0))); + CalculatePF(SubWithFlags(SrcSize, Res, (uint64_t)0)); } else { _SubNZCV(SrcSize, Res, Constant(0)); } @@ -2036,7 +2077,7 @@ private: } else { // Because we explicitly inverted for CF above, we use the unsafe // _NZCVSelect rather than the safe CF-aware version. - return _NZCVSelect(OpSize::i32Bit, CondForNZCVBit(BitOffset, Invert), Constant(1), Constant(0)); + return _NZCVSelect01(CondForNZCVBit(BitOffset, Invert)); } } else if (BitOffset == FEXCore::X86State::RFLAG_PF_RAW_LOC) { return LoadGPR(Core::CPUState::PF_AS_GREG); @@ -2133,7 +2174,7 @@ private: void ConvertNZCVToX87() { LOGMAN_THROW_A_FMT(NZCVDirty && CachedNZCV, "NZCV must be saved"); - Ref V = _NZCVSelect(OpSize::i32Bit, CondForNZCVBit(FEXCore::X86State::RFLAG_OF_RAW_LOC, false), Constant(1), Constant(0)); + Ref V = _NZCVSelect01(CondForNZCVBit(FEXCore::X86State::RFLAG_OF_RAW_LOC, false)); if (CTX->HostFeatures.SupportsFlagM2) { // Convert to x86 flags, saves us from or'ing after. @@ -2141,8 +2182,8 @@ private: } // CF is inverted after FCMP - Ref C = _NZCVSelect(OpSize::i32Bit, CondForNZCVBit(FEXCore::X86State::RFLAG_CF_RAW_LOC, true), Constant(1), Constant(0)); - Ref Z = _NZCVSelect(OpSize::i32Bit, CondForNZCVBit(FEXCore::X86State::RFLAG_ZF_RAW_LOC, false), Constant(1), Constant(0)); + Ref C = _NZCVSelect01(CondForNZCVBit(FEXCore::X86State::RFLAG_CF_RAW_LOC, true)); + Ref Z = _NZCVSelect01(CondForNZCVBit(FEXCore::X86State::RFLAG_ZF_RAW_LOC, false)); if (!CTX->HostFeatures.SupportsFlagM2) { C = _Or(OpSize::i32Bit, C, V); @@ -2238,7 +2279,7 @@ private: std::optional DecodeNZCVCondition(uint8_t OP); Ref SelectBit(Ref Cmp, IR::OpSize ResultSize, Ref TrueValue, Ref FalseValue); - Ref SelectCC(uint8_t OP, IR::OpSize ResultSize, Ref TrueValue, Ref FalseValue); + Ref SelectCC0All1(uint8_t OP); /** * @brief Flushes NZCV. Mostly vestigial. @@ -2313,7 +2354,6 @@ private: * @name These functions are used by the deferred flag handling while it is calculating and storing flags in to RFLAGs. * @{ */ Ref LoadPFRaw(bool Mask, bool Invert); - Ref SelectPF(bool Invert, IR::OpSize ResultSize, Ref TrueValue, Ref FalseValue); Ref LoadAF(); void FixupAF(); void SetAFAndFixup(Ref AF); @@ -2551,7 +2591,7 @@ private: } ArithRef Presub(uint64_t K) { - return IsConstant ? ArithRef(E, K - C) : ArithRef(E, E->_Sub(OpSize::i64Bit, E->Constant(K), R)); + return IsConstant ? ArithRef(E, K - C) : ArithRef(E, E->Sub(OpSize::i64Bit, E->Constant(K), R)); } ArithRef Lshl(uint64_t Shift) { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp index 25f0e07ca..d793a2adc 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp @@ -2212,8 +2212,6 @@ void OpDispatchBuilder::AVX128_VTESTP(OpcodeArgs) { // For 256-bit, we need to split up the operation. This is nontrivial. // Let's go the simple route here. Ref ZF, CFInv; - Ref ZeroConst = Constant(0); - Ref OneConst = Constant(1); const auto ElementSizeInBits = IR::OpSizeAsBits(ElementSize); @@ -2255,7 +2253,7 @@ void OpDispatchBuilder::AVX128_VTESTP(OpcodeArgs) { // ExtGPR will either be [0, 8] or [0, 16] If 0 then set Flag. auto ExtGPR = _VExtractToGPR(OpSize::i128Bit, ElementSize, AddWide, 0); - CFInv = _Select(IR::COND_NEQ, ExtGPR, ZeroConst, OneConst, ZeroConst); + CFInv = To01(OpSize::i64Bit, ExtGPR); } // As in PTest, this sets Z appropriately while zeroing the rest of NZCV. @@ -2294,10 +2292,7 @@ void OpDispatchBuilder::AVX128_PTest(OpcodeArgs) { Test1 = _VExtractToGPR(OpSize::i128Bit, OpSize::i16Bit, Test1, 0); Test2 = _VExtractToGPR(OpSize::i128Bit, OpSize::i16Bit, Test2, 0); - auto ZeroConst = Constant(0); - auto OneConst = Constant(1); - - Test2 = _Select(FEXCore::IR::COND_NEQ, Test2, ZeroConst, OneConst, ZeroConst); + Test2 = To01(OpSize::i64Bit, Test2); // Careful, these flags are different between {V,}PTEST and VTESTP{S,D} // Set ZF according to Test1. SF will be zeroed since we do a 32-bit test on @@ -2518,7 +2513,7 @@ OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_VPGatherImpl(OpSize Size, O ///< BaseAddr doesn't need to exist, calculate that here. Ref BaseAddr = VSIB.BaseAddr; if (BaseAddr && VSIB.Displacement) { - BaseAddr = _Add(OpSize::i64Bit, BaseAddr, Constant(VSIB.Displacement)); + BaseAddr = Add(OpSize::i64Bit, BaseAddr, VSIB.Displacement); } else if (VSIB.Displacement) { BaseAddr = Constant(VSIB.Displacement); } else if (!BaseAddr) { @@ -2613,7 +2608,7 @@ OpDispatchBuilder::RefPair OpDispatchBuilder::AVX128_VPGatherQPSImpl(Ref Dest, R ///< BaseAddr doesn't need to exist, calculate that here. Ref BaseAddr = VSIB.BaseAddr; if (BaseAddr && VSIB.Displacement) { - BaseAddr = _Add(OpSize::i64Bit, BaseAddr, Constant(VSIB.Displacement)); + BaseAddr = Add(OpSize::i64Bit, BaseAddr, VSIB.Displacement); } else if (VSIB.Displacement) { BaseAddr = Constant(VSIB.Displacement); } else if (!BaseAddr) { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp index 2a681cc23..c59fecf73 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Flags.cpp @@ -201,7 +201,7 @@ void OpDispatchBuilder::FixupAF() { auto PFRaw = GetRFLAG(FEXCore::X86State::RFLAG_PF_RAW_LOC); auto AFRaw = GetRFLAG(FEXCore::X86State::RFLAG_AF_RAW_LOC); - // Again 64-bit as masking is more expensive given our ConstProp design. + // Again 64-bit as masking is more expensive. Ref XorRes = _Xor(OpSize::i64Bit, AFRaw, PFRaw); SetRFLAG(XorRes); } @@ -267,8 +267,6 @@ Ref OpDispatchBuilder::IncrementByCarry(OpSize OpSize, Ref Src) { } Ref OpDispatchBuilder::CalculateFlags_ADC(IR::OpSize SrcSize, Ref Src1, Ref Src2) { - auto Zero = _InlineConstant(0); - auto One = _InlineConstant(1); auto OpSize = SrcSize == OpSize::i64Bit ? OpSize::i64Bit : OpSize::i32Bit; Ref Res; @@ -288,11 +286,11 @@ Ref OpDispatchBuilder::CalculateFlags_ADC(IR::OpSize SrcSize, Ref Src1, Ref Src2 Ref Src2PlusCF = IncrementByCarry(OpSize, Src2); // Need to zero-extend for the comparison. - Res = _Add(OpSize, Src1, Src2PlusCF); + Res = Add(OpSize, Src1, Src2PlusCF); Res = _Bfe(OpSize, IR::OpSizeAsBits(SrcSize), 0, Res); // TODO: We can fold that second Bfe in (cmp uxth). - auto SelectCFInv = _Select(FEXCore::IR::COND_UGE, Res, Src2PlusCF, One, Zero); + auto SelectCFInv = Select01(OpSize, CondClassType {COND_UGE}, Res, Src2PlusCF); SetNZ_ZeroCV(SrcSize, Res); SetCFInverted(SelectCFInv); @@ -304,8 +302,6 @@ Ref OpDispatchBuilder::CalculateFlags_ADC(IR::OpSize SrcSize, Ref Src1, Ref Src2 } Ref OpDispatchBuilder::CalculateFlags_SBB(IR::OpSize SrcSize, Ref Src1, Ref Src2) { - auto Zero = _InlineConstant(0); - auto One = _InlineConstant(1); auto OpSize = SrcSize == OpSize::i64Bit ? OpSize::i64Bit : OpSize::i32Bit; CalculateAF(Src1, Src2); @@ -325,10 +321,10 @@ Ref OpDispatchBuilder::CalculateFlags_SBB(IR::OpSize SrcSize, Ref Src1, Ref Src2 auto Src2PlusCF = IncrementByCarry(OpSize, Src2); - Res = _Sub(OpSize, Src1, Src2PlusCF); + Res = Sub(OpSize, Src1, Src2PlusCF); Res = _Bfe(OpSize, IR::OpSizeAsBits(SrcSize), 0, Res); - auto SelectCFInv = _Select(FEXCore::IR::COND_UGE, Src1, Src2PlusCF, One, Zero); + auto SelectCFInv = Select01(OpSize, CondClassType {COND_UGE}, Src1, Src2PlusCF); SetNZ_ZeroCV(SrcSize, Res); SetCFInverted(SelectCFInv); @@ -349,10 +345,10 @@ Ref OpDispatchBuilder::CalculateFlags_SUB(IR::OpSize SrcSize, Ref Src1, Ref Src2 Ref Res; if (SrcSize >= OpSize::i32Bit) { - Res = _SubWithFlags(SrcSize, Src1, Src2); + Res = SubWithFlags(SrcSize, Src1, Src2); } else { _SubNZCV(SrcSize, Src1, Src2); - Res = _Sub(OpSize::i32Bit, Src1, Src2); + Res = Sub(OpSize::i32Bit, Src1, Src2); } CalculatePF(Res); @@ -379,10 +375,10 @@ Ref OpDispatchBuilder::CalculateFlags_ADD(IR::OpSize SrcSize, Ref Src1, Ref Src2 Ref Res; if (SrcSize >= OpSize::i32Bit) { - Res = _AddWithFlags(SrcSize, Src1, Src2); + Res = AddWithFlags(SrcSize, Src1, Src2); } else { _AddNZCV(SrcSize, Src1, Src2); - Res = _Add(OpSize::i32Bit, Src1, Src2); + Res = Add(OpSize::i32Bit, Src1, Src2); } CalculatePF(Res); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index ca2f71838..c37b637de 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -3950,10 +3950,7 @@ void OpDispatchBuilder::PTestOpImpl(OpSize Size, Ref Dest, Ref Src) { Test1 = _VExtractToGPR(Size, OpSize::i16Bit, Test1, 0); Test2 = _VExtractToGPR(Size, OpSize::i16Bit, Test2, 0); - auto ZeroConst = Constant(0); - auto OneConst = Constant(1); - - Test2 = _Select(FEXCore::IR::COND_NEQ, Test2, ZeroConst, OneConst, ZeroConst); + Test2 = To01(OpSize::i64Bit, Test2); // Careful, these flags are different between {V,}PTEST and VTESTP{S,D} // Set ZF according to Test1. SF will be zeroed since we do a 32-bit test on @@ -3990,10 +3987,7 @@ void OpDispatchBuilder::VTESTOpImpl(OpSize SrcSize, IR::OpSize ElementSize, Ref Ref AndGPR = _VExtractToGPR(SrcSize, OpSize::i16Bit, MaxAnd, 0); Ref AndNotGPR = _VExtractToGPR(SrcSize, OpSize::i16Bit, MaxAndNot, 0); - Ref ZeroConst = Constant(0); - Ref OneConst = Constant(1); - - Ref CFInv = _Select(IR::COND_NEQ, AndNotGPR, ZeroConst, OneConst, ZeroConst); + Ref CFInv = To01(OpSize::i64Bit, AndNotGPR); // As in PTest, this sets Z appropriately while zeroing the rest of NZCV. SetNZ_ZeroCV(OpSize::i32Bit, AndGPR); @@ -5084,7 +5078,7 @@ void OpDispatchBuilder::VPGATHER(OpcodeArgs) { ///< BaseAddr doesn't need to exist, calculate that here. Ref BaseAddr = VSIB.BaseAddr; if (BaseAddr && VSIB.Displacement) { - BaseAddr = _Add(OpSize::i64Bit, BaseAddr, Constant(VSIB.Displacement)); + BaseAddr = Add(OpSize::i64Bit, BaseAddr, VSIB.Displacement); } else if (VSIB.Displacement) { BaseAddr = Constant(VSIB.Displacement); } else if (!BaseAddr) { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp index 0402410a9..cfa819695 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp @@ -114,10 +114,10 @@ void OpDispatchBuilder::FILD(OpcodeArgs) { auto absolute = _Neg(OpSize::i64Bit, Data, CondClassType {COND_MI}); // left justify the absolute integer - auto shift = _Sub(OpSize::i64Bit, Constant(63), _FindMSB(IR::OpSize::i64Bit, absolute)); + auto shift = Sub(OpSize::i64Bit, Constant(63), _FindMSB(IR::OpSize::i64Bit, absolute)); auto shifted = _Lshl(OpSize::i64Bit, absolute, shift); - auto adjusted_exponent = _Sub(OpSize::i64Bit, Constant(0x3fff + 63), shift); + auto adjusted_exponent = Sub(OpSize::i64Bit, Constant(0x3fff + 63), shift); auto zeroed_exponent = _Select(COND_EQ, absolute, zero, zero, adjusted_exponent); auto upper = _Or(OpSize::i64Bit, sign, zeroed_exponent); @@ -164,12 +164,12 @@ void OpDispatchBuilder::FIST(OpcodeArgs, bool Truncate) { // Check for NaN/Infinity: exponent = 0x7fff SaveNZCV(); _TestNZ(OpSize::i64Bit, Exponent, Constant(0x7fff)); - Ref IsSpecial = _NZCVSelect(OpSize::i64Bit, {COND_EQ}, Constant(1), Constant(0)); + Ref IsSpecial = _NZCVSelect01({COND_EQ}); // For overflow detection, check if exponent indicates a value >= 2^15 // Biased exponent for 2^15 is 0x3fff + 15 = 0x400e - _SubWithFlags(OpSize::i64Bit, Exponent, Constant(0x400e)); - Ref IsOverflow = _NZCVSelect(OpSize::i64Bit, {COND_UGE}, Constant(1), Constant(0)); + SubWithFlags(OpSize::i64Bit, Exponent, 0x400e); + Ref IsOverflow = _NZCVSelect01({COND_UGE}); // Set Invalid Operation flag if overflow or special value Ref InvalidFlag = _Or(OpSize::i64Bit, IsSpecial, IsOverflow); @@ -443,13 +443,13 @@ void OpDispatchBuilder::X87LDENV(OpcodeArgs) { auto NewFCW = _LoadMem(GPRClass, OpSize::i16Bit, Mem, OpSize::i16Bit); _StoreContext(OpSize::i16Bit, GPRClass, NewFCW, offsetof(FEXCore::Core::CPUState, FCW)); - Ref MemLocation = _Add(OpSize::i64Bit, Mem, Constant(IR::OpSizeToSize(Size) * 1)); + Ref MemLocation = Add(OpSize::i64Bit, Mem, IR::OpSizeToSize(Size) * 1); auto NewFSW = _LoadMem(GPRClass, Size, MemLocation, Size); ReconstructX87StateFromFSW_Helper(NewFSW); { // FTW - Ref MemLocation = _Add(OpSize::i64Bit, Mem, Constant(IR::OpSizeToSize(Size) * 2)); + Ref MemLocation = Add(OpSize::i64Bit, Mem, IR::OpSizeToSize(Size) * 2); SetX87FTW(_LoadMem(GPRClass, Size, MemLocation, Size)); } } @@ -512,7 +512,6 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) { _StoreMem(GPRClass, Size, ZeroConst, Mem, Constant(IR::OpSizeToSize(Size) * 6), Size, MEM_OFFSET_SXTX, 1); } - auto OneConst = Constant(1); auto SevenConst = Constant(7); const auto LoadSize = ReducedPrecisionMode ? OpSize::i64Bit : OpSize::i128Bit; for (int i = 0; i < 7; ++i) { @@ -521,7 +520,7 @@ void OpDispatchBuilder::X87FNSAVE(OpcodeArgs) { data = _F80CVTTo(data, OpSize::i64Bit); } _StoreMem(FPRClass, OpSize::i128Bit, data, Mem, Constant((IR::OpSizeToSize(Size) * 7) + (10 * i)), OpSize::i8Bit, MEM_OFFSET_SXTX, 1); - Top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, Top, OneConst), SevenConst); + Top = _And(OpSize::i32Bit, Add(OpSize::i32Bit, Top, 1), SevenConst); } // The final st(7) needs a bit of special handling here @@ -565,9 +564,7 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) { SetX87FTW(_LoadMem(GPRClass, Size, Mem, Constant(IR::OpSizeToSize(Size) * 2), Size, MEM_OFFSET_SXTX, 1)); } - auto OneConst = Constant(1); auto SevenConst = Constant(7); - auto low = Constant(~0ULL); auto high = Constant(0xFFFF); Ref Mask = _VLoadTwoGPRs(low, high); @@ -582,7 +579,7 @@ void OpDispatchBuilder::X87FRSTOR(OpcodeArgs) { } _StoreContextIndexed(Reg, Top, StoreSize, MMBaseOffset(), IR::OpSizeToSize(OpSize::i128Bit), FPRClass); - Top = _And(OpSize::i32Bit, _Add(OpSize::i32Bit, Top, OneConst), SevenConst); + Top = _And(OpSize::i32Bit, Add(OpSize::i32Bit, Top, 1), SevenConst); } // The final st(7) needs a bit of special handling here @@ -831,11 +828,7 @@ void OpDispatchBuilder::X87FCMOV(OpcodeArgs) { default: LOGMAN_MSG_A_FMT("Unhandled FCMOV op: 0x{:x}", Opcode); break; } - auto ZeroConst = Constant(0); - auto AllOneConst = Constant(0xffff'ffff'ffff'ffffull); - - Ref SrcCond = SelectCC(CC, OpSize::i64Bit, AllOneConst, ZeroConst); - Ref VecCond = _VDupFromGPR(OpSize::i128Bit, OpSize::i64Bit, SrcCond); + Ref VecCond = _VDupFromGPR(OpSize::i128Bit, OpSize::i64Bit, SelectCC0All1(CC)); _F80VBSLStack(OpSize::i128Bit, VecCond, Op->OP & 7, 0); } @@ -851,11 +844,9 @@ void OpDispatchBuilder::X87FXAM(OpcodeArgs) { // Claim this is a normal number // We don't support anything else auto TopValid = _StackValidTag(0); - auto ZeroConst = Constant(0); - auto OneConst = Constant(1); // In the case of top being invalid then C3:C2:C0 is 0b101 - auto C3 = _Select(FEXCore::IR::COND_NEQ, TopValid, OneConst, OneConst, ZeroConst); + auto C3 = Select01(OpSize::i32Bit, CondClassType {COND_NEQ}, TopValid, Constant(1)); auto C2 = TopValid; auto C0 = C3; // Mirror C3 until something other than zero is supported diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp index 8db9223da..dbbee1220 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/X87F64.cpp @@ -382,7 +382,7 @@ void OpDispatchBuilder::X87FXTRACTF64(OpcodeArgs) { // non zero case Ref ExpNZ = _Bfe(OpSize::i64Bit, 11, 52, Gpr); - ExpNZ = _Sub(OpSize::i64Bit, ExpNZ, Constant(1023)); + ExpNZ = Sub(OpSize::i64Bit, ExpNZ, Constant(1023)); Ref ExpNZV = _Float_FromGPR_S(OpSize::i64Bit, OpSize::i64Bit, ExpNZ); Ref SigNZ = _And(OpSize::i64Bit, Gpr, Constant(0x800f'ffff'ffff'ffffLL)); diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index 0e578627c..6bd59d1f5 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -308,12 +308,14 @@ "RAOverride": "0" }, "CondJump SSA:$Cmp1, SSA:$Cmp2, SSA:$TrueBlock, SSA:$FalseBlock, CondClass:$Cond{{COND_NEQ}}, OpSize:$CompareSize{OpSize::iInvalid}, i1:$FromNZCV{false}": { + "Inline": ["", "AddSub"], "HasSideEffects": true, "RAOverride": "2" }, "ExitFunction OpSize:#Size, GPR:$NewRIP, BranchHint:$Hint, GPR:$CallReturnAddress, SSA:$CallReturnBlock": { "Desc": ["Exits the current JIT function with a target RIP" ], + "Inline": ["Any"], "HasSideEffects": true, "DestSize": "Size", "RAOverride": "2" @@ -448,10 +450,10 @@ "Zero Extends if value's type is too small", "Truncates if value's type is too large" ], + "Inline": ["Zero", ""], "HasSideEffects": true, "DestSize": "ByteSize", "EmitValidation": [ - "WalkFindRegClass($Value) == $Class", "($Class == GPRClass && (#ByteSize == IR::OpSize::i8Bit || #ByteSize == IR::OpSize::i16Bit || #ByteSize == IR::OpSize::i32Bit || #ByteSize == IR::OpSize::i64Bit)) || $Class == FPRClass", "($Class == FPRClass && (#ByteSize == IR::OpSize::i8Bit || #ByteSize == IR::OpSize::i16Bit || #ByteSize == IR::OpSize::i32Bit || #ByteSize == IR::OpSize::i64Bit || #ByteSize == IR::OpSize::i128Bit || #ByteSize == IR::OpSize::i256Bit)) || $Class == GPRClass", "!($Offset >= offsetof(Core::CPUState, gregs[0]) && $Offset < offsetof(Core::CPUState, gregs[16])) && \"Can't StoreContext to GPR\"", @@ -543,6 +545,7 @@ }, "SSA = LoadMem RegisterClass:$Class, OpSize:#Size, GPR:$Addr, GPR:$Offset, OpSize:$Align, MemOffsetType:$OffsetType, u8:$OffsetScale": { + "Inline": ["", "Mem"], "DestSize": "Size" }, @@ -557,11 +560,9 @@ "Zero Extends if value's type is too small", "Truncates if value's type is too large" ], + "Inline": ["Zero", "", "Mem"], "HasSideEffects": true, - "DestSize": "Size", - "EmitValidation": [ - "WalkFindRegClass($Value) == $Class" - ] + "DestSize": "Size" }, "StoreMemPair RegisterClass:$Class, OpSize:#Size, SSA:$Value1, SSA:$Value2, GPR:$Addr, u32:$Offset": { @@ -569,11 +570,9 @@ "Zero Extends if value's type is too small", "Truncates if value's type is too large" ], + "Inline": ["Zero", "Zero"], "HasSideEffects": true, - "DestSize": "Size", - "EmitValidation": [ - "WalkFindRegClass($Value1) == $Class" - ] + "DestSize": "Size" }, "StoreMemX87SVEOptPredicate OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Value, GPR:$Addr": { @@ -593,6 +592,7 @@ "SSA = LoadMemTSO RegisterClass:$Class, OpSize:#Size, GPR:$Addr, GPR:$Offset, OpSize:$Align, MemOffsetType:$OffsetType, u8:$OffsetScale": { "Desc": ["Does a x86 TSO compatible load from memory. Offset must be Invalid()." ], + "Inline": ["", "Memtso"], "DestSize": "Size", "DynamicDispatch": true }, @@ -600,12 +600,10 @@ "StoreMemTSO RegisterClass:$Class, OpSize:#Size, SSA:$Value, GPR:$Addr, GPR:$Offset, OpSize:$Align, MemOffsetType:$OffsetType, u8:$OffsetScale": { "Desc": ["Does a x86 TSO compatible store to memory. Offset must be Invalid()." ], + "Inline": ["Zero", "", "Memtso"], "HasSideEffects": true, "DestSize": "Size", - "DynamicDispatch": true, - "EmitValidation": [ - "WalkFindRegClass($Value) == $Class" - ] + "DynamicDispatch": true }, "FPR = VLoadVectorMasked OpSize:#RegisterSize, OpSize:#ElementSize, FPR:$Mask, GPR:$Addr, GPR:$Offset, MemOffsetType:$OffsetType, u8:$OffsetScale": { @@ -716,6 +714,7 @@ "Desc": ["Duplicates behaviour of x86 STOS repeat", "Returns the final address that gets generated without the prefix appended." ], + "Inline": ["", "", "Zero", "", "Any"], "HasSideEffects": true, "DestSize": "OpSize::i64Bit" }, @@ -723,6 +722,7 @@ "Desc": ["Duplicates behaviour of x86 MOVS repeat", "Returns the final addresses after they have been incremented or decremented" ], + "Inline": ["", "", "", "Any"], "HasSideEffects": true, "DestSize": "OpSize::i64Bit" }, @@ -760,9 +760,8 @@ "Prefetch i1:$ForStore, i1:$Stream, i8:$CacheLevel, GPR:$Addr, GPR:$Offset, MemOffsetType:$OffsetType, u8:$OffsetScale": { "Desc": ["Does a cacheline prefetch operation" ], - "EmitValidation": [ - "CacheLevel > 0 && CacheLevel < 4" - ], + "Inline": ["", "Mem"], + "EmitValidation": ["CacheLevel > 0 && CacheLevel < 4"], "HasSideEffects": true, "DestSize": "OpSize::i64Bit" }, @@ -1080,6 +1079,7 @@ "Desc": [ "Integer Add", "Will truncate to 64 or 32bits" ], + "Inline": ["", "LargeAddSub"], "DestSize": "Size", "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" @@ -1089,6 +1089,7 @@ "Desc": [ "Integer Add with carry", "Will truncate to 64 or 32bits" ], + "Inline": ["Zero", ""], "DestSize": "Size", "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" @@ -1116,6 +1117,7 @@ }, "GPR = AddWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": { "Desc": [ "Integer add. Truncates and sets NZCV per AddNZCV"], + "Inline": ["", "LargeAddSub"], "DestSize": "Size", "HasSideEffects": true, "EmitValidation": [ @@ -1124,6 +1126,7 @@ }, "AddNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": { "Desc": ["Set NZCV for the sum of two GPRs"], + "Inline": ["", "LargeAddSub"], "HasSideEffects": true, "DestSize": "Size" }, @@ -1150,10 +1153,12 @@ }, "RmifNZCV GPR:$Src, u8:$Rotate, u8:$Mask": { "Desc": ["Rotate, mask, and insert into NZCV on FlagM platforms"], + "Inline": ["Zero", ""], "HasSideEffects": true }, "CondAddNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2, CondClass:$Cond, u8:$FalseNZCV": { "Desc": ["If condition is true, set NZCV per sum of GPRs, else force NZCV to a constant."], + "Inline": ["Zero", "AddSub"], "HasSideEffects": true, "DestSize": "Size", "EmitValidation": [ @@ -1162,6 +1167,7 @@ }, "CondSubNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2, CondClass:$Cond, u8:$FalseNZCV": { "Desc": ["If condition is true, set NZCV per difference of GPRs, else force NZCV to a constant."], + "Inline": ["Zero", "AddSub"], "HasSideEffects": true, "DestSize": "Size", "EmitValidation": [ @@ -1170,6 +1176,7 @@ }, "GPR = AdcWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": { "Desc": ["Adds and set NZCV for the sum of two GPRs and carry-in given as NZCV"], + "Inline": ["Zero", ""], "HasSideEffects": true, "DestSize": "Size", "EmitValidation": [ @@ -1219,6 +1226,7 @@ "Desc": [ "Integer Sub", "Will truncate to 64 or 32bits" ], + "Inline": ["SubtractZero", "LargeAddSub"], "DestSize": "Size", "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" @@ -1236,6 +1244,7 @@ }, "GPR = SubWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": { "Desc": [ "Integer Sub. Truncates and sets NZCV per SubNZCV"], + "Inline": ["SubtractZero", "LargeAddSub"], "DestSize": "Size", "HasSideEffects": true, "EmitValidation": [ @@ -1252,6 +1261,7 @@ "Desc": ["Set NZCV for the difference of two GPRs. ", "Carry flag uses arm64 definition, inverted x86.", ""], + "Inline": ["Zero", "LargeAddSub"], "DestSize": "Size", "HasSideEffects": true }, @@ -1259,6 +1269,7 @@ "Desc": ["Integer binary or" ], "DestSize": "Size", + "Inline": ["", "Logical"], "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" ] @@ -1288,8 +1299,8 @@ ] }, "GPR = Xor OpSize:#Size, GPR:$Src1, GPR:$Src2": { - "Desc": ["Integer binary exclusive or" - ], + "Desc": ["Integer binary exclusive or"], + "Inline": ["", "Logical"], "DestSize": "Size", "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" @@ -1310,8 +1321,8 @@ ] }, "GPR = And OpSize:#Size, GPR:$Src1, GPR:$Src2": { - "Desc": ["Integer binary and" - ], + "Desc": ["Integer binary and"], + "Inline": ["", "Logical"], "DestSize": "Size", "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" @@ -1327,6 +1338,7 @@ "GPR = AndWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": { "Desc": ["Integer binary and" ], + "Inline": ["", "Logical"], "DestSize": "Size", "TiedSource": 0, "HasSideEffects": true @@ -1334,12 +1346,14 @@ "GPR = Andn OpSize:#Size, GPR:$Src1, GPR:$Src2": { "Desc": ["Integer binary AND NOT. Performs the equivalent of Src1 & ~Src2"], "DestSize": "Size", + "Inline": ["", "Logical"], "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" ] }, "TestNZ OpSize:#Size, GPR:$Src1, GPR:$Src2": { "Desc": ["Set NZCV for the binary AND of two GPRs, setting N and Z accordingly and zeroing C and V"], + "Inline": ["", "Logical"], "DestSize": "Size", "HasSideEffects": true }, @@ -1349,24 +1363,24 @@ "HasSideEffects": true }, "GPR = Lshl OpSize:#Size, GPR:$Src1, GPR:$Src2": { - "Desc": ["Integer logical shift left" - ], + "Desc": ["Integer logical shift left"], + "Inline": ["", "Any"], "DestSize": "Size", "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" ] }, "GPR = Lshr OpSize:#Size, GPR:$Src1, GPR:$Src2": { - "Desc": ["Integer logical shift right" - ], + "Desc": ["Integer logical shift right"], + "Inline": ["", "Any"], "DestSize": "Size", "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" ] }, "GPR = Ashr OpSize:#Size, GPR:$Src1, GPR:$Src2": { - "Desc": ["Integer arithmetic shift right" - ], + "Desc": ["Integer arithmetic shift right"], + "Inline": ["", "Any"], "DestSize": "Size", "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" @@ -1383,8 +1397,8 @@ "HasSideEffects": true }, "GPR = Ror OpSize:#Size, GPR:$Src1, GPR:$Src2": { - "Desc": ["Integer rotate right" - ], + "Desc": ["Integer rotate right"], + "Inline": ["", "Any"], "DestSize": "Size", "EmitValidation": [ "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit" @@ -1520,12 +1534,12 @@ "op:", "Dest = Cmp1 Cmp2 ? TrueVal : FalseVal" ], + "Inline": ["", "AddSub", "", ""], "DestSize": "ResultSize", "ImplicitFlagClobber": true, "EmitValidation": [ "CompareSize == FEXCore::IR::OpSize::i32Bit || CompareSize == FEXCore::IR::OpSize::i64Bit || CompareSize == FEXCore::IR::OpSize::i128Bit", - "ResultSize == FEXCore::IR::OpSize::i32Bit || ResultSize == FEXCore::IR::OpSize::i64Bit", - "WalkFindRegClass($Cmp1) == WalkFindRegClass($Cmp2)" + "ResultSize == FEXCore::IR::OpSize::i32Bit || ResultSize == FEXCore::IR::OpSize::i64Bit" ] }, "GPR = Extr OpSize:#Size, GPR:$Upper, GPR:$Lower, u8:$LSB": { diff --git a/FEXCore/Source/Interface/IR/IREmitter.h b/FEXCore/Source/Interface/IR/IREmitter.h index df39b1de1..093f67356 100644 --- a/FEXCore/Source/Interface/IR/IREmitter.h +++ b/FEXCore/Source/Interface/IR/IREmitter.h @@ -1,6 +1,7 @@ // SPDX-License-Identifier: MIT #pragma once +#include "CodeEmitter/Emitter.h" #include "Interface/IR/IR.h" #include "Interface/IR/IntrusiveIRList.h" @@ -23,8 +24,9 @@ class IREmitter { friend class FEXCore::IR::PassManager; public: - IREmitter(FEXCore::Utils::IntrusivePooledAllocator& ThreadAllocator) - : DualListData {ThreadAllocator, 8 * 1024 * 1024} { + IREmitter(FEXCore::Utils::IntrusivePooledAllocator& ThreadAllocator, bool SupportsTSOImm9) + : DualListData {ThreadAllocator, 8 * 1024 * 1024} + , SupportsTSOImm9(SupportsTSOImm9) { ReownOrClaimBuffer(); ResetWorkingList(); } @@ -51,6 +53,56 @@ public: FEXCore::IR::RegisterClassType WalkFindRegClass(Ref Node); + // These inlining helpers are used by IRDefines.inc so define first. + Ref InlineMem(OpSize Size, Ref Offset, MemOffsetType OffsetType, uint8_t& OffsetScale, bool TSO = false) { + uint64_t Imm {}; + if (OffsetType != MEM_OFFSET_SXTX || !IsValueConstant(WrapNode(Offset), &Imm)) { + return Offset; + } + + // The immediate may be scaled in the IR, we need to correct for that. + Imm *= OffsetScale; + + // Signed immediate unscaled 9-bit range for both regular and LRCPC2 ops. + bool IsSIMM9 = ((int64_t)Imm >= -256) && ((int64_t)Imm <= 255); + IsSIMM9 &= (SupportsTSOImm9 || !TSO); + + // Extended offsets for regular loadstore only. + LOGMAN_THROW_A_FMT(Size >= IR::OpSize::i8Bit && Size <= IR::OpSize::i256Bit, "Must be sized"); + + bool IsExtended = (Imm & (IR::OpSizeToSize(Size) - 1)) == 0 && Imm / IR::OpSizeToSize(Size) <= 4095; + IsExtended &= !TSO; + + if (IsSIMM9 || IsExtended) { + OffsetScale = 1; + return _InlineConstant(Imm); + } else { + return Offset; + } + } + +#define DEF_INLINE(Type, Variable, Filter) \ + Ref Inline##Type(OpSize Size, Ref Source) { \ + uint64_t Variable; \ + if (IsValueConstant(WrapNode(Source), &Variable) && (Filter)) { \ + return _InlineConstant(Variable); \ + } else { \ + return Source; \ + } \ + } + + DEF_INLINE(Any, _, true) + DEF_INLINE(Zero, X, X == 0) + DEF_INLINE(AddSub, X, ARMEmitter::IsImmAddSub(X)) + DEF_INLINE(LargeAddSub, X, ARMEmitter::IsImmAddSub(X) && Size >= OpSize::i32Bit); + DEF_INLINE(Logical, X, ARMEmitter::Emitter::IsImmLogical(X, std::max((int)IR::OpSizeAsBits(Size), 32))); + + Ref InlineSubtractZero(OpSize Size, Ref Src1, Ref Src2) { + // Only inline a zero if we won't inline the other source. + return IsValueConstant(WrapNode(Src2)) ? Src1 : InlineZero(Size, Src1); + } +#undef DEF_INLINE + // These handlers add cost to the constructor and destructor // If it becomes an issue then blow them away // GCC also generates some pretty atrocious code around these @@ -82,6 +134,66 @@ public: return _StoreMem(Class, Size, Value, Addr, Invalid(), Align, MEM_OFFSET_SXTX, 1); } + IRPair Select01(FEXCore::IR::OpSize CompareSize, CondClassType Cond, OrderedNode* Cmp1, OrderedNode* Cmp2) { + return _Select(OpSize::i64Bit, CompareSize, Cond, Cmp1, Cmp2, _InlineConstant(1), _InlineConstant(0)); + } + + IRPair To01(FEXCore::IR::OpSize CompareSize, OrderedNode* Cmp1) { + return Select01(CompareSize, CondClassType {COND_NEQ}, Cmp1, Constant(0)); + } + + IRPair _NZCVSelect01(CondClassType Cond) { + return _NZCVSelect(OpSize::i64Bit, Cond, _InlineConstant(1), _InlineConstant(0)); + } + + Ref Addsub(IR::OpSize Size, IROps Op, IROps NegatedOp, Ref Src1, uint64_t Src2) { + // Sign-extend the constant + if (Size == OpSize::i32Bit) { + Src2 = (int64_t)(int32_t)Src2; + } + + // Negative constants need to be negated to inline. + if (Src2 & (1ull << 63) && ARMEmitter::IsImmAddSub(-Src2)) { + Op = NegatedOp; + Src2 = -Src2; + } + + auto Dest = _Add(Size, Src1, Constant(Src2)); + Dest.first->Header.Op = Op; + return Dest; + } + + Ref Add(IR::OpSize Size, Ref Src1, uint64_t Src2) { + return Addsub(Size, OP_ADD, OP_SUB, Src1, Src2); + } + + Ref Sub(IR::OpSize Size, Ref Src1, uint64_t Src2) { + return Addsub(Size, OP_SUB, OP_ADD, Src1, Src2); + } + + Ref AddWithFlags(IR::OpSize Size, Ref Src1, uint64_t Src2) { + return Addsub(Size, OP_ADDWITHFLAGS, OP_SUBWITHFLAGS, Src1, Src2); + } + + Ref SubWithFlags(IR::OpSize Size, Ref Src1, uint64_t Src2) { + return Addsub(Size, OP_SUBWITHFLAGS, OP_ADDWITHFLAGS, Src1, Src2); + } + +#define DEF_ADDSUB(Op) \ + Ref Op(IR::OpSize Size, Ref Src1, Ref Src2) { \ + uint64_t Constant; \ + if (IsValueConstant(WrapNode(Src2), &Constant)) { \ + return Op(Size, Src1, Constant); \ + } else { \ + return _##Op(Size, Src1, Src2); \ + } \ + } + + DEF_ADDSUB(Add) + DEF_ADDSUB(Sub) + DEF_ADDSUB(AddWithFlags) + DEF_ADDSUB(SubWithFlags) + int64_t Constants[32]; Ref ConstantRefs[32]; uint32_t NrConstants; @@ -348,6 +460,7 @@ protected: Ref CurrentCodeBlock {}; fextl::vector CodeBlocks; uint64_t Entry {}; + bool SupportsTSOImm9 {}; }; } // namespace FEXCore::IR diff --git a/FEXCore/Source/Interface/IR/PassManager.cpp b/FEXCore/Source/Interface/IR/PassManager.cpp index 2f97f3146..074df50ac 100644 --- a/FEXCore/Source/Interface/IR/PassManager.cpp +++ b/FEXCore/Source/Interface/IR/PassManager.cpp @@ -71,7 +71,6 @@ void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl* ctx) { if (!DisablePasses()) { InsertPass(CreateX87StackOptimizationPass(ctx->HostFeatures, ctx->Config.Is64BitMode ? IR::OpSize::i64Bit : IR::OpSize::i32Bit)); - InsertPass(CreateConstProp(ctx->HostFeatures.SupportsTSOImm9)); InsertPass(CreateDeadFlagCalculationEliminination()); } } diff --git a/FEXCore/Source/Interface/IR/PassManager.h b/FEXCore/Source/Interface/IR/PassManager.h index 1d09e26c9..53daf1b01 100644 --- a/FEXCore/Source/Interface/IR/PassManager.h +++ b/FEXCore/Source/Interface/IR/PassManager.h @@ -43,7 +43,6 @@ protected: }; class PassManager final { - friend class ConstProp; public: void AddDefaultPasses(FEXCore::Context::ContextImpl* ctx); void AddDefaultValidationPasses(); diff --git a/FEXCore/Source/Interface/IR/Passes.h b/FEXCore/Source/Interface/IR/Passes.h index 34f93c159..6d589fa9f 100644 --- a/FEXCore/Source/Interface/IR/Passes.h +++ b/FEXCore/Source/Interface/IR/Passes.h @@ -16,7 +16,6 @@ namespace FEXCore::IR { class Pass; class RegisterAllocationPass; -fextl::unique_ptr CreateConstProp(bool SupportsTSOImm9); fextl::unique_ptr CreateDeadFlagCalculationEliminination(); fextl::unique_ptr CreateRegisterAllocationPass(const FEXCore::CPUIDEmu* CPUID); fextl::unique_ptr CreateX87StackOptimizationPass(const FEXCore::HostFeatures&, OpSize GPROpSize); diff --git a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp index 7090649f9..e69de29bb 100644 --- a/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp +++ b/FEXCore/Source/Interface/IR/Passes/ConstProp.cpp @@ -1,341 +0,0 @@ -// SPDX-License-Identifier: MIT -/* -$info$ -tags: ir|opts -desc: ConstProp, ZExt elim, const pooling, fcmp reduction, const inlining -$end_info$ -*/ -#include - -#include "Interface/IR/IREmitter.h" -#include "Interface/IR/PassManager.h" - -#include -#include -#include -#include -#include -#include - -#include -#include - -namespace FEXCore::IR { - -// aarch64 heuristics -static bool IsImmLogical(uint64_t imm, unsigned width) { - if (width < 32) { - width = 32; - } - return ARMEmitter::Emitter::IsImmLogical(imm, width); -} - -class ConstProp final : public FEXCore::IR::Pass { -public: - explicit ConstProp(bool SupportsTSOImm9) - : SupportsTSOImm9 {SupportsTSOImm9} {} - - void Run(IREmitter* IREmit) override; - -private: - void ConstantPropagation(IREmitter* IREmit, const IRListView& CurrentIR, Ref CodeNode, IROp_Header* IROp); - - bool SupportsTSOImm9 {}; - - template - bool InlineIf(IREmitter* IREmit, const IRListView& CurrentIR, Ref CodeNode, IROp_Header* IROp, unsigned Index, F Filter) { - uint64_t Constant; - if (!IREmit->IsValueConstant(IROp->Args[Index], &Constant) || !Filter(Constant)) { - return false; - } - - IREmit->SetWriteCursor(CurrentIR.GetNode(IROp->Args[Index])); - IREmit->ReplaceNodeArgument(CodeNode, Index, IREmit->_InlineConstant(Constant)); - return true; - } - - bool Inline(IREmitter* IREmit, const IRListView& CurrentIR, Ref CodeNode, IROp_Header* IROp, unsigned Index) { - return InlineIf(IREmit, CurrentIR, CodeNode, IROp, Index, [](uint64_t _) { return true; }); - } - - bool InlineIfZero(IREmitter* IREmit, const IRListView& CurrentIR, Ref CodeNode, IROp_Header* IROp, unsigned Index) { - return InlineIf(IREmit, CurrentIR, CodeNode, IROp, Index, [](uint64_t X) { return X == 0; }); - } - - bool InlineIfLargeAddSub(IREmitter* IREmit, const IRListView& CurrentIR, Ref CodeNode, IROp_Header* IROp, unsigned Index) { - // We don't allow 8/16-bit operations to have constants, since no - // constant would be in bounds after the JIT's 24/16 shift. - auto Filter = [&IROp](uint64_t X) { - return ARMEmitter::IsImmAddSub(X) && IROp->Size >= OpSize::i32Bit; - }; - - return InlineIf(IREmit, CurrentIR, CodeNode, IROp, Index, Filter); - } - - void InlineMemImmediate(IREmitter* IREmit, const IRListView& IR, Ref CodeNode, IR::RegisterClassType RegisterClass, IROp_Header* IROp, - OrderedNodeWrapper Offset, MemOffsetType OffsetType, const size_t Offset_Index, uint8_t& OffsetScale, bool TSO) { - uint64_t Imm {}; - if (OffsetType != MEM_OFFSET_SXTX || !IREmit->IsValueConstant(Offset, &Imm)) { - return; - } - - // The immediate may be scaled in the IR, we need to correct for that. - Imm *= OffsetScale; - - // Signed immediate unscaled 9-bit range for both regular and LRCPC2 ops. - bool IsSIMM9 = ((int64_t)Imm >= -256) && ((int64_t)Imm <= 255); - IsSIMM9 &= (SupportsTSOImm9 || !TSO); - - // Extended offsets for regular loadstore only. - LOGMAN_THROW_A_FMT(IROp->Size >= IR::OpSize::i8Bit && IROp->Size <= (RegisterClass == GPRClass ? IR::OpSize::i64Bit : IR::OpSize::i256Bit), - "Invalid " - "size"); - bool IsExtended = (Imm & (IR::OpSizeToSize(IROp->Size) - 1)) == 0 && Imm / IR::OpSizeToSize(IROp->Size) <= 4095; - IsExtended &= !TSO; - - if (IsSIMM9 || IsExtended) { - IREmit->SetWriteCursor(IR.GetNode(Offset)); - IREmit->ReplaceNodeArgument(CodeNode, Offset_Index, IREmit->_InlineConstant(Imm)); - OffsetScale = 1; - } - } -}; - -// constprop + some more per instruction logic -void ConstProp::ConstantPropagation(IREmitter* IREmit, const IRListView& CurrentIR, Ref CodeNode, IROp_Header* IROp) { - switch (IROp->Op) { - case OP_ADD: - case OP_SUB: - case OP_ADDWITHFLAGS: - case OP_SUBWITHFLAGS: { - auto Op = IROp->C(); - uint64_t Constant1 {}; - uint64_t Constant2 {}; - bool IsConstant2 = IREmit->IsValueConstant(IROp->Args[1], &Constant2); - - /* IsImmAddSub assumes the constants are sign-extended, take care of that - * here so we get the optimization for 32-bit adds too. - */ - if (Op->Header.Size == OpSize::i32Bit) { - Constant1 = (int64_t)(int32_t)Constant1; - Constant2 = (int64_t)(int32_t)Constant2; - } - - if (IsConstant2 && !ARMEmitter::IsImmAddSub(Constant2) && ARMEmitter::IsImmAddSub(-Constant2)) { - // If the second argument is constant, the immediate is not ImmAddSub, but when negated is. - // So, negate the operation to negate (and inline) the constant. - if (IROp->Op == OP_ADD) { - IROp->Op = OP_SUB; - } else if (IROp->Op == OP_SUB) { - IROp->Op = OP_ADD; - } else if (IROp->Op == OP_ADDWITHFLAGS) { - IROp->Op = OP_SUBWITHFLAGS; - } else if (IROp->Op == OP_SUBWITHFLAGS) { - IROp->Op = OP_ADDWITHFLAGS; - } - - IREmit->SetWriteCursorBefore(CodeNode); - - // Negate the constant. - auto NegConstant = IREmit->_Constant(-Constant2); - - // Replace the second source with the negated constant. - IREmit->ReplaceNodeArgument(CodeNode, Op->Src2_Index, NegConstant); - } - - if (!InlineIfLargeAddSub(IREmit, CurrentIR, CodeNode, IROp, 1) && (IROp->Op == OP_SUB || IROp->Op == OP_SUBWITHFLAGS)) { - // TODO: Generalize this - InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, 0); - } - - break; - } - case OP_ADDNZCV: { - InlineIfLargeAddSub(IREmit, CurrentIR, CodeNode, IROp, 1); - break; - } - case OP_SUBNZCV: { - if (!InlineIfLargeAddSub(IREmit, CurrentIR, CodeNode, IROp, 1)) { - // TODO: Generalize this - InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, 0); - } - break; - } - case OP_AND: - case OP_OR: - case OP_XOR: { - InlineIf(IREmit, CurrentIR, CodeNode, IROp, 1, [&IROp](uint64_t X) { return IsImmLogical(X, IR::OpSizeAsBits(IROp->Size)); }); - break; - } - case OP_ANDWITHFLAGS: - case OP_ANDN: - case OP_TESTNZ: { - InlineIf(IREmit, CurrentIR, CodeNode, IROp, 1, [&IROp](uint64_t X) { return IsImmLogical(X, IR::OpSizeAsBits(IROp->Size)); }); - break; - } - case OP_ASHR: - case OP_ROR: { - Inline(IREmit, CurrentIR, CodeNode, IROp, 1); - break; - } - case OP_LSHL: { - Inline(IREmit, CurrentIR, CodeNode, IROp, 1); - break; - } - case OP_LSHR: { - Inline(IREmit, CurrentIR, CodeNode, IROp, 1); - break; - } - case OP_ADC: - case OP_ADCWITHFLAGS: - case OP_RMIFNZCV: { - InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, 0); - break; - } - case OP_STORECONTEXT: { - // For i128Bit, we won't see a normal Constant to inline, but as a special - // case we can replace with a 2x64-bit store which can use inline zeroes. - if (IROp->Size == OpSize::i128Bit) { - auto Op = IROp->C(); - auto Header = IREmit->GetOpHeader(IROp->Args[0]); - const auto MAX_STP_OFFSET = (252 * 4); - - if (Op->Offset <= MAX_STP_OFFSET && Header->Op == OP_LOADNAMEDVECTORCONSTANT) { - auto Const = Header->C(); - - if (Const->Constant == IR::NamedVectorConstant::NAMED_VECTOR_ZERO) { - IREmit->SetWriteCursor(CodeNode); - Ref Zero = IREmit->_Constant(0); - Ref STP = IREmit->_StoreContextPair(IR::OpSize::i64Bit, GPRClass, Zero, Zero, Op->Offset); - IREmit->Remove(CodeNode); - - // XXX: This works around InlineConstant not having an associated - // register class, else we'd just do InlineConstant above. - Ref InlineZero = IREmit->_InlineConstant(0); - IREmit->ReplaceNodeArgument(STP, 0, InlineZero); - IREmit->ReplaceNodeArgument(STP, 1, InlineZero); - } - } - } else { - InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, 0); - } - - break; - } - - case OP_CONDADDNZCV: - case OP_CONDSUBNZCV: { - InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, 0); - InlineIf(IREmit, CurrentIR, CodeNode, IROp, 1, ARMEmitter::IsImmAddSub); - break; - } - case OP_SELECT: { - InlineIf(IREmit, CurrentIR, CodeNode, IROp, 1, ARMEmitter::IsImmAddSub); - - uint64_t AllOnes = IROp->Size == OpSize::i64Bit ? 0xffff'ffff'ffff'ffffull : 0xffff'ffffull; - - uint64_t Constant2 {}; - uint64_t Constant3 {}; - if (IREmit->IsValueConstant(IROp->Args[2], &Constant2) && IREmit->IsValueConstant(IROp->Args[3], &Constant3) && - (Constant2 == 1 || Constant2 == AllOnes) && Constant3 == 0) { - IREmit->SetWriteCursor(CurrentIR.GetNode(IROp->Args[2])); - - IREmit->ReplaceNodeArgument(CodeNode, 2, IREmit->_InlineConstant(Constant2)); - IREmit->ReplaceNodeArgument(CodeNode, 3, IREmit->_InlineConstant(Constant3)); - } - - break; - } - case OP_NZCVSELECT: { - // We always allow source 1 to be zero, but source 0 can only be a - // special 1/~0 constant if source 1 is 0. - if (InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, 1)) { - uint64_t AllOnes = IROp->Size == OpSize::i64Bit ? 0xffff'ffff'ffff'ffffull : 0xffff'ffffull; - InlineIf(IREmit, CurrentIR, CodeNode, IROp, 0, [&AllOnes](uint64_t X) { return X == 1 || X == AllOnes; }); - } - break; - } - case OP_CONDJUMP: { - InlineIf(IREmit, CurrentIR, CodeNode, IROp, 1, ARMEmitter::IsImmAddSub); - break; - } - case OP_EXITFUNCTION: { - auto Op = IROp->C(); - - if (!Inline(IREmit, CurrentIR, CodeNode, IROp, Op->NewRIP_Index)) { - auto NewRIP = IREmit->GetOpHeader(Op->NewRIP); - if (NewRIP->Op == OP_ENTRYPOINTOFFSET) { - auto EO = NewRIP->C(); - IREmit->SetWriteCursor(CurrentIR.GetNode(Op->NewRIP)); - - IREmit->ReplaceNodeArgument(CodeNode, 0, IREmit->_InlineEntrypointOffset(EO->Header.Size, EO->Offset)); - } - } - break; - } - - case OP_LOADMEM: { - auto Op = IROp->CW(); - InlineMemImmediate(IREmit, CurrentIR, CodeNode, Op->Class, IROp, Op->Offset, Op->OffsetType, Op->Offset_Index, Op->OffsetScale, false); - break; - } - case OP_STOREMEM: { - auto Op = IROp->CW(); - InlineMemImmediate(IREmit, CurrentIR, CodeNode, Op->Class, IROp, Op->Offset, Op->OffsetType, Op->Offset_Index, Op->OffsetScale, false); - InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, Op->Value_Index); - break; - } - case OP_PREFETCH: { - auto Op = IROp->CW(); - InlineMemImmediate(IREmit, CurrentIR, CodeNode, GPRClass, IROp, Op->Offset, Op->OffsetType, Op->Offset_Index, Op->OffsetScale, false); - break; - } - case OP_LOADMEMTSO: { - auto Op = IROp->CW(); - InlineMemImmediate(IREmit, CurrentIR, CodeNode, Op->Class, IROp, Op->Offset, Op->OffsetType, Op->Offset_Index, Op->OffsetScale, true); - break; - } - case OP_STOREMEMTSO: { - auto Op = IROp->CW(); - InlineMemImmediate(IREmit, CurrentIR, CodeNode, Op->Class, IROp, Op->Offset, Op->OffsetType, Op->Offset_Index, Op->OffsetScale, true); - InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, Op->Value_Index); - break; - } - case OP_STOREMEMPAIR: { - auto Op = IROp->CW(); - InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, Op->Value1_Index); - InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, Op->Value2_Index); - break; - } - case OP_MEMCPY: { - auto Op = IROp->CW(); - Inline(IREmit, CurrentIR, CodeNode, IROp, Op->Direction_Index); - break; - } - case OP_MEMSET: { - auto Op = IROp->CW(); - Inline(IREmit, CurrentIR, CodeNode, IROp, Op->Direction_Index); - InlineIfZero(IREmit, CurrentIR, CodeNode, IROp, Op->Value_Index); - break; - } - - default: break; - } -} - -void ConstProp::Run(IREmitter* IREmit) { - FEXCORE_PROFILE_SCOPED("PassManager::ConstProp"); - - auto CurrentIR = IREmit->ViewIR(); - - for (auto [BlockNode, BlockIROp] : CurrentIR.GetBlocks()) { - for (auto [CodeNode, IROp] : CurrentIR.GetCode(BlockNode)) { - ConstantPropagation(IREmit, CurrentIR, CodeNode, IROp); - } - } -} - -fextl::unique_ptr CreateConstProp(bool SupportsTSOImm9) { - return fextl::make_unique(SupportsTSOImm9); -} -} // namespace FEXCore::IR diff --git a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp index dc19f1fdc..5c7d7b98c 100644 --- a/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp +++ b/FEXCore/Source/Interface/IR/Passes/x87StackOptimizationPass.cpp @@ -410,7 +410,7 @@ inline Ref X87StackOptimization::GetOffsetTopWithCache_Slow(uint8_t Offset) { auto* OffsetTop = GetTopWithCache_Slow(); if (Offset != 0) { - OffsetTop = IREmit->_And(OpSize::i32Bit, IREmit->_Add(OpSize::i32Bit, OffsetTop, GetConstant(Offset)), GetConstant(7)); + OffsetTop = IREmit->_And(OpSize::i32Bit, IREmit->Add(OpSize::i32Bit, OffsetTop, Offset), GetConstant(7)); // GetTopWithCache_Slow already sets the cache so we don't need to set it here for offset == 0 TopOffsetCache[Offset] = OffsetTop; } @@ -542,7 +542,7 @@ void X87StackOptimization::HandleBinopStack(IROps Op64, bool VFOp64, IROps Op80, inline void X87StackOptimization::UpdateTopForPop_Slow() { // Pop the top of the x87 stack auto* TopOffset = GetTopWithCache_Slow(); - TopOffset = IREmit->_Add(OpSize::i32Bit, TopOffset, GetConstant(1)); + TopOffset = IREmit->Add(OpSize::i32Bit, TopOffset, 1); TopOffset = IREmit->_And(OpSize::i32Bit, TopOffset, GetConstant(7)); SetTopWithCache_Slow(TopOffset); } @@ -550,7 +550,7 @@ inline void X87StackOptimization::UpdateTopForPop_Slow() { inline void X87StackOptimization::UpdateTopForPush_Slow() { // Pop the top of the x87 stack auto* TopOffset = GetTopWithCache_Slow(); - TopOffset = IREmit->_Sub(OpSize::i32Bit, TopOffset, GetConstant(1)); + TopOffset = IREmit->Sub(OpSize::i32Bit, TopOffset, 1); TopOffset = IREmit->_And(OpSize::i32Bit, TopOffset, GetConstant(7)); SetTopWithCache_Slow(TopOffset); } @@ -569,12 +569,7 @@ Ref X87StackOptimization::SynchronizeStackValues() { if (TopOffset != 0) { auto* OrigTop = GetTopWithCache_Slow(); - Ref NewTop {}; - if (TopOffset > 0) { - NewTop = IREmit->_And(OpSize::i32Bit, IREmit->_Sub(OpSize::i32Bit, OrigTop, GetConstant(TopOffset)), GetConstant(0x7)); - } else { - NewTop = IREmit->_And(OpSize::i32Bit, IREmit->_Add(OpSize::i32Bit, OrigTop, GetConstant(-TopOffset)), GetConstant(0x7)); - } + Ref NewTop = IREmit->_And(OpSize::i32Bit, IREmit->Sub(OpSize::i32Bit, OrigTop, TopOffset), GetConstant(0x7)); SetTopWithCache_Slow(NewTop); } StackData.TopOffset = 0; @@ -832,7 +827,7 @@ void X87StackOptimization::Run(IREmitter* Emit) { auto* TopValue = GetTopWithCache_Slow(); if (Offset != 0) { auto* Mask = GetConstant(7); - TopValue = IREmit->_And(OpSize::i32Bit, IREmit->_Add(OpSize::i32Bit, TopValue, GetConstant(Offset)), Mask); + TopValue = IREmit->_And(OpSize::i32Bit, IREmit->Add(OpSize::i32Bit, TopValue, Offset), Mask); } SetX87ValidTag(TopValue, false); } else { diff --git a/docs/SourceOutline.md b/docs/SourceOutline.md index b85224174..cd4d3f2da 100644 --- a/docs/SourceOutline.md +++ b/docs/SourceOutline.md @@ -105,7 +105,6 @@ C++ Functions to generate IR. See IR.json for spec. IR to IR Optimization - [PassManager.cpp](../FEXCore/Source/Interface/IR/PassManager.cpp): Defines which passes are run, and runs them - [PassManager.h](../FEXCore/Source/Interface/IR/PassManager.h) -- [ConstProp.cpp](../FEXCore/Source/Interface/IR/Passes/ConstProp.cpp): ConstProp, ZExt elim, const pooling, fcmp reduction, const inlining - [IRValidation.cpp](../FEXCore/Source/Interface/IR/Passes/IRValidation.cpp): Sanity checking pass - [RedundantFlagCalculationElimination.cpp](../FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp): This is not used right now, possibly broken - [RegisterAllocationPass.cpp](../FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp) diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index ea94db0aa..b83be6800 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -2702,8 +2702,8 @@ ], "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -2715,8 +2715,8 @@ ], "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -2728,8 +2728,8 @@ ], "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -2741,8 +2741,8 @@ ], "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json index 4caafba40..885a3d7b4 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json @@ -19,8 +19,8 @@ ], "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, @@ -31,8 +31,8 @@ ], "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, @@ -43,8 +43,8 @@ ], "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, @@ -55,8 +55,8 @@ ], "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] } diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index af5c1182f..d96eef8dc 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -512,12 +512,12 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -529,8 +529,6 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "mov w27, #0x0", - "mov w26, #0x1", "and v4.16b, v17.16b, v16.16b", "and v5.16b, v3.16b, v2.16b", "ushr v4.4s, v4.4s, #31", @@ -545,11 +543,13 @@ "add v2.4s, v2.4s, v4.4s", "addv s2, v2.4s", "mov w21, v2.s[0]", + "mov w27, #0x0", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -570,12 +570,12 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -587,8 +587,6 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "mov w27, #0x0", - "mov w26, #0x1", "and v4.16b, v17.16b, v16.16b", "and v5.16b, v3.16b, v2.16b", "ushr v4.2d, v4.2d, #63", @@ -603,11 +601,13 @@ "add v2.2d, v2.2d, v4.2d", "addp v2.2d, v2.2d, v2.2d", "mov x21, v2.d[0]", + "mov w27, #0x0", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -676,12 +676,12 @@ "umov w20, v2.h[0]", "umov w21, v3.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -704,12 +704,12 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json index 0fb409609..2f401d88d 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json @@ -30,11 +30,11 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vtestps ymm0, ymm1": { @@ -45,8 +45,6 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "mov w27, #0x0", - "mov w26, #0x1", "and v4.16b, v17.16b, v16.16b", "and v5.16b, v3.16b, v2.16b", "ushr v4.4s, v4.4s, #31", @@ -61,10 +59,12 @@ "add v2.4s, v2.4s, v4.4s", "addv s2, v2.4s", "mov w21, v2.s[0]", + "mov w27, #0x0", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vtestpd xmm0, xmm1": { @@ -84,11 +84,11 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vtestpd ymm0, ymm1": { @@ -99,8 +99,6 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "mov w27, #0x0", - "mov w26, #0x1", "and v4.16b, v17.16b, v16.16b", "and v5.16b, v3.16b, v2.16b", "ushr v4.2d, v4.2d, #63", @@ -115,10 +113,12 @@ "add v2.2d, v2.2d, v4.2d", "addp v2.2d, v2.2d, v2.2d", "mov x21, v2.d[0]", + "mov w27, #0x0", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vptest xmm0, xmm1": { @@ -134,11 +134,11 @@ "umov w20, v2.h[0]", "umov w21, v3.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vptest ymm0, ymm1": { @@ -160,11 +160,11 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vmaskmovps xmm0, xmm1, [rax]": { @@ -642,7 +642,7 @@ "bic w20, w6, w20", "tst x7, #0xe0", "csel w4, w6, w20, ne", - "cset w20, eq", + "cset x20, eq", "cmp w4, #0x0 (0)", "rmif x20, #63, #nzCv" ] @@ -658,7 +658,7 @@ "bic x20, x6, x20", "tst x7, #0xc0", "csel x4, x6, x20, ne", - "cset w20, eq", + "cset x20, eq", "cmp x4, #0x0 (0)", "rmif x20, #63, #nzCv" ] diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 983e7ccb0..5f6fd7691 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -1477,7 +1477,7 @@ "mov w20, #0xff", "ldaddalb w20, w27, [x4]", "mov w20, #0x1", - "cset w21, hs", + "cset x21, hs", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", "sub w26, w27, #0x1 (1)", @@ -1575,7 +1575,7 @@ "mov w20, #0xffff", "ldaddalh w20, w27, [x4]", "mov w20, #0x1", - "cset w21, hs", + "cset x21, hs", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", "sub w26, w27, #0x1 (1)", @@ -1590,7 +1590,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldaddal w20, w27, [x4]", - "cset w20, hs", + "cset x20, hs", "subs w26, w27, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -1603,7 +1603,7 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "ldaddal x20, x27, [x4]", - "cset w20, hs", + "cset x20, hs", "subs x26, x27, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -1616,7 +1616,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalb w20, w27, [x4]", - "cset w21, hs", + "cset x21, hs", "lsl w0, w27, #24", "cmn w0, w20, lsl #24", "add w26, w27, #0x1 (1)", @@ -1631,7 +1631,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddalh w20, w27, [x4]", - "cset w21, hs", + "cset x21, hs", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", "add w26, w27, #0x1 (1)", @@ -1646,7 +1646,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal w20, w27, [x4]", - "cset w20, hs", + "cset x20, hs", "adds w26, w27, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -1659,7 +1659,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal x20, x27, [x4]", - "cset w20, hs", + "cset x20, hs", "adds x26, x27, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json index c0d063861..1131372d9 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json @@ -171,7 +171,7 @@ "mov w20, #0x5", "movk w20, #0x1, lsl #16", "str x20, [x28, #24]", - "cset w20, lo", + "cset x20, lo", "eor x21, x27, x26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -182,7 +182,7 @@ "ldrsb x21, [x28, #986]", "lsr x21, x21, #63", "orr x20, x20, x21, lsl #10", - "cset w21, vs", + "cset x21, vs", "orr x20, x20, x21, lsl #11", "ldrb w21, [x28, #988]", "orr x20, x20, x21, lsl #12", @@ -1574,7 +1574,7 @@ "mov v16.s[0], v0.s[0]", "mov w7, #0x0", "fcmp s16, s18", - "cset w26, vc", + "cset x26, vc", "axflag", "mov x27, x7" ] diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index 7e6bc3dc6..92922cb3c 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -1389,7 +1389,7 @@ "ExpectedArm64ASM": [ "mov w20, #0xffffffff", "ldaddal w20, w27, [x4]", - "cset w20, hs", + "cset x20, hs", "subs w26, w27, #0x1 (1)", "rmif x20, #63, #nzCv" ] @@ -1400,7 +1400,7 @@ "ExpectedArm64ASM": [ "mov x20, #0xffffffffffffffff", "ldaddal x20, x27, [x4]", - "cset w20, hs", + "cset x20, hs", "subs x26, x27, #0x1 (1)", "rmif x20, #63, #nzCv" ] @@ -1435,7 +1435,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal w20, w27, [x4]", - "cset w20, hs", + "cset x20, hs", "adds w26, w27, #0x1 (1)", "rmif x20, #63, #nzCv" ] @@ -1446,7 +1446,7 @@ "ExpectedArm64ASM": [ "mov w20, #0x1", "ldaddal x20, x27, [x4]", - "cset w20, hs", + "cset x20, hs", "adds x26, x27, #0x1 (1)", "rmif x20, #63, #nzCv" ] diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index e557304b4..38995d18b 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -94,7 +94,7 @@ ], "ExpectedArm64ASM": [ "adds x4, x4, x6", - "cset w20, lo", + "cset x20, lo", "adds x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x27, x4", @@ -125,7 +125,7 @@ ], "ExpectedArm64ASM": [ "subs x4, x4, x6", - "cset w20, hs", + "cset x20, hs", "subs x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x27, x4", @@ -212,7 +212,7 @@ "and x20, x7, #0x3f", "cbz x20, #+0x20", "lsr x20, x4, x7", - "cset w21, lo", + "cset x21, lo", "neg x22, x7", "lsl x23, x4, x22", "orr x20, x20, x23, lsl #1", @@ -304,7 +304,7 @@ ], "ExpectedArm64ASM": [ "fcmp s16, s17", - "cset w26, vc", + "cset x26, vc", "bfxil x7, x26, #0, #8", "subs x26, x4, #0x0 (0)" ] diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json index 34eb6d7ad..c38debaa5 100644 --- a/unittests/InstructionCountCI/FlagM/H0F38.json +++ b/unittests/InstructionCountCI/FlagM/H0F38.json @@ -25,11 +25,11 @@ "umov w20, v2.h[0]", "umov w21, v3.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "adcx eax, ebx": { diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 6564fba94..7d0fdbca0 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -1665,7 +1665,7 @@ "ExpectedInstructionCount": 39, "Comment": "0x9c", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x27, x26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -1676,7 +1676,7 @@ "ldrsb x21, [x28, #986]", "lsr x21, x21, #63", "orr x20, x20, x21, lsl #10", - "cset w21, vs", + "cset x21, vs", "orr x20, x20, x21, lsl #11", "ldrb w21, [x28, #988]", "orr x20, x20, x21, lsl #12", @@ -1710,7 +1710,7 @@ "ExpectedInstructionCount": 39, "Comment": "0x9c", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x27, x26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -1721,7 +1721,7 @@ "ldrsb x21, [x28, #986]", "lsr x21, x21, #63", "orr x20, x20, x21, lsl #10", - "cset w21, vs", + "cset x21, vs", "orr x20, x20, x21, lsl #11", "ldrb w21, [x28, #988]", "orr x20, x20, x21, lsl #12", @@ -1815,7 +1815,7 @@ "ExpectedInstructionCount": 14, "Comment": "0x9f", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x27, x26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index d6854bde2..cdfb161fb 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -908,22 +908,22 @@ "Comment": "GROUP2 0xC0 /2", "ExpectedArm64ASM": [ "uxtb w20, w4", - "mov w21, #0x0", - "cset w22, lo", - "bfi x21, x20, #55, #8", - "bfi x21, x22, #63, #1", - "bfi x21, x20, #46, #8", - "bfi x21, x22, #54, #1", - "bfi x21, x20, #37, #8", - "bfi x21, x22, #45, #1", - "bfi x21, x20, #28, #8", - "bfi x21, x22, #36, #1", - "bfi x21, x20, #19, #8", - "bfi x21, x22, #27, #1", - "bfxil x21, x20, #0, #8", - "ror x20, x21, #62", + "cset x21, lo", + "mov w22, #0x0", + "bfi x22, x20, #55, #8", + "bfi x22, x21, #63, #1", + "bfi x22, x20, #46, #8", + "bfi x22, x21, #54, #1", + "bfi x22, x20, #37, #8", + "bfi x22, x21, #45, #1", + "bfi x22, x20, #28, #8", + "bfi x22, x21, #36, #1", + "bfi x22, x20, #19, #8", + "bfi x22, x21, #27, #1", + "bfxil x22, x20, #0, #8", + "ror x20, x22, #62", "bfxil x4, x20, #0, #8", - "ror x20, x21, #61", + "ror x20, x22, #61", "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] @@ -932,7 +932,7 @@ "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xC0 /3", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "uxtb w21, w4", "bfi x21, x20, #8, #1", "bfi x21, x21, #9, #9", @@ -1044,18 +1044,18 @@ "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "uxth w20, w4", - "mov w21, #0x0", - "cset w22, lo", - "bfi x21, x20, #47, #16", - "bfi x21, x22, #63, #1", - "bfi x21, x20, #30, #16", - "bfi x21, x22, #46, #1", - "bfi x21, x20, #13, #16", - "bfi x21, x22, #29, #1", - "bfxil x21, x20, #0, #16", - "ror x20, x21, #62", + "cset x21, lo", + "mov w22, #0x0", + "bfi x22, x20, #47, #16", + "bfi x22, x21, #63, #1", + "bfi x22, x20, #30, #16", + "bfi x22, x21, #46, #1", + "bfi x22, x20, #13, #16", + "bfi x22, x21, #29, #1", + "bfxil x22, x20, #0, #16", + "ror x20, x22, #62", "bfxil x4, x20, #0, #16", - "ror x20, x21, #61", + "ror x20, x22, #61", "eor x20, x20, #0x1", "rmif x20, #63, #nzCv" ] @@ -1065,7 +1065,7 @@ "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "lsl w20, w4, #2", - "cset w21, lo", + "cset x21, lo", "orr w20, w20, w4, lsr #31", "eor x22, x4, #0x40000000", "rmif x22, #29, #nzCv", @@ -1077,7 +1077,7 @@ "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "lsl x20, x4, #2", - "cset w21, lo", + "cset x21, lo", "orr x20, x20, x4, lsr #63", "eor x22, x4, #0x4000000000000000", "rmif x22, #61, #nzCv", @@ -1088,7 +1088,7 @@ "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "uxth w21, w4", "bfi x21, x20, #16, #1", "bfi x21, x21, #17, #17", @@ -1104,7 +1104,7 @@ "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "lsr w20, w4, #2", - "cset w21, lo", + "cset x21, lo", "orr w20, w20, w4, lsl #31", "eor x22, x4, #0x2", "rmif x22, #0, #nzCv", @@ -1116,7 +1116,7 @@ "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "lsr x20, x4, #2", - "cset w21, lo", + "cset x21, lo", "orr x20, x20, x4, lsl #63", "eor x22, x4, #0x2", "rmif x22, #0, #nzCv", @@ -1257,7 +1257,7 @@ "Comment": "GROUP2 0xd0 /2", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, lo", + "cset x21, lo", "orr w21, w21, w20, lsl #1", "eor x22, x20, #0x80", "rmif x22, #6, #nzCv", @@ -1271,7 +1271,7 @@ "Comment": "GROUP2 0xd0 /3", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, lo", + "cset x21, lo", "eor x22, x20, #0x1", "rmif x22, #63, #nzCv", "ubfx w20, w20, #1, #7", @@ -1396,7 +1396,7 @@ "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ "uxth w20, w4", - "cset w21, lo", + "cset x21, lo", "orr w21, w21, w20, lsl #1", "eor x22, x20, #0x8000", "rmif x22, #14, #nzCv", @@ -1410,7 +1410,7 @@ "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ "mov w20, w4", - "cset w21, lo", + "cset x21, lo", "orr w4, w21, w20, lsl #1", "eor x21, x20, #0x80000000", "rmif x21, #30, #nzCv", @@ -1422,7 +1422,7 @@ "ExpectedInstructionCount": 7, "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "orr x20, x20, x4, lsl #1", "eor x21, x4, #0x8000000000000000", "rmif x21, #62, #nzCv", @@ -1435,7 +1435,7 @@ "ExpectedInstructionCount": 8, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x4, #0x1", "rmif x21, #63, #nzCv", "ubfx w21, w4, #1, #15", @@ -1449,7 +1449,7 @@ "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x4, #0x1", "rmif x21, #63, #nzCv", "extr w4, w20, w4, #1", @@ -1461,7 +1461,7 @@ "ExpectedInstructionCount": 6, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x4, #0x1", "rmif x21, #63, #nzCv", "extr x4, x20, x4, #1", @@ -1622,25 +1622,25 @@ "cbz x20, #+0x68", "and x20, x7, #0x1f", "uxtb w21, w4", - "mov w22, #0x0", - "cset w23, lo", - "bfi x22, x21, #55, #8", - "bfi x22, x23, #63, #1", - "bfi x22, x21, #46, #8", - "bfi x22, x23, #54, #1", - "bfi x22, x21, #37, #8", - "bfi x22, x23, #45, #1", - "bfi x22, x21, #28, #8", - "bfi x22, x23, #36, #1", - "bfi x22, x21, #19, #8", - "bfi x22, x23, #27, #1", - "bfxil x22, x21, #0, #8", + "cset x22, lo", + "mov w23, #0x0", + "bfi x23, x21, #55, #8", + "bfi x23, x22, #63, #1", + "bfi x23, x21, #46, #8", + "bfi x23, x22, #54, #1", + "bfi x23, x21, #37, #8", + "bfi x23, x22, #45, #1", + "bfi x23, x21, #28, #8", + "bfi x23, x22, #36, #1", + "bfi x23, x21, #19, #8", + "bfi x23, x22, #27, #1", + "bfxil x23, x21, #0, #8", "neg x21, x20", - "ror x21, x22, x21", + "ror x21, x23, x21", "bfxil x4, x21, #0, #8", - "mov w23, #0x3f", - "sub x20, x23, x20", - "ror x20, x22, x20", + "mov w22, #0x3f", + "sub x20, x22, x20", + "ror x20, x23, x20", "eor x22, x20, #0x1", "rmif x22, #63, #nzCv", "eor x20, x20, x21, lsr #7", @@ -1654,7 +1654,7 @@ "and x20, x7, #0x1f", "cbz x20, #+0x40", "and x20, x7, #0x1f", - "cset w21, lo", + "cset x21, lo", "uxtb w22, w4", "bfi x22, x21, #8, #1", "bfi x22, x22, #9, #9", @@ -1817,21 +1817,21 @@ "cbz x20, #+0x58", "and x20, x7, #0x1f", "uxth w21, w4", - "mov w22, #0x0", - "cset w23, lo", - "bfi x22, x21, #47, #16", - "bfi x22, x23, #63, #1", - "bfi x22, x21, #30, #16", - "bfi x22, x23, #46, #1", - "bfi x22, x21, #13, #16", - "bfi x22, x23, #29, #1", - "bfxil x22, x21, #0, #16", + "cset x22, lo", + "mov w23, #0x0", + "bfi x23, x21, #47, #16", + "bfi x23, x22, #63, #1", + "bfi x23, x21, #30, #16", + "bfi x23, x22, #46, #1", + "bfi x23, x21, #13, #16", + "bfi x23, x22, #29, #1", + "bfxil x23, x21, #0, #16", "neg x21, x20", - "ror x21, x22, x21", + "ror x21, x23, x21", "bfxil x4, x21, #0, #16", - "mov w23, #0x3f", - "sub x20, x23, x20", - "ror x20, x22, x20", + "mov w22, #0x3f", + "sub x20, x22, x20", + "ror x20, x23, x20", "eor x22, x20, #0x1", "rmif x22, #63, #nzCv", "eor x20, x20, x21, lsr #15", @@ -1845,7 +1845,7 @@ "and w20, w7, #0x1f", "cbz x20, #+0x3c", "lsl w20, w4, w7", - "cset w21, lo", + "cset x21, lo", "neg w22, w7", "lsr w23, w4, w22", "orr w20, w20, w23, lsr #1", @@ -1868,7 +1868,7 @@ "and x20, x7, #0x3f", "cbz x20, #+0x38", "lsl x20, x4, x7", - "cset w21, lo", + "cset x21, lo", "neg x22, x7", "lsr x23, x4, x22", "orr x20, x20, x23, lsr #1", @@ -1889,7 +1889,7 @@ "and x20, x7, #0x1f", "cbz x20, #+0x3c", "and x20, x7, #0x1f", - "cset w21, lo", + "cset x21, lo", "uxth w22, w4", "bfi x22, x21, #16, #1", "bfi x22, x22, #17, #17", @@ -1911,7 +1911,7 @@ "and w20, w7, #0x1f", "cbz x20, #+0x3c", "lsr w20, w4, w7", - "cset w21, lo", + "cset x21, lo", "neg w22, w7", "lsl w23, w4, w22", "orr w20, w20, w23, lsl #1", @@ -1934,7 +1934,7 @@ "and x20, x7, #0x3f", "cbz x20, #+0x38", "lsr x20, x4, x7", - "cset w21, lo", + "cset x21, lo", "neg x22, x7", "lsl x23, x4, x22", "orr x20, x20, x23, lsl #1", @@ -2386,7 +2386,7 @@ "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "adds w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x27, x4", @@ -2397,7 +2397,7 @@ "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "adds x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x27, x4", @@ -2420,7 +2420,7 @@ "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "subs w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x27, x4", @@ -2431,7 +2431,7 @@ "ExpectedInstructionCount": 5, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "subs x26, x4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x27, x4", diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json index 35c409c78..1b5828935 100644 --- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json @@ -107,7 +107,7 @@ "Comment": "0x27", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, hs", + "cset x21, hs", "and x22, x20, #0xf", "cmp x22, #0x9 (9)", "cset x22, hi", @@ -134,7 +134,7 @@ "Comment": "0x2f", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, lo", + "cset x21, lo", "and x22, x20, #0xf", "cmp x22, #0x9 (9)", "cset x22, hi", @@ -214,7 +214,7 @@ "ExpectedInstructionCount": 5, "Comment": "0x40", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "adds w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x27, x4", @@ -251,7 +251,7 @@ "ExpectedInstructionCount": 5, "Comment": "0x48", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "subs w26, w4, #0x1 (1)", "rmif x20, #63, #nzCv", "mov x27, x4", @@ -310,7 +310,7 @@ "ExpectedInstructionCount": 39, "Comment": "0x9c", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x27, x26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -321,7 +321,7 @@ "ldrsb x21, [x28, #986]", "lsr x21, x21, #63", "orr x20, x20, x21, lsl #10", - "cset w21, vs", + "cset x21, vs", "orr x20, x20, x21, lsl #11", "ldrb w21, [x28, #988]", "orr x20, x20, x21, lsl #12", @@ -355,7 +355,7 @@ "ExpectedInstructionCount": 39, "Comment": "0x9c", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x27, x26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -366,7 +366,7 @@ "ldrsb x21, [x28, #986]", "lsr x21, x21, #63", "orr x20, x20, x21, lsl #10", - "cset w21, vs", + "cset x21, vs", "orr x20, x20, x21, lsl #11", "ldrb w21, [x28, #988]", "orr x20, x20, x21, lsl #12", diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 519372be3..a83318405 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -18,8 +18,8 @@ "Comment": "0x0f 0x2e", "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, @@ -28,8 +28,8 @@ "Comment": "0x0f 0x2f", "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index 925cfd474..834a65c82 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -739,9 +739,9 @@ "ExpectedArm64ASM": [ "mrs x20, rndr", "bfxil x4, x20, #0, #16", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "rmif x20, #63, #NZCV" ] }, @@ -751,9 +751,9 @@ "ExpectedArm64ASM": [ "mrs x20, rndr", "mov w4, w20", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "rmif x20, #63, #NZCV" ] }, @@ -762,9 +762,9 @@ "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x4, rndr", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "rmif x20, #63, #NZCV" ] }, @@ -774,9 +774,9 @@ "ExpectedArm64ASM": [ "mrs x20, rndrrs", "bfxil x4, x20, #0, #16", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "rmif x20, #63, #NZCV" ] }, @@ -786,9 +786,9 @@ "ExpectedArm64ASM": [ "mrs x20, rndrrs", "mov w4, w20", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "rmif x20, #63, #NZCV" ] }, @@ -797,9 +797,9 @@ "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x4, rndrrs", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "rmif x20, #63, #NZCV" ] }, diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index 9ef435017..24bab0a35 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -18,8 +18,8 @@ "Comment": "0x66 0x0f 0x2e", "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, @@ -28,8 +28,8 @@ "Comment": "0x66 0x0f 0x2f", "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index ffea7abac..3a83d6adc 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -21,8 +21,8 @@ ], "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, @@ -33,8 +33,8 @@ ], "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, @@ -45,8 +45,8 @@ ], "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, @@ -57,8 +57,8 @@ ], "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "axflag" ] }, diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json index 75643e686..f357ee6e5 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map2.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json @@ -29,11 +29,11 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vtestps ymm0, ymm1": { @@ -53,11 +53,11 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vtestpd xmm0, xmm1": { @@ -77,11 +77,11 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vtestpd ymm0, ymm1": { @@ -101,11 +101,11 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vptest xmm0, xmm1": { @@ -121,11 +121,11 @@ "umov w20, v2.h[0]", "umov w21, v3.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vptest ymm0, ymm1": { @@ -141,11 +141,11 @@ "umov w20, v2.h[0]", "umov w21, v3.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", - "rmif x21, #63, #nzCv" + "rmif x21, #63, #nzCv", + "mov w26, #0x1" ] }, "vmaskmovps xmm0, xmm1, [rax]": { @@ -375,7 +375,7 @@ "bic w20, w6, w20", "tst x7, #0xe0", "csel w4, w6, w20, ne", - "cset w20, eq", + "cset x20, eq", "cmp w4, #0x0 (0)", "rmif x20, #63, #nzCv" ] @@ -391,7 +391,7 @@ "bic x20, x6, x20", "tst x7, #0xc0", "csel x4, x6, x20, ne", - "cset w20, eq", + "cset x20, eq", "cmp x4, #0x0 (0)", "rmif x20, #63, #nzCv" ] diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json index ae3b5f61a..d720aeff7 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map_group.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json @@ -76,7 +76,7 @@ "neg w20, w6", "and w4, w6, w20", "cmp w4, #0x0 (0)", - "cset w20, eq", + "cset x20, eq", "rmif x20, #63, #nzCv" ] }, @@ -89,7 +89,7 @@ "neg x20, x6", "and x4, x6, x20", "cmp x4, #0x0 (0)", - "cset w20, eq", + "cset x20, eq", "rmif x20, #63, #nzCv" ] } diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index 5c8af33aa..4a2a60f07 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -481,26 +481,26 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q4, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q7, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "mov w23, #0x8", - "sub w20, w23, w20", - "ldrb w23, [x28, #1426]", - "mov w12, #0x707", - "lsr w20, w12, w20", - "orr w20, w23, w20", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "mov w22, #0x8", + "sub w20, w22, w20", + "ldrb w22, [x28, #1426]", + "mov w23, #0x707", + "lsr w20, w23, w20", + "orr w20, w22, w20", "strb w20, [x28, #1426]", "ldrb w20, [x28, #1426]", - "lsl w21, w21, w22", + "mov w22, #0x1", + "lsl w21, w22, w21", "bic w20, w20, w21", "strb w20, [x28, #1426]" ] @@ -743,22 +743,22 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x6 (6)", - "and w22, w22, #0x7", - "mov w23, #0x8", - "sub w20, w23, w20", - "ldrb w23, [x28, #1426]", - "mov w12, #0x303", - "lsr w20, w12, w20", - "orr w20, w23, w20", + "add w21, w20, #0x6 (6)", + "and w21, w21, #0x7", + "mov w22, #0x8", + "sub w20, w22, w20", + "ldrb w22, [x28, #1426]", + "mov w23, #0x303", + "lsr w20, w23, w20", + "orr w20, w22, w20", "strb w20, [x28, #1426]", "ldrb w20, [x28, #1426]", - "lsl w21, w21, w22", + "mov w22, #0x1", + "lsl w21, w22, w21", "bic w20, w20, w21", "strb w20, [x28, #1426]" ] @@ -1003,27 +1003,26 @@ "ldr x30, [sp], #16", "mov v2.16b, v0.16b", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w23, w20", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w20, w23, w20", + "orr w20, w22, w20", "strb w20, [x28, #1426]", "ldrb w20, [x28, #1426]", - "lsl w21, w21, w22", + "lsl w21, w23, w21", "bic w20, w20, w21", "strb w20, [x28, #1426]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -1035,12 +1034,13 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -1054,9 +1054,9 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x10]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -1876,30 +1876,30 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q5, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q4, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q3, [x0, #1040]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x7 (7)", - "and w22, w22, #0x7", - "mov w23, #0x8", - "sub w20, w23, w20", - "ldrb w23, [x28, #1426]", - "mov w12, #0xf0f", - "lsr w20, w12, w20", - "orr w20, w23, w20", + "add w21, w20, #0x7 (7)", + "and w21, w21, #0x7", + "mov w22, #0x8", + "sub w20, w22, w20", + "ldrb w22, [x28, #1426]", + "mov w23, #0xf0f", + "lsr w20, w23, w20", + "orr w20, w22, w20", "strb w20, [x28, #1426]", "ldrb w20, [x28, #1426]", - "lsl w21, w21, w22", + "mov w22, #0x1", + "lsl w21, w22, w21", "bic w20, w20, w21", "strb w20, [x28, #1426]" ] @@ -2147,27 +2147,26 @@ "ldr x30, [sp], #16", "mov v2.16b, v0.16b", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x4 (4)", - "and w22, w22, #0x7", - "ldrb w23, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w23, w20", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w20, w23, w20", + "orr w20, w22, w20", "strb w20, [x28, #1426]", "ldrb w20, [x28, #1426]", - "lsl w21, w21, w22", + "lsl w21, w23, w21", "bic w20, w20, w21", "strb w20, [x28, #1426]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -2191,9 +2190,10 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x11]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -2232,15 +2232,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", @@ -2437,15 +2437,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 0d3b9ea17..41f6f0b48 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -17712,12 +17712,12 @@ "sub w20, w20, w21", "str w20, [x8, #-4]!", "ldrb w21, [x28, #1019]", - "mov w22, #0x1", "add w21, w21, #0x1 (1)", "and w21, w21, #0x7", - "ldrb w23, [x28, #1426]", - "lsl w21, w22, w21", - "bic w21, w23, w21", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w21, w23, w21", + "bic w21, w22, w21", "strb w21, [x28, #1426]" ] }, @@ -20226,7 +20226,7 @@ "mov w22, #0x0", "cmp x20, #0x0 (0)", "mov w23, #0x8000", - "csel x12, x23, xzr, lt", + "csel x12, x23, x22, lt", "cneg x20, x20, mi", "mov w13, #0x3f", "mov x0, #0x3f", @@ -20277,7 +20277,7 @@ "sxtw x20, w20", "mrs x21, nzcv", "cmp x20, #0x0 (0)", - "csel x23, x23, xzr, lt", + "csel x23, x23, x22, lt", "cneg x20, x20, mi", "mov x0, #0x3f", "clz x12, x20", @@ -26201,12 +26201,12 @@ "fmov s2, s0", "str s2, [x7]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -26549,15 +26549,15 @@ "sub w20, w20, w21", "str w20, [x8, #-4]!", "ldrb w21, [x28, #1019]", - "mov w22, #0x1", "sub w21, w21, #0x1 (1)", "and w21, w21, #0x7", "strb w21, [x28, #1019]", "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1426]", - "lsl w21, w22, w21", - "orr w21, w23, w21", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w21, w23, w21", + "orr w21, w22, w21", "strb w21, [x28, #1426]" ] }, diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index a031621ce..fbd30bf48 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -9475,12 +9475,12 @@ "cfinv", "mov x8, x26", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -15384,7 +15384,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "cset w21, hs", + "cset x21, hs", "subs w26, w9, #0x1 (1)", "rmif x21, #63, #nzCv", "mov x27, x9", @@ -20964,7 +20964,7 @@ "orr w21, w21, w23", "strb w21, [x28, #1426]", "subs w6, w6, #0x10 (16)", - "cset w21, hs", + "cset x21, hs", "subs w26, w9, #0x1 (1)", "rmif x21, #63, #nzCv", "mov x27, x9", @@ -27034,16 +27034,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "add w11, w10, w7, lsl #1", "ldr s2, [x8, #64]", "str x30, [sp, #-16]!", @@ -27098,10 +27098,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #64]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -27152,10 +27152,10 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #44]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -27172,10 +27172,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #64]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -27226,15 +27226,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #40]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", - "ldur s2, [x22, #-8]", + "add w21, w4, w10, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27247,12 +27247,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w6, lsl #2", - "ldr s2, [x22]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w6, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27272,8 +27272,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", - "ldur s2, [x22, #-4]", + "add w21, w4, w7, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27286,18 +27286,18 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "ldr q3, [x28, #3456]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w10, lsl #2", - "ldur s2, [x22, #-4]", + "add w21, w4, w10, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27317,8 +27317,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w6, lsl #2", - "ldr s2, [x22]", + "add w21, w4, w6, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27331,12 +27331,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldur s2, [x22, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27366,15 +27366,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", - "ldur s2, [x22, #-4]", + "add w21, w4, w10, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27387,12 +27387,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w7, lsl #2", - "ldur s2, [x22, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w7, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27422,15 +27422,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #28]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldur s2, [x22, #-8]", + "add w21, w4, w5, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27443,12 +27443,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldur s2, [x22, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27468,8 +27468,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", - "ldur s2, [x22, #-4]", + "add w21, w4, w5, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27482,12 +27482,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldur s2, [x22, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27517,15 +27517,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldur s2, [x22, #-8]", + "add w21, w4, w5, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27538,12 +27538,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldur s2, [x22, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27573,15 +27573,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #32]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldur s2, [x22, #-4]", + "add w21, w4, w5, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27594,12 +27594,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldur s2, [x22, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -27629,10 +27629,10 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -27643,13 +27643,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27663,7 +27663,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w6, lsl #2", + "add w21, w4, w6, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -27673,27 +27673,27 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #16]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -27714,7 +27714,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", + "add w21, w4, w7, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -27724,26 +27724,26 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27757,7 +27757,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -27767,28 +27767,28 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w23, [x28, #1426]", - "lsl w22, w21, w22", - "orr w22, w23, w22", - "strb w22, [x28, #1426]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "lsl w21, w22, w21", + "orr w21, w23, w21", + "strb w21, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -27805,13 +27805,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27825,7 +27825,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -27835,18 +27835,18 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -27863,10 +27863,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #20]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -27900,10 +27900,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #28]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -27924,22 +27924,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27953,22 +27953,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -27984,9 +27984,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -27996,16 +27996,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -28015,30 +28015,30 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28052,22 +28052,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28083,9 +28083,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -28095,16 +28095,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -28114,25 +28114,25 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -28149,10 +28149,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #24]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -28186,10 +28186,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #32]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -28223,13 +28223,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28256,13 +28256,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28278,9 +28278,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -28290,16 +28290,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -28309,11 +28309,11 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -28330,13 +28330,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28363,13 +28363,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28385,9 +28385,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -28397,16 +28397,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -28416,30 +28416,30 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28452,12 +28452,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28477,8 +28477,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #4]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28491,18 +28491,18 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "ldr q3, [x28, #3456]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #4]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28522,8 +28522,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28536,12 +28536,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28571,15 +28571,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #4]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28592,12 +28592,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28627,15 +28627,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #28]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28648,12 +28648,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28673,8 +28673,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #4]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28687,12 +28687,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28722,15 +28722,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28743,12 +28743,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28778,15 +28778,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #32]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #4]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28799,12 +28799,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -28834,10 +28834,10 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -28848,13 +28848,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28868,7 +28868,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", + "add w21, w4, w7, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -28878,27 +28878,27 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #16]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -28919,7 +28919,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", + "add w21, w4, w7, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -28929,26 +28929,26 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -28962,7 +28962,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -28972,28 +28972,28 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w23, [x28, #1426]", - "lsl w22, w21, w22", - "orr w22, w23, w22", - "strb w22, [x28, #1426]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "lsl w21, w22, w21", + "orr w21, w23, w21", + "strb w21, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -29010,13 +29010,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29030,7 +29030,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -29040,18 +29040,18 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -29068,10 +29068,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #20]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -29105,10 +29105,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #28]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -29129,22 +29129,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29178,7 +29178,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -29188,17 +29188,17 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29232,7 +29232,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -29242,18 +29242,18 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -29270,10 +29270,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #24]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -29307,10 +29307,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #32]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -29344,32 +29344,32 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "ldr q3, [x28, #3456]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29383,9 +29383,9 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29399,7 +29399,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -29409,23 +29409,23 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", "add w23, w20, #0x2 (2)", @@ -29444,7 +29444,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29458,7 +29458,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -29468,30 +29468,30 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #8]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29504,12 +29504,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29529,8 +29529,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #12]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29543,18 +29543,18 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "ldr q3, [x28, #3456]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #12]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29574,8 +29574,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #8]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29588,12 +29588,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29623,15 +29623,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #12]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29644,12 +29644,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29679,15 +29679,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #28]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #8]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29700,12 +29700,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29725,8 +29725,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #12]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29739,12 +29739,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29774,15 +29774,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #8]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29795,12 +29795,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29830,15 +29830,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #32]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #12]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29851,12 +29851,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -29886,10 +29886,10 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -29900,13 +29900,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -29920,7 +29920,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", + "add w21, w4, w7, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -29930,27 +29930,27 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #16]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -29971,7 +29971,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", + "add w21, w4, w7, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -29981,26 +29981,26 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #12]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30014,7 +30014,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -30024,28 +30024,28 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w23, [x28, #1426]", - "lsl w22, w21, w22", - "orr w22, w23, w22", - "strb w22, [x28, #1426]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "lsl w21, w22, w21", + "orr w21, w23, w21", + "strb w21, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -30062,13 +30062,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30082,7 +30082,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -30092,18 +30092,18 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #12]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -30120,10 +30120,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #20]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -30157,10 +30157,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #28]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -30181,22 +30181,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30210,22 +30210,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x4 (4)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30241,9 +30241,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -30253,16 +30253,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -30272,26 +30272,26 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30307,13 +30307,13 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", "add w23, w20, #0x1 (1)", @@ -30334,7 +30334,7 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -30344,27 +30344,27 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -30374,25 +30374,25 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #12]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -30409,10 +30409,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #24]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -30446,10 +30446,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #32]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -30483,13 +30483,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30516,13 +30516,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30538,9 +30538,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -30550,16 +30550,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -30569,11 +30569,11 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -30590,13 +30590,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30623,13 +30623,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -30645,9 +30645,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -30657,16 +30657,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -30676,26 +30676,26 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #12]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldp w11, w10, [x8], #8", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w9, [x8], #4", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -30987,16 +30987,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "add w11, w10, w7, lsl #1", "ldr s2, [x8, #64]", "str x30, [sp, #-16]!", @@ -31051,10 +31051,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #64]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -31105,10 +31105,10 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #48]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -31125,10 +31125,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #64]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -31179,15 +31179,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #44]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", - "ldur s2, [x22, #-8]", + "add w21, w4, w10, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31200,12 +31200,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w6, lsl #2", - "ldr s2, [x22]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w6, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31225,8 +31225,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", - "ldur s2, [x22, #-4]", + "add w21, w4, w7, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31239,12 +31239,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldur s2, [x22, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31264,8 +31264,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w6, lsl #2", - "ldr s2, [x22]", + "add w21, w4, w6, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31278,12 +31278,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldur s2, [x22, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31313,15 +31313,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w7, lsl #2", - "ldur s2, [x22, #-4]", + "add w21, w4, w7, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31334,12 +31334,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldur s2, [x22, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31369,15 +31369,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #28]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", - "ldur s2, [x22, #-8]", + "add w21, w4, w11, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31390,12 +31390,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w5, lsl #2", - "ldur s2, [x22, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w5, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31415,8 +31415,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", - "ldur s2, [x22, #-4]", + "add w21, w4, w5, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31429,12 +31429,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldur s2, [x22, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31464,15 +31464,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldur s2, [x22, #-8]", + "add w21, w4, w5, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31485,12 +31485,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldur s2, [x22, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldur s2, [x21, #-8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31520,15 +31520,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #32]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldur s2, [x22, #-4]", + "add w21, w4, w5, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31541,12 +31541,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldur s2, [x22, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldur s2, [x21, #-4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -31576,10 +31576,10 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -31590,13 +31590,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -31610,7 +31610,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w6, lsl #2", + "add w21, w4, w6, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -31620,11 +31620,11 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -31641,13 +31641,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -31661,7 +31661,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", + "add w21, w4, w7, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -31671,26 +31671,26 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -31704,7 +31704,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -31714,28 +31714,28 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w23, [x28, #1426]", - "lsl w22, w21, w22", - "orr w22, w23, w22", - "strb w22, [x28, #1426]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "lsl w21, w22, w21", + "orr w21, w23, w21", + "strb w21, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -31759,7 +31759,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -31769,11 +31769,11 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -31790,10 +31790,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #20]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -31827,10 +31827,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #28]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -31851,22 +31851,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -31880,22 +31880,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -31911,9 +31911,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -31923,16 +31923,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -31942,30 +31942,30 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -31979,22 +31979,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -32010,9 +32010,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -32022,16 +32022,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -32041,25 +32041,25 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32076,10 +32076,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #24]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -32113,10 +32113,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #32]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -32150,13 +32150,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -32183,13 +32183,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -32205,9 +32205,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -32217,16 +32217,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -32236,11 +32236,11 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32257,13 +32257,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -32290,13 +32290,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -32312,9 +32312,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -32324,16 +32324,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -32343,30 +32343,30 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "stur s2, [x22, #-4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "stur s2, [x21, #-4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32379,12 +32379,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32404,8 +32404,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #4]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32418,12 +32418,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32443,8 +32443,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32457,12 +32457,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32492,15 +32492,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #4]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32513,12 +32513,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32548,15 +32548,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #28]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32569,12 +32569,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32594,8 +32594,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #4]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32608,12 +32608,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32643,15 +32643,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32664,12 +32664,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32699,15 +32699,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #32]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #4]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32720,12 +32720,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #4]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -32755,10 +32755,10 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32769,13 +32769,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -32789,7 +32789,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", + "add w21, w4, w7, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -32799,11 +32799,11 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32820,13 +32820,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -32840,7 +32840,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", + "add w21, w4, w7, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -32850,26 +32850,26 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -32883,7 +32883,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -32893,28 +32893,28 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w23, [x28, #1426]", - "lsl w22, w21, w22", - "orr w22, w23, w22", - "strb w22, [x28, #1426]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "lsl w21, w22, w21", + "orr w21, w23, w21", + "strb w21, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32938,7 +32938,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -32948,11 +32948,11 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -32969,10 +32969,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #20]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -33006,10 +33006,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #28]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -33030,22 +33030,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -33079,7 +33079,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -33089,17 +33089,17 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -33133,7 +33133,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -33143,18 +33143,18 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -33171,10 +33171,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #24]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -33208,10 +33208,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #32]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -33245,32 +33245,32 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "ldr q3, [x28, #3456]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -33284,9 +33284,9 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -33300,7 +33300,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -33310,23 +33310,23 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", "add w23, w20, #0x2 (2)", @@ -33345,7 +33345,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -33359,7 +33359,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -33369,30 +33369,30 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #4]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #4]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #8]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33405,12 +33405,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33430,8 +33430,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #12]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33444,12 +33444,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33469,8 +33469,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #8]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33483,12 +33483,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33518,15 +33518,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #24]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w7, lsl #2", - "ldr s2, [x22, #12]", + "add w21, w4, w7, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33539,12 +33539,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w10, lsl #2", - "ldr s2, [x22, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w10, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33574,15 +33574,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #28]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #8]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33595,12 +33595,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33620,8 +33620,8 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #12]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33634,12 +33634,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33669,15 +33669,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #16]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #8]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33690,12 +33690,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #8]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33725,15 +33725,15 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #32]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w5, lsl #2", - "ldr s2, [x22, #12]", + "add w21, w4, w5, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33746,12 +33746,12 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w4, w11, lsl #2", - "ldr s2, [x22, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w4, w11, lsl #2", + "ldr s2, [x21, #12]", "str x30, [sp, #-16]!", "fmov s0, s2", "ldr x0, [x28, #1560]", @@ -33781,10 +33781,10 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x8, #20]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -33795,13 +33795,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -33815,7 +33815,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", + "add w21, w4, w7, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -33825,11 +33825,11 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -33846,13 +33846,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -33866,7 +33866,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w7, lsl #2", + "add w21, w4, w7, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -33876,26 +33876,26 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #12]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -33909,7 +33909,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -33919,28 +33919,28 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "ldrb w23, [x28, #1426]", - "lsl w22, w21, w22", - "orr w22, w23, w22", - "strb w22, [x28, #1426]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "lsl w21, w22, w21", + "orr w21, w23, w21", + "strb w21, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -33964,7 +33964,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w4, w5, lsl #2", + "add w21, w4, w5, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -33974,11 +33974,11 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #12]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -33995,10 +33995,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #20]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -34032,10 +34032,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #28]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -34056,22 +34056,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -34085,22 +34085,22 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "add w22, w20, #0x4 (4)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x4 (4)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -34116,9 +34116,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -34128,16 +34128,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -34147,26 +34147,26 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -34182,13 +34182,13 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", "add w23, w20, #0x1 (1)", @@ -34209,7 +34209,7 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -34219,27 +34219,27 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x2 (2)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x2 (2)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", "strb wzr, [x28, #1017]", - "add w22, w4, w10, lsl #2", + "add w21, w4, w10, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -34249,25 +34249,25 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #12]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -34284,10 +34284,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #24]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -34321,10 +34321,10 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", "ldr s2, [x8, #32]", "str x30, [sp, #-16]!", "fmov s0, s2", @@ -34358,13 +34358,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -34391,13 +34391,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -34413,9 +34413,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -34425,16 +34425,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -34444,11 +34444,11 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #8]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #8]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", @@ -34465,13 +34465,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -34498,13 +34498,13 @@ "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "orr w22, w22, w23", - "strb w22, [x28, #1426]", - "add w22, w20, #0x3 (3)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "orr w21, w21, w23", + "strb w21, [x28, #1426]", + "add w21, w20, #0x3 (3)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -34520,9 +34520,9 @@ "str q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -34532,16 +34532,16 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "add w22, w4, w11, lsl #2", + "add w21, w4, w11, lsl #2", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", "str x30, [sp, #-16]!", @@ -34551,26 +34551,26 @@ "blr x0", "ldr x30, [sp], #16", "fmov s2, s0", - "str s2, [x22, #12]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "str s2, [x21, #12]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldp w11, w10, [x8], #8", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "ldr w9, [x8], #4", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 342ee527d..fd77709fb 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -964,10 +964,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -976,19 +975,20 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -2042,15 +2042,15 @@ "ldr x30, [sp], #16", "mov v2.16b, v0.16b", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2199,15 +2199,15 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2218,19 +2218,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2245,15 +2245,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2268,15 +2268,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2291,15 +2291,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2314,15 +2314,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2337,15 +2337,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2360,15 +2360,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2604,7 +2604,7 @@ "lsr w20, w21, w20", "and w20, w20, #0x1", "mrs x21, nzcv", - "cmp x20, #0x1 (1)", + "cmp w20, #0x1 (1)", "cset x22, ne", "strb w22, [x28, #1016]", "strb w20, [x28, #1018]", @@ -2620,15 +2620,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3232]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2640,15 +2640,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3248]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2660,15 +2660,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3264]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2680,15 +2680,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3280]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2700,15 +2700,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3296]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2720,15 +2720,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3312]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2740,15 +2740,15 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2819,15 +2819,15 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldr q2, [x28, #3232]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]", "strb wzr, [x28, #1018]" ] @@ -3067,15 +3067,15 @@ "mov v4.16b, v1.16b", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q4, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]", "strb wzr, [x28, #1018]" ] @@ -4086,10 +4086,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -4098,26 +4097,27 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -4136,7 +4136,7 @@ "mov w22, #0x0", "cmp x20, #0x0 (0)", "mov w23, #0x8000", - "csel x23, x23, xzr, lt", + "csel x23, x23, x22, lt", "cneg x20, x20, mi", "mov w24, #0x3f", "mov x0, #0x3f", @@ -4153,15 +4153,15 @@ "fmov v2.D[1], x20", "msr nzcv, x21", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -4248,15 +4248,15 @@ "add x20, x4, #0x8 (8)", "ld1 {v2.h}[4], [x20]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -6938,15 +6938,15 @@ "ldr x30, [sp], #16", "mov v2.16b, v0.16b", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -7330,12 +7330,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -7451,14 +7451,14 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -7589,15 +7589,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -7610,18 +7610,18 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1426]", - "lsl w22, w21, w22", - "orr w22, w23, w22", - "strb w22, [x28, #1426]", "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov w23, #0x1", + "lsl w21, w23, w21", + "orr w21, w22, w21", + "strb w21, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w22, w23, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8091,10 +8091,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8103,19 +8102,20 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8656,10 +8656,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -8669,11 +8668,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8918,10 +8918,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -8931,11 +8930,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -9149,10 +9149,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -9161,26 +9160,27 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -9227,10 +9227,9 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -9242,11 +9241,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -9493,10 +9493,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -9506,11 +9505,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -9755,10 +9755,9 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -9770,11 +9769,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -10021,10 +10021,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -10034,11 +10033,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -10255,7 +10255,7 @@ "mov w22, #0x0", "cmp x20, #0x0 (0)", "mov w23, #0x8000", - "csel x23, x23, xzr, lt", + "csel x23, x23, x22, lt", "cneg x20, x20, mi", "mov w24, #0x3f", "mov x0, #0x3f", @@ -10272,15 +10272,15 @@ "fmov v2.D[1], x20", "msr nzcv, x21", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -10407,15 +10407,15 @@ "ldr x30, [sp], #16", "mov v2.16b, v0.16b", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -10612,10 +10612,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -10624,19 +10623,20 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "eor x23, x23, #0x1", - "rmif x23, #63, #nzCv", - "rmif x24, #62, #nZcv", - "eor w26, w22, #0x1", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "eor x22, x22, #0x1", + "rmif x22, #63, #nzCv", + "rmif x23, #62, #nZcv", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -10930,10 +10930,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -10942,19 +10941,20 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "eor x23, x23, #0x1", - "rmif x23, #63, #nzCv", - "rmif x24, #62, #nZcv", - "eor w26, w22, #0x1", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "eor x22, x22, #0x1", + "rmif x22, #63, #nzCv", + "rmif x23, #62, #nZcv", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 3df2a65e6..f85b31d4e 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -60,10 +60,10 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w21, vs", + "cset x21, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", @@ -84,10 +84,10 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -464,10 +464,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -490,10 +490,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -516,10 +516,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -542,10 +542,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -568,10 +568,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -594,10 +594,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -620,10 +620,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -646,10 +646,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -670,10 +670,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -696,31 +696,31 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mrs x22, nzcv", + "mrs x21, nzcv", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w23, vs", + "cset x22, vs", "axflag", - "cset w24, lo", - "cset w30, eq", - "strb w24, [x28, #1016]", + "cset x23, lo", + "cset x24, eq", + "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w23, [x28, #1018]", - "strb w30, [x28, #1022]", - "ldrb w23, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w23, w21", - "strb w21, [x28, #1426]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x21" ] }, "fcomp st0, st2": { @@ -738,10 +738,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -772,10 +772,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -806,10 +806,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -840,10 +840,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -874,10 +874,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -908,10 +908,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -1504,15 +1504,15 @@ "ldr s2, [x4]", "fcvt d2, s2", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1663,15 +1663,15 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1682,19 +1682,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1709,15 +1709,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1732,15 +1732,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1755,15 +1755,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1778,15 +1778,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1801,15 +1801,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1824,15 +1824,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2033,10 +2033,10 @@ "mov w21, #0x0", "fmov d3, x21", "fcmp d2, d3", - "cset w21, vs", + "cset x21, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", @@ -2060,7 +2060,7 @@ "lsr w20, w21, w20", "and w20, w20, #0x1", "mrs x21, nzcv", - "cmp x20, #0x1 (1)", + "cmp w20, #0x1 (1)", "cset x22, ne", "strb w22, [x28, #1016]", "strb w20, [x28, #1018]", @@ -2077,15 +2077,15 @@ "mov x20, #0x3ff0000000000000", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2101,15 +2101,15 @@ "movk x20, #0x400a, lsl #48", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2125,15 +2125,15 @@ "movk x20, #0x3ff7, lsl #48", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2149,15 +2149,15 @@ "movk x20, #0x4009, lsl #48", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2173,15 +2173,15 @@ "movk x20, #0x3fd3, lsl #48", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2197,15 +2197,15 @@ "movk x20, #0x3fe6, lsl #48", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2218,15 +2218,15 @@ "mov w20, #0x0", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2298,15 +2298,15 @@ "str d2, [x0, #1040]", "mov x21, #0x3ff0000000000000", "fmov d2, x21", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]", "strb wzr, [x28, #1018]" ] @@ -2534,15 +2534,15 @@ "fmov d4, d1", "add x0, x28, x20, lsl #4", "str d3, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d4, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]", "strb wzr, [x28, #1018]" ] @@ -2673,10 +2673,10 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w21, vs", + "cset x21, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", @@ -2697,10 +2697,10 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -3443,38 +3443,38 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mrs x22, nzcv", + "mrs x21, nzcv", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w23, vs", + "cset x22, vs", "axflag", - "cset w24, lo", - "cset w30, eq", - "strb w24, [x28, #1016]", + "cset x23, lo", + "cset x24, eq", + "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w23, [x28, #1018]", - "strb w30, [x28, #1022]", - "ldrb w23, [x28, #1426]", - "lsl w24, w21, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1426]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w23, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w23, w21", - "strb w21, [x28, #1426]", + "ldrb w22, [x28, #1426]", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x21" ] }, "fild dword [rax]": { @@ -3486,15 +3486,15 @@ "ldr w20, [x4]", "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -3570,15 +3570,15 @@ "ldr x30, [sp], #16", "fmov d2, d0", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -4310,7 +4310,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4328,7 +4328,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4346,7 +4346,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4364,7 +4364,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4382,7 +4382,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4400,7 +4400,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4418,7 +4418,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4436,7 +4436,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4452,7 +4452,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4470,7 +4470,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4488,7 +4488,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4506,7 +4506,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4524,7 +4524,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4542,7 +4542,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4560,7 +4560,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4578,7 +4578,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag" ] }, @@ -4624,10 +4624,10 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w21, vs", + "cset x21, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", @@ -4647,10 +4647,10 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -5598,15 +5598,15 @@ "ExpectedArm64ASM": [ "ldr d2, [x4]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -6002,12 +6002,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -6123,14 +6123,14 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -6261,15 +6261,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -6282,18 +6282,18 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w23, [x28, #1426]", - "lsl w22, w21, w22", - "orr w22, w23, w22", - "strb w22, [x28, #1426]", "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov w23, #0x1", + "lsl w21, w23, w21", + "orr w21, w22, w21", + "strb w21, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w22, w23, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -6475,10 +6475,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -6501,10 +6501,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -6527,10 +6527,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -6553,10 +6553,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -6579,10 +6579,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -6605,10 +6605,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -6631,10 +6631,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -6657,10 +6657,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", + "cset x20, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w20, [x28, #1018]", @@ -6681,10 +6681,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -6707,31 +6707,31 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mrs x22, nzcv", + "mrs x21, nzcv", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w23, vs", + "cset x22, vs", "axflag", - "cset w24, lo", - "cset w30, eq", - "strb w24, [x28, #1016]", + "cset x23, lo", + "cset x24, eq", + "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w23, [x28, #1018]", - "strb w30, [x28, #1022]", - "ldrb w23, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w23, w21", - "strb w21, [x28, #1426]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x21" ] }, "fucomp st2": { @@ -6749,10 +6749,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -6783,10 +6783,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -6817,10 +6817,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -6851,10 +6851,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -6885,10 +6885,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -6919,10 +6919,10 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -6986,10 +6986,10 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w21, vs", + "cset x21, vs", "axflag", - "cset w22, lo", - "cset w23, eq", + "cset x22, lo", + "cset x23, eq", "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w21, [x28, #1018]", @@ -7011,10 +7011,10 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", + "cset x22, vs", "axflag", - "cset w23, lo", - "cset w24, eq", + "cset x23, lo", + "cset x24, eq", "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", "strb w22, [x28, #1018]", @@ -7131,17 +7131,17 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fadd d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7337,17 +7337,17 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fmul d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7517,38 +7517,38 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mrs x22, nzcv", + "mrs x21, nzcv", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w23, vs", + "cset x22, vs", "axflag", - "cset w24, lo", - "cset w30, eq", - "strb w24, [x28, #1016]", + "cset x23, lo", + "cset x24, eq", + "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w23, [x28, #1018]", - "strb w30, [x28, #1022]", - "ldrb w23, [x28, #1426]", - "lsl w24, w21, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1426]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w23, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w23, w21", - "strb w21, [x28, #1426]", + "ldrb w22, [x28, #1426]", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x21" ] }, "db 0xde, 0xe0": { @@ -7584,19 +7584,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7794,17 +7794,17 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8000,19 +8000,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8210,17 +8210,17 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8393,15 +8393,15 @@ "sxth x20, w20", "scvtf d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -8484,15 +8484,15 @@ "ldr x30, [sp], #16", "fmov d2, d0", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -8661,7 +8661,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8680,19 +8680,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8713,7 +8713,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8739,7 +8739,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8765,7 +8765,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8791,7 +8791,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8817,7 +8817,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8843,7 +8843,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8867,7 +8867,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8886,19 +8886,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8919,7 +8919,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8945,7 +8945,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8971,7 +8971,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -8997,7 +8997,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -9023,7 +9023,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", @@ -9049,7 +9049,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "axflag", "ldrb w21, [x28, #1426]", "mov w22, #0x1", diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index 50fbd1aac..d3add1eb1 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -450,12 +450,12 @@ "umov w20, v2.h[0]", "umov w21, v3.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -734,7 +734,7 @@ "eor w21, w20, #0x20000000", "msr nzcv, x21", "adcs w4, w6, w4", - "cset w21, lo", + "cset x21, lo", "bfi w20, w21, #29, #1", "msr nzcv, x20" ] @@ -749,7 +749,7 @@ "eor w21, w20, #0x20000000", "msr nzcv, x21", "adcs x4, x6, x4", - "cset w21, lo", + "cset x21, lo", "bfi w20, w21, #29, #1", "msr nzcv, x20" ] @@ -763,7 +763,7 @@ "mrs x20, nzcv", "ccmp wzr, #0, #nzcv, vs", "adcs w4, w6, w4", - "cset w21, hs", + "cset x21, hs", "bfi w20, w21, #28, #1", "msr nzcv, x20" ] @@ -777,7 +777,7 @@ "mrs x20, nzcv", "ccmp wzr, #0, #nzcv, vs", "adcs x4, x6, x4", - "cset w21, hs", + "cset x21, hs", "bfi w20, w21, #28, #1", "msr nzcv, x20" ] diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index a3db66959..a389f377e 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -2640,7 +2640,7 @@ "ExpectedInstructionCount": 39, "Comment": "0x9c", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x27, x26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -2651,7 +2651,7 @@ "ldrsb x21, [x28, #986]", "lsr x21, x21, #63", "orr x20, x20, x21, lsl #10", - "cset w21, vs", + "cset x21, vs", "orr x20, x20, x21, lsl #11", "ldrb w21, [x28, #988]", "orr x20, x20, x21, lsl #12", @@ -2685,7 +2685,7 @@ "ExpectedInstructionCount": 39, "Comment": "0x9c", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x27, x26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", @@ -2696,7 +2696,7 @@ "ldrsb x21, [x28, #986]", "lsr x21, x21, #63", "orr x20, x20, x21, lsl #10", - "cset w21, vs", + "cset x21, vs", "orr x20, x20, x21, lsl #11", "ldrb w21, [x28, #988]", "orr x20, x20, x21, lsl #12", @@ -2799,7 +2799,7 @@ "ExpectedInstructionCount": 14, "Comment": "0x9f", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x27, x26", "ubfx w21, w21, #4, #1", "orr x20, x20, x21, lsl #4", diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 7013440ba..eb6100c0e 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -1017,22 +1017,22 @@ "Comment": "GROUP2 0xC0 /2", "ExpectedArm64ASM": [ "uxtb w20, w4", - "mov w21, #0x0", - "cset w22, lo", - "bfi x21, x20, #55, #8", - "bfi x21, x22, #63, #1", - "bfi x21, x20, #46, #8", - "bfi x21, x22, #54, #1", - "bfi x21, x20, #37, #8", - "bfi x21, x22, #45, #1", - "bfi x21, x20, #28, #8", - "bfi x21, x22, #36, #1", - "bfi x21, x20, #19, #8", - "bfi x21, x22, #27, #1", - "bfxil x21, x20, #0, #8", - "ror x20, x21, #62", + "cset x21, lo", + "mov w22, #0x0", + "bfi x22, x20, #55, #8", + "bfi x22, x21, #63, #1", + "bfi x22, x20, #46, #8", + "bfi x22, x21, #54, #1", + "bfi x22, x20, #37, #8", + "bfi x22, x21, #45, #1", + "bfi x22, x20, #28, #8", + "bfi x22, x21, #36, #1", + "bfi x22, x20, #19, #8", + "bfi x22, x21, #27, #1", + "bfxil x22, x20, #0, #8", + "ror x20, x22, #62", "bfxil x4, x20, #0, #8", - "ror x20, x21, #61", + "ror x20, x22, #61", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x21, nzcv", @@ -1044,7 +1044,7 @@ "ExpectedInstructionCount": 13, "Comment": "GROUP2 0xC0 /3", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "uxtb w21, w4", "bfi x21, x20, #8, #1", "bfi x21, x21, #9, #9", @@ -1186,18 +1186,18 @@ "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "uxth w20, w4", - "mov w21, #0x0", - "cset w22, lo", - "bfi x21, x20, #47, #16", - "bfi x21, x22, #63, #1", - "bfi x21, x20, #30, #16", - "bfi x21, x22, #46, #1", - "bfi x21, x20, #13, #16", - "bfi x21, x22, #29, #1", - "bfxil x21, x20, #0, #16", - "ror x20, x21, #62", + "cset x21, lo", + "mov w22, #0x0", + "bfi x22, x20, #47, #16", + "bfi x22, x21, #63, #1", + "bfi x22, x20, #30, #16", + "bfi x22, x21, #46, #1", + "bfi x22, x20, #13, #16", + "bfi x22, x21, #29, #1", + "bfxil x22, x20, #0, #16", + "ror x20, x22, #62", "bfxil x4, x20, #0, #16", - "ror x20, x21, #61", + "ror x20, x22, #61", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x21, nzcv", @@ -1210,7 +1210,7 @@ "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "lsl w20, w4, #2", - "cset w21, lo", + "cset x21, lo", "orr w20, w20, w4, lsr #31", "eor x22, x4, #0x40000000", "ubfx x22, x22, #30, #1", @@ -1225,7 +1225,7 @@ "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "lsl x20, x4, #2", - "cset w21, lo", + "cset x21, lo", "orr x20, x20, x4, lsr #63", "eor x22, x4, #0x4000000000000000", "ubfx x22, x22, #62, #1", @@ -1239,7 +1239,7 @@ "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "uxth w21, w4", "bfi x21, x20, #16, #1", "bfi x21, x21, #17, #17", @@ -1258,7 +1258,7 @@ "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "lsr w20, w4, #2", - "cset w21, lo", + "cset x21, lo", "orr w20, w20, w4, lsl #31", "eor x22, x4, #0x2", "ubfx x22, x22, #1, #1", @@ -1273,7 +1273,7 @@ "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "lsr x20, x4, #2", - "cset w21, lo", + "cset x21, lo", "orr x20, x20, x4, lsl #63", "eor x22, x4, #0x2", "ubfx x22, x22, #1, #1", @@ -1452,7 +1452,7 @@ "Comment": "GROUP2 0xd0 /2", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, lo", + "cset x21, lo", "orr w21, w21, w20, lsl #1", "eor x22, x20, #0x80", "ubfx x22, x22, #7, #1", @@ -1470,7 +1470,7 @@ "Comment": "GROUP2 0xd0 /3", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, lo", + "cset x21, lo", "eor x22, x20, #0x1", "ubfx x22, x22, #0, #1", "mrs x23, nzcv", @@ -1634,7 +1634,7 @@ "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ "uxth w20, w4", - "cset w21, lo", + "cset x21, lo", "orr w21, w21, w20, lsl #1", "eor x22, x20, #0x8000", "ubfx x22, x22, #15, #1", @@ -1652,7 +1652,7 @@ "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ "mov w20, w4", - "cset w21, lo", + "cset x21, lo", "orr w4, w21, w20, lsl #1", "eor x21, x20, #0x80000000", "ubfx x21, x21, #31, #1", @@ -1668,7 +1668,7 @@ "ExpectedInstructionCount": 11, "Comment": "GROUP2 0xd1 /2", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "orr x20, x20, x4, lsl #1", "eor x21, x4, #0x8000000000000000", "lsr x21, x21, #63", @@ -1685,7 +1685,7 @@ "ExpectedInstructionCount": 12, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x4, #0x1", "ubfx x21, x21, #0, #1", "mrs x22, nzcv", @@ -1703,7 +1703,7 @@ "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x4, #0x1", "ubfx x21, x21, #0, #1", "mrs x22, nzcv", @@ -1719,7 +1719,7 @@ "ExpectedInstructionCount": 10, "Comment": "GROUP2 0xd1 /3", "ExpectedArm64ASM": [ - "cset w20, lo", + "cset x20, lo", "eor x21, x4, #0x1", "ubfx x21, x21, #0, #1", "mrs x22, nzcv", @@ -1923,25 +1923,25 @@ "cbz x20, #+0x78", "and x20, x7, #0x1f", "uxtb w21, w4", - "mov w22, #0x0", - "cset w23, lo", - "bfi x22, x21, #55, #8", - "bfi x22, x23, #63, #1", - "bfi x22, x21, #46, #8", - "bfi x22, x23, #54, #1", - "bfi x22, x21, #37, #8", - "bfi x22, x23, #45, #1", - "bfi x22, x21, #28, #8", - "bfi x22, x23, #36, #1", - "bfi x22, x21, #19, #8", - "bfi x22, x23, #27, #1", - "bfxil x22, x21, #0, #8", + "cset x22, lo", + "mov w23, #0x0", + "bfi x23, x21, #55, #8", + "bfi x23, x22, #63, #1", + "bfi x23, x21, #46, #8", + "bfi x23, x22, #54, #1", + "bfi x23, x21, #37, #8", + "bfi x23, x22, #45, #1", + "bfi x23, x21, #28, #8", + "bfi x23, x22, #36, #1", + "bfi x23, x21, #19, #8", + "bfi x23, x22, #27, #1", + "bfxil x23, x21, #0, #8", "neg x21, x20", - "ror x21, x22, x21", + "ror x21, x23, x21", "bfxil x4, x21, #0, #8", - "mov w23, #0x3f", - "sub x20, x23, x20", - "ror x20, x22, x20", + "mov w22, #0x3f", + "sub x20, x22, x20", + "ror x20, x23, x20", "eor x22, x20, #0x1", "ubfx x22, x22, #0, #1", "mrs x23, nzcv", @@ -1959,7 +1959,7 @@ "and x20, x7, #0x1f", "cbz x20, #+0x50", "and x20, x7, #0x1f", - "cset w21, lo", + "cset x21, lo", "uxtb w22, w4", "bfi x22, x21, #8, #1", "bfi x22, x22, #9, #9", @@ -2153,21 +2153,21 @@ "cbz x20, #+0x68", "and x20, x7, #0x1f", "uxth w21, w4", - "mov w22, #0x0", - "cset w23, lo", - "bfi x22, x21, #47, #16", - "bfi x22, x23, #63, #1", - "bfi x22, x21, #30, #16", - "bfi x22, x23, #46, #1", - "bfi x22, x21, #13, #16", - "bfi x22, x23, #29, #1", - "bfxil x22, x21, #0, #16", + "cset x22, lo", + "mov w23, #0x0", + "bfi x23, x21, #47, #16", + "bfi x23, x22, #63, #1", + "bfi x23, x21, #30, #16", + "bfi x23, x22, #46, #1", + "bfi x23, x21, #13, #16", + "bfi x23, x22, #29, #1", + "bfxil x23, x21, #0, #16", "neg x21, x20", - "ror x21, x22, x21", + "ror x21, x23, x21", "bfxil x4, x21, #0, #16", - "mov w23, #0x3f", - "sub x20, x23, x20", - "ror x20, x22, x20", + "mov w22, #0x3f", + "sub x20, x22, x20", + "ror x20, x23, x20", "eor x22, x20, #0x1", "ubfx x22, x22, #0, #1", "mrs x23, nzcv", @@ -2185,7 +2185,7 @@ "and w20, w7, #0x1f", "cbz x20, #+0x4c", "lsl w20, w4, w7", - "cset w21, lo", + "cset x21, lo", "neg w22, w7", "lsr w23, w4, w22", "orr w20, w20, w23, lsr #1", @@ -2212,7 +2212,7 @@ "and x20, x7, #0x3f", "cbz x20, #+0x48", "lsl x20, x4, x7", - "cset w21, lo", + "cset x21, lo", "neg x22, x7", "lsr x23, x4, x22", "orr x20, x20, x23, lsr #1", @@ -2237,7 +2237,7 @@ "and x20, x7, #0x1f", "cbz x20, #+0x4c", "and x20, x7, #0x1f", - "cset w21, lo", + "cset x21, lo", "uxth w22, w4", "bfi x22, x21, #16, #1", "bfi x22, x22, #17, #17", @@ -2263,7 +2263,7 @@ "and w20, w7, #0x1f", "cbz x20, #+0x4c", "lsr w20, w4, w7", - "cset w21, lo", + "cset x21, lo", "neg w22, w7", "lsl w23, w4, w22", "orr w20, w20, w23, lsl #1", @@ -2290,7 +2290,7 @@ "and x20, x7, #0x3f", "cbz x20, #+0x48", "lsr x20, x4, x7", - "cset w21, lo", + "cset x21, lo", "neg x22, x7", "lsl x23, x4, x22", "orr x20, x20, x23, lsl #1", @@ -2856,7 +2856,7 @@ "ExpectedArm64ASM": [ "uxtb w27, w4", "mov w20, #0x1", - "cset w21, hs", + "cset x21, hs", "lsl w0, w27, #24", "cmn w0, w20, lsl #24", "add w26, w27, #0x1 (1)", @@ -2872,7 +2872,7 @@ "ExpectedArm64ASM": [ "uxtb w27, w4", "mov w20, #0x1", - "cset w21, hs", + "cset x21, hs", "lsl w0, w27, #24", "cmp w0, w20, lsl #24", "sub w26, w27, #0x1 (1)", @@ -2888,7 +2888,7 @@ "ExpectedArm64ASM": [ "uxth w27, w4", "mov w20, #0x1", - "cset w21, hs", + "cset x21, hs", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", "add w26, w27, #0x1 (1)", @@ -2902,7 +2902,7 @@ "ExpectedInstructionCount": 7, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "adds w26, w4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -2915,7 +2915,7 @@ "ExpectedInstructionCount": 7, "Comment": "GROUP4 0xfe /0", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "adds x26, x4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -2930,7 +2930,7 @@ "ExpectedArm64ASM": [ "uxth w27, w4", "mov w20, #0x1", - "cset w21, hs", + "cset x21, hs", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", "sub w26, w27, #0x1 (1)", @@ -2944,7 +2944,7 @@ "ExpectedInstructionCount": 7, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "subs w26, w4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -2957,7 +2957,7 @@ "ExpectedInstructionCount": 7, "Comment": "GROUP4 0xfe /1", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "subs x26, x4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index 429b14ba1..87ab012e9 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -106,7 +106,7 @@ "Comment": "0x27", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, hs", + "cset x21, hs", "and x22, x20, #0xf", "cmp x22, #0x9 (9)", "cset x22, hi", @@ -135,7 +135,7 @@ "Comment": "0x2f", "ExpectedArm64ASM": [ "uxtb w20, w4", - "cset w21, lo", + "cset x21, lo", "and x22, x20, #0xf", "cmp x22, #0x9 (9)", "cset x22, hi", @@ -207,7 +207,7 @@ "ExpectedArm64ASM": [ "uxth w27, w4", "mov w20, #0x1", - "cset w21, hs", + "cset x21, hs", "lsl w0, w27, #16", "cmn w0, w20, lsl #16", "add w26, w27, #0x1 (1)", @@ -221,7 +221,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x40", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "adds w26, w4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -236,7 +236,7 @@ "ExpectedArm64ASM": [ "uxth w27, w4", "mov w20, #0x1", - "cset w21, hs", + "cset x21, hs", "lsl w0, w27, #16", "cmp w0, w20, lsl #16", "sub w26, w27, #0x1 (1)", @@ -264,7 +264,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x48", "ExpectedArm64ASM": [ - "cset w20, hs", + "cset x20, hs", "subs w26, w4, #0x1 (1)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 4581ac21c..a10a57903 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -228,8 +228,8 @@ "Comment": "0x0f 0x2e", "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -239,8 +239,8 @@ "Comment": "0x0f 0x2f", "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index d471d1d7f..f7ec35e5c 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -941,9 +941,9 @@ "ExpectedArm64ASM": [ "mrs x20, rndr", "bfxil x4, x20, #0, #16", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "mov w0, w27", "bfi w0, w20, #29, #1", "mov w20, w0", @@ -956,9 +956,9 @@ "ExpectedArm64ASM": [ "mrs x20, rndr", "mov w4, w20", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "mov w0, w27", "bfi w0, w20, #29, #1", "mov w20, w0", @@ -970,9 +970,9 @@ "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x4, rndr", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "mov w0, w27", "bfi w0, w20, #29, #1", "mov w20, w0", @@ -985,9 +985,9 @@ "ExpectedArm64ASM": [ "mrs x20, rndrrs", "bfxil x4, x20, #0, #16", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "mov w0, w27", "bfi w0, w20, #29, #1", "mov w20, w0", @@ -1000,9 +1000,9 @@ "ExpectedArm64ASM": [ "mrs x20, rndrrs", "mov w4, w20", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "mov w0, w27", "bfi w0, w20, #29, #1", "mov w20, w0", @@ -1014,9 +1014,9 @@ "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x4, rndrrs", + "cset x20, eq", "mov w26, #0x1", "mov w27, #0x0", - "cset w20, eq", "mov w0, w27", "bfi w0, w20, #29, #1", "mov w20, w0", diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index fee959d6e..646efa303 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -157,8 +157,8 @@ "Comment": "0x66 0x0f 0x2e", "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -168,8 +168,8 @@ "Comment": "0x66 0x0f 0x2f", "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 7eb06a829..9cb517aa8 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -3394,8 +3394,8 @@ ], "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -3407,8 +3407,8 @@ ], "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -3420,8 +3420,8 @@ ], "ExpectedArm64ASM": [ "fcmp s16, s17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -3433,8 +3433,8 @@ ], "ExpectedArm64ASM": [ "fcmp d16, d17", + "cset x26, vc", "mov w27, #0x0", - "cset w26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 7e3375889..0cf9ce555 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -517,12 +517,12 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -543,12 +543,12 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -569,12 +569,12 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -595,12 +595,12 @@ "umov w20, v3.h[0]", "umov w21, v2.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -675,12 +675,12 @@ "umov w20, v2.h[0]", "umov w21, v3.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -697,12 +697,12 @@ "umov w20, v2.h[0]", "umov w21, v3.h[0]", "mov w27, #0x0", - "mov w26, #0x1", "cmp x21, #0x0 (0)", "cset x21, ne", "cmp w20, #0x0 (0)", "mrs x20, nzcv", "bfi w20, w21, #29, #1", + "mov w26, #0x1", "msr nzcv, x20" ] }, @@ -4925,7 +4925,7 @@ "bic w20, w6, w20", "tst x7, #0xe0", "csel w4, w6, w20, ne", - "cset w20, eq", + "cset x20, eq", "cmp w4, #0x0 (0)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", @@ -4943,7 +4943,7 @@ "bic x20, x6, x20", "tst x7, #0xc0", "csel x4, x6, x20, ne", - "cset w20, eq", + "cset x20, eq", "cmp x4, #0x0 (0)", "mrs x21, nzcv", "bfi w21, w20, #29, #1", diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json index 6aa94fcd5..f5d3ea6f7 100644 --- a/unittests/InstructionCountCI/VEX_map_group.json +++ b/unittests/InstructionCountCI/VEX_map_group.json @@ -680,7 +680,7 @@ "neg w20, w6", "and w4, w6, w20", "cmp w4, #0x0 (0)", - "cset w20, eq", + "cset x20, eq", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "msr nzcv, x21" @@ -695,7 +695,7 @@ "neg x20, x6", "and x4, x6, x20", "cmp x4, #0x0 (0)", - "cset w20, eq", + "cset x20, eq", "mrs x21, nzcv", "bfi w21, w20, #29, #1", "msr nzcv, x21" diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json index ae0978d6e..5db227b89 100644 --- a/unittests/InstructionCountCI/X87ldst-SVE.json +++ b/unittests/InstructionCountCI/X87ldst-SVE.json @@ -175,15 +175,15 @@ "ExpectedArm64ASM": [ "ld1h {z2.h}, p2/z, [x4]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 8374f16c3..aefa402e2 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -963,10 +963,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -975,19 +974,20 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -2041,15 +2041,15 @@ "ldr x30, [sp], #16", "mov v2.16b, v0.16b", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2198,15 +2198,15 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2217,19 +2217,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2244,15 +2244,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2267,15 +2267,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2290,15 +2290,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2313,15 +2313,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2336,15 +2336,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2359,15 +2359,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2603,7 +2603,7 @@ "lsr w20, w21, w20", "and w20, w20, #0x1", "mrs x21, nzcv", - "cmp x20, #0x1 (1)", + "cmp w20, #0x1 (1)", "cset x22, ne", "strb w22, [x28, #1016]", "strb w20, [x28, #1018]", @@ -2619,15 +2619,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3232]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2639,15 +2639,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3248]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2659,15 +2659,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3264]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2679,15 +2679,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3280]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2699,15 +2699,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3296]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2719,15 +2719,15 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #3312]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2739,15 +2739,15 @@ "ExpectedArm64ASM": [ "movi v2.2d, #0x0", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2818,15 +2818,15 @@ "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", "ldr q2, [x28, #3232]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]", "strb wzr, [x28, #1018]" ] @@ -3066,15 +3066,15 @@ "mov v4.16b, v1.16b", "add x0, x28, x20, lsl #4", "str q3, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q4, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]", "strb wzr, [x28, #1018]" ] @@ -4085,10 +4085,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -4097,26 +4096,27 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -4135,7 +4135,7 @@ "mov w22, #0x0", "cmp x20, #0x0 (0)", "mov w23, #0x8000", - "csel x23, x23, xzr, lt", + "csel x23, x23, x22, lt", "cneg x20, x20, mi", "mov w24, #0x3f", "mov x0, #0x3f", @@ -4152,15 +4152,15 @@ "fmov v2.D[1], x20", "msr nzcv, x21", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -4247,15 +4247,15 @@ "add x20, x4, #0x8 (8)", "ld1 {v2.h}[4], [x20]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -6969,15 +6969,15 @@ "ldr x30, [sp], #16", "mov v2.16b, v0.16b", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -7264,12 +7264,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -7385,14 +7385,14 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -7523,15 +7523,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -7544,18 +7544,18 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w23, [x28, #1426]", - "lsl w22, w21, w22", - "orr w22, w23, w22", - "strb w22, [x28, #1426]", "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov w23, #0x1", + "lsl w21, w23, w21", + "orr w21, w22, w21", + "strb w21, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w22, w23, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8025,10 +8025,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8037,19 +8036,20 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8590,10 +8590,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -8603,11 +8602,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8852,10 +8852,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -8865,11 +8864,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -9083,10 +9083,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -9095,26 +9094,27 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "strb w23, [x28, #1016]", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "strb w22, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w22, [x28, #1018]", - "strb w24, [x28, #1022]", - "ldrb w22, [x28, #1426]", - "lsl w23, w21, w20", - "bic w22, w22, w23", - "strb w22, [x28, #1426]", + "strb w21, [x28, #1018]", + "strb w23, [x28, #1022]", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w23, w22, w20", + "bic w21, w21, w23", + "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -9161,10 +9161,9 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -9176,11 +9175,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -9427,10 +9427,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -9440,11 +9439,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -9689,10 +9689,9 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", @@ -9704,11 +9703,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -9955,10 +9955,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -9968,11 +9967,12 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -10189,7 +10189,7 @@ "mov w22, #0x0", "cmp x20, #0x0 (0)", "mov w23, #0x8000", - "csel x23, x23, xzr, lt", + "csel x23, x23, x22, lt", "cneg x20, x20, mi", "mov w24, #0x3f", "mov x0, #0x3f", @@ -10206,15 +10206,15 @@ "fmov v2.D[1], x20", "msr nzcv, x21", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -10341,15 +10341,15 @@ "ldr x30, [sp], #16", "mov v2.16b, v0.16b", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -10548,10 +10548,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -10560,25 +10559,26 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "eor x23, x23, #0x1", - "mrs x30, nzcv", - "bfi w30, w23, #29, #1", - "bfi w30, w24, #30, #1", - "eor w26, w22, #0x1", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "eor x22, x22, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x30" + "msr nzcv, x24" ] }, "fucomip st2": { @@ -10882,10 +10882,9 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr q3, [x0, #1040]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -10894,25 +10893,26 @@ "ldr x3, [x28, #1728]", "blr x0", "ldr x30, [sp], #16", - "mov x22, x0", - "ubfx x23, x22, #1, #1", - "ubfx x24, x22, #0, #1", - "ubfx x22, x22, #2, #1", - "orr w23, w23, w22", - "orr w24, w24, w22", - "eor x23, x23, #0x1", - "mrs x30, nzcv", - "bfi w30, w23, #29, #1", - "bfi w30, w24, #30, #1", - "eor w26, w22, #0x1", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov x21, x0", + "ubfx x22, x21, #1, #1", + "ubfx x23, x21, #0, #1", + "ubfx x21, x21, #2, #1", + "orr w22, w22, w21", + "orr w23, w23, w21", + "eor x22, x22, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "eor w26, w21, #0x1", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x30" + "msr nzcv, x24" ] }, "fcomip st2": { diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index 5c820efad..899a99f6f 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -59,9 +59,9 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w21, vs", - "cset w22, lo", - "cset w23, eq", + "cset x21, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", @@ -84,9 +84,9 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -465,9 +465,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -492,9 +492,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -519,9 +519,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -546,9 +546,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -573,9 +573,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -600,9 +600,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -627,9 +627,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -654,9 +654,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -679,9 +679,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -706,32 +706,32 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mrs x22, nzcv", + "mrs x21, nzcv", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w23, vs", - "cset w24, lo", - "cset w30, eq", - "orr w24, w24, w23", - "orr w30, w30, w23", - "strb w24, [x28, #1016]", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w23, [x28, #1018]", - "strb w30, [x28, #1022]", - "ldrb w23, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w23, w21", - "strb w21, [x28, #1426]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x21" ] }, "fcomp st0, st2": { @@ -749,9 +749,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -784,9 +784,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -819,9 +819,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -854,9 +854,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -889,9 +889,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -924,9 +924,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -1521,15 +1521,15 @@ "ldr s2, [x4]", "fcvt d2, s2", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1680,15 +1680,15 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1699,19 +1699,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1726,15 +1726,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1749,15 +1749,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1772,15 +1772,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1795,15 +1795,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1818,15 +1818,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -1841,15 +1841,15 @@ "and w21, w21, #0x7", "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2050,9 +2050,9 @@ "mov w21, #0x0", "fmov d3, x21", "fcmp d2, d3", - "cset w21, vs", - "cset w22, lo", - "cset w23, eq", + "cset x21, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", @@ -2078,7 +2078,7 @@ "lsr w20, w21, w20", "and w20, w20, #0x1", "mrs x21, nzcv", - "cmp x20, #0x1 (1)", + "cmp w20, #0x1 (1)", "cset x22, ne", "strb w22, [x28, #1016]", "strb w20, [x28, #1018]", @@ -2095,15 +2095,15 @@ "mov x20, #0x3ff0000000000000", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2119,15 +2119,15 @@ "movk x20, #0x400a, lsl #48", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2143,15 +2143,15 @@ "movk x20, #0x3ff7, lsl #48", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2167,15 +2167,15 @@ "movk x20, #0x4009, lsl #48", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2191,15 +2191,15 @@ "movk x20, #0x3fd3, lsl #48", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2215,15 +2215,15 @@ "movk x20, #0x3fe6, lsl #48", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2236,15 +2236,15 @@ "mov w20, #0x0", "fmov d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -2316,15 +2316,15 @@ "str d2, [x0, #1040]", "mov x21, #0x3ff0000000000000", "fmov d2, x21", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]", "strb wzr, [x28, #1018]" ] @@ -2552,15 +2552,15 @@ "fmov d4, d1", "add x0, x28, x20, lsl #4", "str d3, [x0, #1040]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d4, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]", "strb wzr, [x28, #1018]" ] @@ -2691,9 +2691,9 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w21, vs", - "cset w22, lo", - "cset w23, eq", + "cset x21, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", @@ -2716,9 +2716,9 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -3463,39 +3463,39 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mrs x22, nzcv", + "mrs x21, nzcv", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w23, vs", - "cset w24, lo", - "cset w30, eq", - "orr w24, w24, w23", - "orr w30, w30, w23", - "strb w24, [x28, #1016]", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w23, [x28, #1018]", - "strb w30, [x28, #1022]", - "ldrb w23, [x28, #1426]", - "lsl w24, w21, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1426]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w23, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w23, w21", - "strb w21, [x28, #1426]", + "ldrb w22, [x28, #1426]", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x21" ] }, "fild dword [rax]": { @@ -3507,15 +3507,15 @@ "ldr w20, [x4]", "scvtf d2, w20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -3591,15 +3591,15 @@ "ldr x30, [sp], #16", "fmov d2, d0", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -4331,7 +4331,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4350,7 +4350,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4369,7 +4369,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4388,7 +4388,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4407,7 +4407,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4426,7 +4426,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4445,7 +4445,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4464,7 +4464,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4481,7 +4481,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4500,7 +4500,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4519,7 +4519,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4538,7 +4538,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4557,7 +4557,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4576,7 +4576,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4595,7 +4595,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4614,7 +4614,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le" ] @@ -4661,9 +4661,9 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w21, vs", - "cset w22, lo", - "cset w23, eq", + "cset x21, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", @@ -4685,9 +4685,9 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -5637,15 +5637,15 @@ "ExpectedArm64ASM": [ "ldr d2, [x4]", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -6041,12 +6041,12 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -6162,14 +6162,14 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -6300,15 +6300,15 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "bic w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "bic w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -6321,18 +6321,18 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w23, [x28, #1426]", - "lsl w22, w21, w22", - "orr w22, w23, w22", - "strb w22, [x28, #1426]", "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "mov w23, #0x1", + "lsl w21, w23, w21", + "orr w21, w22, w21", + "strb w21, [x28, #1426]", + "ldrb w21, [x28, #1426]", + "lsl w22, w23, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -6514,9 +6514,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -6541,9 +6541,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -6568,9 +6568,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -6595,9 +6595,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -6622,9 +6622,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -6649,9 +6649,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -6676,9 +6676,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -6703,9 +6703,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w20, vs", - "cset w22, lo", - "cset w23, eq", + "cset x20, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w20", "orr w23, w23, w20", "strb w22, [x28, #1016]", @@ -6728,9 +6728,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -6755,32 +6755,32 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mrs x22, nzcv", + "mrs x21, nzcv", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w23, vs", - "cset w24, lo", - "cset w30, eq", - "orr w24, w24, w23", - "orr w30, w30, w23", - "strb w24, [x28, #1016]", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w23, [x28, #1018]", - "strb w30, [x28, #1022]", - "ldrb w23, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w23, w21", - "strb w21, [x28, #1426]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x21" ] }, "fucomp st2": { @@ -6798,9 +6798,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -6833,9 +6833,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -6868,9 +6868,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -6903,9 +6903,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -6938,9 +6938,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -6973,9 +6973,9 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -7041,9 +7041,9 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w21, vs", - "cset w22, lo", - "cset w23, eq", + "cset x21, vs", + "cset x22, lo", + "cset x23, eq", "orr w22, w22, w21", "orr w23, w23, w21", "strb w22, [x28, #1016]", @@ -7067,9 +7067,9 @@ "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w22, vs", - "cset w23, lo", - "cset w24, eq", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", "orr w23, w23, w22", "orr w24, w24, w22", "strb w23, [x28, #1016]", @@ -7188,17 +7188,17 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fadd d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7394,17 +7394,17 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fmul d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7574,39 +7574,39 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", - "mrs x22, nzcv", + "mrs x21, nzcv", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w23, vs", - "cset w24, lo", - "cset w30, eq", - "orr w24, w24, w23", - "orr w30, w30, w23", - "strb w24, [x28, #1016]", + "cset x22, vs", + "cset x23, lo", + "cset x24, eq", + "orr w23, w23, w22", + "orr w24, w24, w22", + "strb w23, [x28, #1016]", "strb wzr, [x28, #1017]", - "strb w23, [x28, #1018]", - "strb w30, [x28, #1022]", - "ldrb w23, [x28, #1426]", - "lsl w24, w21, w20", - "bic w23, w23, w24", - "strb w23, [x28, #1426]", + "strb w22, [x28, #1018]", + "strb w24, [x28, #1022]", + "ldrb w22, [x28, #1426]", + "mov w23, #0x1", + "lsl w24, w23, w20", + "bic w22, w22, w24", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "ldrb w23, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w23, w21", - "strb w21, [x28, #1426]", + "ldrb w22, [x28, #1426]", + "lsl w23, w23, w20", + "bic w22, w22, w23", + "strb w22, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x21" ] }, "db 0xde, 0xe0": { @@ -7642,19 +7642,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -7852,17 +7852,17 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fsub d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8058,19 +8058,19 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8268,17 +8268,17 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr d2, [x0, #1040]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d3, [x0, #1040]", "fdiv d2, d3, d2", - "add x0, x28, x22, lsl #4", + "add x0, x28, x21, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8451,15 +8451,15 @@ "sxth x20, w20", "scvtf d2, x20", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -8542,15 +8542,15 @@ "ldr x30, [sp], #16", "fmov d2, d0", "ldrb w20, [x28, #1019]", - "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "str d2, [x0, #1040]", - "ldrb w22, [x28, #1426]", - "lsl w20, w21, w20", - "orr w20, w22, w20", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w20, w22, w20", + "orr w20, w21, w20", "strb w20, [x28, #1426]" ] }, @@ -8719,7 +8719,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -8739,20 +8739,20 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8773,7 +8773,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -8800,7 +8800,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -8827,7 +8827,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -8854,7 +8854,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -8881,7 +8881,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -8908,7 +8908,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -8933,7 +8933,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -8953,20 +8953,20 @@ ], "ExpectedArm64ASM": [ "ldrb w20, [x28, #1019]", - "mov w21, #0x1", - "add w22, w20, #0x1 (1)", - "and w22, w22, #0x7", - "add x0, x28, x22, lsl #4", + "add w21, w20, #0x1 (1)", + "and w21, w21, #0x7", + "add x0, x28, x21, lsl #4", "ldr d2, [x0, #1040]", "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", - "ldrb w22, [x28, #1426]", - "lsl w21, w21, w20", - "bic w21, w22, w21", + "ldrb w21, [x28, #1426]", + "mov w22, #0x1", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1426]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -8987,7 +8987,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -9014,7 +9014,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -9041,7 +9041,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -9068,7 +9068,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -9095,7 +9095,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]", @@ -9122,7 +9122,7 @@ "add x0, x28, x20, lsl #4", "ldr d3, [x0, #1040]", "fcmp d3, d2", - "cset w26, vc", + "cset x26, vc", "csetm x0, eq", "ccmn x26, x0, #nzCv, le", "ldrb w21, [x28, #1426]",