diff --git a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp index 6cb731ad5..68ff1efe4 100644 --- a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp @@ -146,6 +146,15 @@ DEF_OP(ExitFunction) { } else { stp(ARMEmitter::XReg::zr, ARMEmitter::XReg::zr, REG_CALLRET_SP, -0x10); } + } else if (Op->Hint == IR::BranchHint::CheckTF) { + ARMEmitter::ForwardLabel TFUnset; + ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC])); + cbz(ARMEmitter::Size::i32Bit, TMP1, &TFUnset); + LoadConstant(ARMEmitter::Size::i64Bit, TMP1, NewRIP); + str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)); + ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop)); + blr(TMP2); + Bind(&TFUnset); } EmitLinkedBranch(NewRIP, Op->Hint == IR::BranchHint::Call); diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index de6c0e99f..38a0f71af 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -3604,6 +3604,10 @@ void OpDispatchBuilder::POPFOp(OpcodeArgs) { Src = _Or(OpSize::i64Bit, Src, Constant(0x202)); SetPackedRFLAG(false, Src); + + auto NewRIP = GetRelocatedPC(Op); + ExitFunction(NewRIP, BranchHint::CheckTF); + BlockSetRIP = true; } void OpDispatchBuilder::NEGOp(OpcodeArgs) { diff --git a/FEXCore/Source/Interface/IR/IR.h b/FEXCore/Source/Interface/IR/IR.h index 5a0f66535..0670b2b2b 100644 --- a/FEXCore/Source/Interface/IR/IR.h +++ b/FEXCore/Source/Interface/IR/IR.h @@ -621,11 +621,7 @@ enum class ShiftType : uint8_t { ROR, }; -enum class BranchHint : uint8_t { - None = 0, - Call, - Return, -}; +enum class BranchHint : uint8_t { None = 0, Call, Return, CheckTF }; // Converts a size stored as an integer in to an OpSize enum.