diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json
index a70e4cd38..bcf1d9c8f 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map1.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json
@@ -485,7 +485,7 @@
       ],
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #3200]",
+        "ldr q3, [x28, #3216]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -499,7 +499,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #192]",
         "ushr v3.4s, v16.4s, #31",
-        "ldr q4, [x28, #3200]",
+        "ldr q4, [x28, #3216]",
         "ushl v3.4s, v3.4s, v4.4s",
         "addv s3, v3.4s",
         "mov w20, v3.s[0]",
@@ -3884,7 +3884,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d",
         "stp xzr, xzr, [x28, #192]"
@@ -3898,7 +3898,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
         "ldr q3, [x28, #224]",
-        "ldr q4, [x28, #3104]",
+        "ldr q4, [x28, #3120]",
         "eor v5.16b, v18.16b, v4.16b",
         "fadd v16.2d, v17.2d, v5.2d",
         "eor v3.16b, v3.16b, v4.16b",
@@ -3912,7 +3912,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s",
         "stp xzr, xzr, [x28, #192]"
@@ -3926,7 +3926,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #208]",
         "ldr q3, [x28, #224]",
-        "ldr q4, [x28, #3072]",
+        "ldr q4, [x28, #3088]",
         "eor v5.16b, v18.16b, v4.16b",
         "fadd v16.4s, v17.4s, v5.4s",
         "eor v3.16b, v3.16b, v4.16b",
@@ -4097,7 +4097,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -4113,7 +4113,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #192]",
-        "ldr q3, [x28, #3328]",
+        "ldr q3, [x28, #3344]",
         "cmlt v4.16b, v16.16b, #0",
         "and v4.16b, v4.16b, v3.16b",
         "addp v4.16b, v4.16b, v4.16b",
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json
index 5040918ff..c740ff2bf 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json
@@ -1917,7 +1917,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
@@ -4485,7 +4485,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4502,7 +4502,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4518,7 +4518,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4535,7 +4535,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4551,7 +4551,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4568,7 +4568,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4584,7 +4584,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3168]",
+        "ldr q2, [x28, #3184]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4601,7 +4601,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3168]",
+        "ldr q5, [x28, #3184]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -5541,7 +5541,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5558,7 +5558,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5574,7 +5574,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5591,7 +5591,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5607,7 +5607,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5624,7 +5624,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5640,7 +5640,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3168]",
+        "ldr q2, [x28, #3184]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5657,7 +5657,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3168]",
+        "ldr q5, [x28, #3184]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5673,7 +5673,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5689,7 +5689,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5704,7 +5704,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5720,7 +5720,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5735,7 +5735,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5751,7 +5751,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5766,7 +5766,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3168]",
+        "ldr q2, [x28, #3184]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5782,7 +5782,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3168]",
+        "ldr q5, [x28, #3184]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
index 06f568827..573447f6a 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
@@ -2843,7 +2843,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2860,7 +2860,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2876,7 +2876,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2893,7 +2893,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2909,7 +2909,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2926,7 +2926,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2942,7 +2942,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3168]",
+        "ldr q2, [x28, #3184]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2959,7 +2959,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3168]",
+        "ldr q5, [x28, #3184]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -3879,7 +3879,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3896,7 +3896,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3912,7 +3912,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3929,7 +3929,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3945,7 +3945,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3962,7 +3962,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3978,7 +3978,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3168]",
+        "ldr q2, [x28, #3184]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3995,7 +3995,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3168]",
+        "ldr q5, [x28, #3184]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -4011,7 +4011,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4027,7 +4027,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3072]",
+        "ldr q5, [x28, #3088]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4042,7 +4042,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4058,7 +4058,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3104]",
+        "ldr q5, [x28, #3120]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4073,7 +4073,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4089,7 +4089,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3136]",
+        "ldr q5, [x28, #3152]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4104,7 +4104,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3168]",
+        "ldr q2, [x28, #3184]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4120,7 +4120,7 @@
         "ldr q2, [x28, #192]",
         "ldr q3, [x28, #208]",
         "ldr q4, [x28, #224]",
-        "ldr q5, [x28, #3168]",
+        "ldr q5, [x28, #3184]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json
index 4072f83f2..a88bc6705 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map3.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json
@@ -337,7 +337,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3232]",
+        "ldr q2, [x28, #3248]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -348,7 +348,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -369,7 +369,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3264]",
+        "ldr q2, [x28, #3280]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -391,7 +391,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3280]",
+        "ldr q2, [x28, #3296]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -412,7 +412,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -423,7 +423,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3312]",
+        "ldr q2, [x28, #3328]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #192]"
       ]
@@ -3488,7 +3488,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "ldr q3, [x28, #3216]",
+        "ldr q3, [x28, #3232]",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v2.16b",
         "tbl v16.16b, {v16.16b}, v3.16b",
@@ -3502,7 +3502,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "ldr q3, [x28, #3216]",
+        "ldr q3, [x28, #3232]",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v2.16b",
         "tbl v16.16b, {v16.16b}, v3.16b",
diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json
index 3ebb496f4..525ed59e6 100644
--- a/unittests/InstructionCountCI/Crypto/H0F3A.json
+++ b/unittests/InstructionCountCI/Crypto/H0F3A.json
@@ -55,7 +55,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -68,7 +68,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -84,7 +84,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3600]",
+        "ldr q2, [x28, #3616]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2688]",
         "ldr q4, [x0, #432]",
@@ -101,7 +101,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3616]",
+        "ldr q2, [x28, #3632]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2688]",
         "ldr q4, [x0, #432]",
@@ -118,7 +118,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3632]",
+        "ldr q2, [x28, #3648]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2688]",
         "ldr q4, [x0, #432]",
@@ -135,7 +135,7 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3648]",
+        "ldr q2, [x28, #3664]",
         "movi v3.2d, #0x0",
         "ldr x0, [x28, #2688]",
         "ldr q4, [x0, #432]",
diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json
index 62a14a422..150bd20bd 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary.json
@@ -1608,7 +1608,7 @@
         "mov w20, #0xffff",
         "strb w20, [x28, #1202]",
         "ldr d2, [x28, #1056]",
-        "ldr d3, [x28, #3328]",
+        "ldr d3, [x28, #3344]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.8b, v2.8b, v3.8b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
index bfc9a7141..c5ddb4d3c 100644
--- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
+++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json
@@ -37,7 +37,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json
index 596cbdf24..0c1ad3cda 100644
--- a/unittests/InstructionCountCI/FlagM/VEX_map1.json
+++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json
@@ -68,7 +68,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
index 2ab38a4df..1d6fcfa58 100644
--- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
+++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json
@@ -557,7 +557,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "bic v2.16b, v2.16b, v3.16b",
         "ldr s3, [x4]",
         "str x30, [sp, #-16]!",
@@ -567,7 +567,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v3.16b, v0.16b",
-        "ldr q4, [x28, #3584]",
+        "ldr q4, [x28, #3600]",
         "bic v3.16b, v3.16b, v4.16b",
         "strb wzr, [x28, #1049]",
         "str x30, [sp, #-16]!",
@@ -598,7 +598,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "bic v2.16b, v2.16b, v3.16b",
         "ldr s3, [x4, #4]",
         "str x30, [sp, #-16]!",
@@ -608,7 +608,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v3.16b, v0.16b",
-        "ldr q5, [x28, #3584]",
+        "ldr q5, [x28, #3600]",
         "bic v3.16b, v3.16b, v5.16b",
         "strb wzr, [x28, #1049]",
         "str x30, [sp, #-16]!",
@@ -639,7 +639,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "bic v2.16b, v2.16b, v3.16b",
         "ldr s3, [x4, #8]",
         "str x30, [sp, #-16]!",
@@ -649,7 +649,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v3.16b, v0.16b",
-        "ldr q6, [x28, #3584]",
+        "ldr q6, [x28, #3600]",
         "bic v3.16b, v3.16b, v6.16b",
         "strb wzr, [x28, #1049]",
         "str x30, [sp, #-16]!",
diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
index 28bd293cd..66dab58db 100644
--- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
+++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json
@@ -3789,7 +3789,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3584]",
+        "ldr q9, [x28, #3600]",
         "eor v2.16b, v2.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -3839,7 +3839,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3584]",
+        "ldr q9, [x28, #3600]",
         "eor v2.16b, v2.16b, v9.16b",
         "ldr s9, [x8, #28]",
         "str x30, [sp, #-16]!",
@@ -4002,7 +4002,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3584]",
+        "ldr q9, [x28, #3600]",
         "eor v2.16b, v2.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -4052,7 +4052,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3584]",
+        "ldr q9, [x28, #3600]",
         "eor v2.16b, v2.16b, v9.16b",
         "ldr s9, [x8, #60]",
         "str x30, [sp, #-16]!",
@@ -4238,7 +4238,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q9, [x28, #3584]",
+        "ldr q9, [x28, #3600]",
         "eor v2.16b, v2.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -4259,7 +4259,7 @@
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
         "str s2, [x8, #176]",
-        "ldr q2, [x28, #3584]",
+        "ldr q2, [x28, #3600]",
         "eor v2.16b, v9.16b, v2.16b",
         "ldr s9, [x8, #8]",
         "str x30, [sp, #-16]!",
@@ -7530,7 +7530,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q10, [x28, #3584]",
+        "ldr q10, [x28, #3600]",
         "eor v8.16b, v8.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v8.16b",
@@ -7621,7 +7621,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q11, [x28, #3584]",
+        "ldr q11, [x28, #3600]",
         "eor v8.16b, v8.16b, v11.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v8.16b",
@@ -7679,7 +7679,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q11, [x28, #3584]",
+        "ldr q11, [x28, #3600]",
         "eor v8.16b, v8.16b, v11.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v8.16b",
@@ -7952,7 +7952,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v7.16b, v0.16b",
-        "ldr q9, [x28, #3584]",
+        "ldr q9, [x28, #3600]",
         "eor v7.16b, v7.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v7.16b",
@@ -8112,7 +8112,7 @@
         "ldr x30, [sp], #16",
         "fmov s2, s0",
         "str s2, [x4, #1024]",
-        "ldr q2, [x28, #3584]",
+        "ldr q2, [x28, #3600]",
         "eor v2.16b, v3.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8130,7 +8130,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8141,7 +8141,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1152]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3584]",
+        "ldr q2, [x28, #3600]",
         "eor v2.16b, v6.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8159,7 +8159,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8177,7 +8177,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8188,7 +8188,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1344]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3584]",
+        "ldr q2, [x28, #3600]",
         "eor v2.16b, v11.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8206,7 +8206,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "eor v2.16b, v2.16b, v3.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8217,7 +8217,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1472]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3584]",
+        "ldr q2, [x28, #3600]",
         "eor v2.16b, v10.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8228,7 +8228,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1536]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3584]",
+        "ldr q2, [x28, #3600]",
         "eor v2.16b, v9.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8239,7 +8239,7 @@
         "fmov s2, s0",
         "str s2, [x4, #1600]",
         "strb wzr, [x28, #1049]",
-        "ldr q2, [x28, #3584]",
+        "ldr q2, [x28, #3600]",
         "eor v2.16b, v8.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -8249,7 +8249,7 @@
         "ldr x30, [sp], #16",
         "fmov s2, s0",
         "str s2, [x4, #1664]",
-        "ldr q2, [x28, #3584]",
+        "ldr q2, [x28, #3600]",
         "eor v2.16b, v7.16b, v2.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -12538,7 +12538,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "eor v3.16b, v2.16b, v3.16b",
         "ldr s4, [x4]",
         "str x30, [sp, #-16]!",
@@ -12580,7 +12580,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v4.16b, v0.16b",
-        "ldr q5, [x28, #3584]",
+        "ldr q5, [x28, #3600]",
         "eor v5.16b, v4.16b, v5.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12615,7 +12615,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3584]",
+        "ldr q6, [x28, #3600]",
         "eor v6.16b, v5.16b, v6.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12650,7 +12650,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v6.16b, v0.16b",
-        "ldr q7, [x28, #3584]",
+        "ldr q7, [x28, #3600]",
         "eor v7.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12685,7 +12685,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v7.16b, v0.16b",
-        "ldr q8, [x28, #3584]",
+        "ldr q8, [x28, #3600]",
         "eor v8.16b, v7.16b, v8.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12720,7 +12720,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v8.16b, v0.16b",
-        "ldr q9, [x28, #3584]",
+        "ldr q9, [x28, #3600]",
         "eor v9.16b, v8.16b, v9.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12755,7 +12755,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
-        "ldr q10, [x28, #3584]",
+        "ldr q10, [x28, #3600]",
         "eor v9.16b, v9.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12789,7 +12789,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
-        "ldr q10, [x28, #3584]",
+        "ldr q10, [x28, #3600]",
         "eor v9.16b, v9.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -12823,7 +12823,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v9.16b, v0.16b",
-        "ldr q10, [x28, #3584]",
+        "ldr q10, [x28, #3600]",
         "eor v9.16b, v9.16b, v10.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -20012,7 +20012,7 @@
         "mov x8, x26",
         "str s2, [x8, #16]",
         "uxtb w7, w4",
-        "ldr q2, [x28, #3360]",
+        "ldr q2, [x28, #3376]",
         "str w7, [x8, #56]",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v2.16b",
@@ -21708,7 +21708,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "eor v2.16b, v2.16b, v3.16b",
         "add x14, x28, x20, lsl #4",
         "ldr q3, [x14, #1056]",
@@ -21763,7 +21763,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q5, [x28, #3584]",
+        "ldr q5, [x28, #3600]",
         "eor v2.16b, v2.16b, v5.16b",
         "mov w14, #0x7b90",
         "movk w14, #0xa7, lsl #16",
@@ -21827,7 +21827,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q6, [x28, #3584]",
+        "ldr q6, [x28, #3600]",
         "eor v2.16b, v2.16b, v6.16b",
         "mov w15, #0x7b80",
         "movk w15, #0xa7, lsl #16",
@@ -21955,7 +21955,7 @@
         "fmov s7, s0",
         "str s7, [x8, #64]",
         "strb wzr, [x28, #1049]",
-        "ldr q7, [x28, #3584]",
+        "ldr q7, [x28, #3600]",
         "eor v7.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v7.16b",
@@ -21979,7 +21979,7 @@
         "fmov s7, s0",
         "str s7, [x8, #68]",
         "strb wzr, [x28, #1049]",
-        "ldr q7, [x28, #3584]",
+        "ldr q7, [x28, #3600]",
         "eor v2.16b, v2.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v5.16b",
@@ -22005,7 +22005,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q5, [x28, #3584]",
+        "ldr q5, [x28, #3600]",
         "eor v5.16b, v2.16b, v5.16b",
         "ldr d7, [x15]",
         "str x30, [sp, #-16]!",
diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
index db12450df..8650f1be7 100644
--- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
+++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json
@@ -10858,7 +10858,7 @@
         "add w22, w20, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x23, x28, x22, lsl #4",
-        "ldr q4, [x28, #3584]",
+        "ldr q4, [x28, #3600]",
         "eor v3.16b, v3.16b, v4.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -10903,7 +10903,7 @@
         "add w22, w22, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x12, x28, x22, lsl #4",
-        "ldr q5, [x28, #3584]",
+        "ldr q5, [x28, #3600]",
         "eor v4.16b, v4.16b, v5.16b",
         "ldur s5, [x5, #-4]",
         "str x30, [sp, #-16]!",
@@ -11028,7 +11028,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3584]",
+        "ldr q6, [x28, #3600]",
         "eor v5.16b, v5.16b, v6.16b",
         "ldr s6, [x5, #4]",
         "str x30, [sp, #-16]!",
@@ -12174,7 +12174,7 @@
         "ldr x30, [sp], #16",
         "mov v4.16b, v0.16b",
         "ldr w9, [x8, #48]",
-        "ldr q5, [x28, #3584]",
+        "ldr q5, [x28, #3600]",
         "eor v4.16b, v4.16b, v5.16b",
         "ldr s5, [x9, #12]",
         "str x30, [sp, #-16]!",
@@ -12302,7 +12302,7 @@
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
         "ldr w9, [x8, #48]",
-        "ldr q6, [x28, #3584]",
+        "ldr q6, [x28, #3600]",
         "eor v5.16b, v5.16b, v6.16b",
         "ldr s6, [x9, #4]",
         "str x30, [sp, #-16]!",
@@ -14021,7 +14021,7 @@
         "add w22, w20, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x23, x28, x22, lsl #4",
-        "ldr q4, [x28, #3584]",
+        "ldr q4, [x28, #3600]",
         "eor v3.16b, v3.16b, v4.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v3.16b",
@@ -22326,7 +22326,7 @@
         "add w22, w22, #0x7 (7)",
         "and w22, w22, #0x7",
         "add x13, x28, x22, lsl #4",
-        "ldr q6, [x28, #3584]",
+        "ldr q6, [x28, #3600]",
         "eor v5.16b, v5.16b, v6.16b",
         "add w14, w4, w10, lsl #2",
         "ldur s6, [x14, #-4]",
@@ -22927,7 +22927,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3584]",
+        "ldr q6, [x28, #3600]",
         "eor v5.16b, v5.16b, v6.16b",
         "add w15, w4, w10, lsl #2",
         "ldr s6, [x15, #4]",
@@ -23397,7 +23397,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v6.16b, v0.16b",
-        "ldr q7, [x28, #3584]",
+        "ldr q7, [x28, #3600]",
         "eor v6.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v5.16b",
@@ -23485,7 +23485,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v5.16b, v0.16b",
-        "ldr q6, [x28, #3584]",
+        "ldr q6, [x28, #3600]",
         "eor v5.16b, v5.16b, v6.16b",
         "add w15, w4, w10, lsl #2",
         "ldr s6, [x15, #12]",
@@ -25586,7 +25586,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v6.16b, v0.16b",
-        "ldr q7, [x28, #3584]",
+        "ldr q7, [x28, #3600]",
         "eor v6.16b, v6.16b, v7.16b",
         "str x30, [sp, #-16]!",
         "mov v0.16b, v5.16b",
diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json
index 021a095c3..32e7b0afe 100644
--- a/unittests/InstructionCountCI/FlagM/x87.json
+++ b/unittests/InstructionCountCI/FlagM/x87.json
@@ -2468,7 +2468,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "eor v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2482,7 +2482,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "bic v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2548,7 +2548,7 @@
         "0xd9 11b 0xe8 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3360]",
+        "ldr q2, [x28, #3376]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2568,7 +2568,7 @@
         "0xd9 11b 0xe9 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3376]",
+        "ldr q2, [x28, #3392]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2588,7 +2588,7 @@
         "0xd9 11b 0xea /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3392]",
+        "ldr q2, [x28, #3408]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2608,7 +2608,7 @@
         "0xd9 11b 0xeb /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3408]",
+        "ldr q2, [x28, #3424]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2628,7 +2628,7 @@
         "0xd9 11b 0xec /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3424]",
+        "ldr q2, [x28, #3440]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2648,7 +2648,7 @@
         "0xd9 11b 0xed /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3440]",
+        "ldr q2, [x28, #3456]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2742,7 +2742,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3360]",
+        "ldr q3, [x28, #3376]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
         "strb wzr, [x28, #1050]",
@@ -2900,7 +2900,7 @@
         "0xd9 11b 0xf9 /7"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3360]",
+        "ldr q2, [x28, #3376]",
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q3, [x21, #1056]",
diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json
index fac17f9b9..a352f2498 100644
--- a/unittests/InstructionCountCI/FlagM/x87_f64.json
+++ b/unittests/InstructionCountCI/FlagM/x87_f64.json
@@ -2287,7 +2287,7 @@
       ]
     },
     "fprem1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 16,
       "Comment": [
         "0xd9 11b 0xf5 /6"
       ],
@@ -2299,11 +2299,10 @@
         "ldr d2, [x21, #1056]",
         "add x20, x28, x20, lsl #4",
         "ldr d3, [x20, #1056]",
-        "str x30, [sp, #-16]!",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #2296]",
-        "ldr x3, [x28, #2304]",
+        "ldr x0, [x28, #3048]",
+        "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",
@@ -2336,7 +2335,7 @@
       ]
     },
     "fprem": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 16,
       "Comment": [
         "0xd9 11b 0xf8 /7"
       ],
@@ -2348,11 +2347,10 @@
         "ldr d2, [x21, #1056]",
         "add x20, x28, x20, lsl #4",
         "ldr d3, [x20, #1056]",
-        "str x30, [sp, #-16]!",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #2280]",
-        "ldr x3, [x28, #2288]",
+        "ldr x0, [x28, #3040]",
+        "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",
diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json
index 9b42b4a90..ea75c5d3e 100644
--- a/unittests/InstructionCountCI/H0F38.json
+++ b/unittests/InstructionCountCI/H0F38.json
@@ -685,7 +685,7 @@
         "0x66 0x0f 0x38 0x41"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json
index 60c313901..55f92cc4d 100644
--- a/unittests/InstructionCountCI/H0F3A.json
+++ b/unittests/InstructionCountCI/H0F3A.json
@@ -327,7 +327,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3232]",
+        "ldr q2, [x28, #3248]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -337,7 +337,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3248]",
+        "ldr q2, [x28, #3264]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -356,7 +356,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3264]",
+        "ldr q2, [x28, #3280]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -376,7 +376,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3280]",
+        "ldr q2, [x28, #3296]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -395,7 +395,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3296]",
+        "ldr q2, [x28, #3312]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -405,7 +405,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3312]",
+        "ldr q2, [x28, #3328]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json
index 019bcf345..7fb3cc633 100644
--- a/unittests/InstructionCountCI/Secondary.json
+++ b/unittests/InstructionCountCI/Secondary.json
@@ -651,7 +651,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #3200]",
+        "ldr q3, [x28, #3216]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -662,7 +662,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #3200]",
+        "ldr q3, [x28, #3216]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -3695,7 +3695,7 @@
         "mov w20, #0xffff",
         "strb w20, [x28, #1202]",
         "ldr d2, [x28, #1056]",
-        "ldr d3, [x28, #3328]",
+        "ldr d3, [x28, #3344]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.8b, v2.8b, v3.8b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json
index c488dadd9..e7bb49f1b 100644
--- a/unittests/InstructionCountCI/Secondary_OpSize.json
+++ b/unittests/InstructionCountCI/Secondary_OpSize.json
@@ -1259,7 +1259,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0x66 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.2d, v16.2d, v2.2d"
       ]
@@ -1315,7 +1315,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json
index 710deb780..b184fd947 100644
--- a/unittests/InstructionCountCI/Secondary_REP.json
+++ b/unittests/InstructionCountCI/Secondary_REP.json
@@ -118,7 +118,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, s16",
         "mov w21, #0x80000000",
-        "ldr s2, [x28, #3456]",
+        "ldr s2, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel w4, w20, w21, gt",
@@ -132,7 +132,7 @@
         "ldr s2, [x6]",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3456]",
+        "ldr s3, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -145,7 +145,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, s16",
         "mov x21, #0x8000000000000000",
-        "ldr s2, [x28, #3488]",
+        "ldr s2, [x28, #3504]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel x4, x20, x21, gt",
@@ -159,7 +159,7 @@
         "ldr s2, [x6]",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3488]",
+        "ldr s3, [x28, #3504]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -173,7 +173,7 @@
         "frinti s2, s16",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3456]",
+        "ldr s3, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -188,7 +188,7 @@
         "frinti s2, s2",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3456]",
+        "ldr s3, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -202,7 +202,7 @@
         "frinti s2, s16",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3488]",
+        "ldr s3, [x28, #3504]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -217,7 +217,7 @@
         "frinti s2, s2",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3488]",
+        "ldr s3, [x28, #3504]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -296,8 +296,8 @@
       "ExpectedInstructionCount": 6,
       "Comment": "0xf3 0x0f 0x5b",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3552]",
-        "ldr q3, [x28, #3456]",
+        "ldr q2, [x28, #3568]",
+        "ldr q3, [x28, #3472]",
         "fcvtzs v4.4s, v17.4s",
         "fcmgt v3.4s, v3.4s, v17.4s",
         "mov v16.16b, v3.16b",
diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json
index a2c8ae8e3..2c07fef7f 100644
--- a/unittests/InstructionCountCI/Secondary_REPNE.json
+++ b/unittests/InstructionCountCI/Secondary_REPNE.json
@@ -503,7 +503,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0xf2 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.4s, v16.4s, v2.4s"
       ]
diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json
index 04caafea0..a5b4c8cad 100644
--- a/unittests/InstructionCountCI/VEX_map1.json
+++ b/unittests/InstructionCountCI/VEX_map1.json
@@ -3271,7 +3271,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, s16",
         "mov w21, #0x80000000",
-        "ldr s2, [x28, #3456]",
+        "ldr s2, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel w4, w20, w21, gt",
@@ -3286,7 +3286,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, s16",
         "mov x21, #0x8000000000000000",
-        "ldr s2, [x28, #3488]",
+        "ldr s2, [x28, #3504]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel x4, x20, x21, gt",
@@ -3301,7 +3301,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, d16",
         "mov w21, #0x80000000",
-        "ldr d2, [x28, #3504]",
+        "ldr d2, [x28, #3520]",
         "mrs x22, nzcv",
         "fcmp d2, d16",
         "csel w4, w20, w21, gt",
@@ -3316,7 +3316,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, d16",
         "mov x21, #0x8000000000000000",
-        "ldr d2, [x28, #3536]",
+        "ldr d2, [x28, #3552]",
         "mrs x22, nzcv",
         "fcmp d2, d16",
         "csel x4, x20, x21, gt",
@@ -3332,7 +3332,7 @@
         "frinti s2, s16",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3456]",
+        "ldr s3, [x28, #3472]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -3348,7 +3348,7 @@
         "frinti s2, s16",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3488]",
+        "ldr s3, [x28, #3504]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -3364,7 +3364,7 @@
         "frinti d2, d16",
         "fcvtzs w20, d2",
         "mov w21, #0x80000000",
-        "ldr d3, [x28, #3504]",
+        "ldr d3, [x28, #3520]",
         "mrs x22, nzcv",
         "fcmp d3, d2",
         "csel w4, w20, w21, gt",
@@ -3380,7 +3380,7 @@
         "frinti d2, d16",
         "fcvtzs x20, d2",
         "mov x21, #0x8000000000000000",
-        "ldr d3, [x28, #3536]",
+        "ldr d3, [x28, #3552]",
         "mrs x22, nzcv",
         "fcmp d3, d2",
         "csel x4, x20, x21, gt",
@@ -3643,8 +3643,8 @@
       ],
       "ExpectedArm64ASM": [
         "frinti v2.4s, v17.4s",
-        "ldr q3, [x28, #3552]",
-        "ldr q4, [x28, #3456]",
+        "ldr q3, [x28, #3568]",
+        "ldr q4, [x28, #3472]",
         "fcvtzs v5.4s, v2.4s",
         "fcmgt v2.4s, v4.4s, v2.4s",
         "mov v16.16b, v2.16b",
@@ -3678,8 +3678,8 @@
         "Map 1 0b10 0x5b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3552]",
-        "ldr q3, [x28, #3456]",
+        "ldr q2, [x28, #3568]",
+        "ldr q3, [x28, #3472]",
         "fcvtzs v4.4s, v17.4s",
         "fcmgt v3.4s, v3.4s, v17.4s",
         "mov v16.16b, v3.16b",
@@ -4429,7 +4429,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d"
       ]
@@ -4452,7 +4452,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s"
       ]
@@ -4589,7 +4589,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3344]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -4981,8 +4981,8 @@
         "Map 1 0b01 0xe6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr d2, [x28, #3552]",
-        "ldr q3, [x28, #3504]",
+        "ldr d2, [x28, #3568]",
+        "ldr q3, [x28, #3520]",
         "fcvtzs z4.s, p6/m, z17.d",
         "uzp1 z4.s, z4.s, z4.s",
         "mov v4.8b, v4.8b",
@@ -4998,7 +4998,7 @@
         "Map 1 0b01 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "ldr x0, [x28, #2592]",
         "ld1b {z3.b}, p7/z, [x0]",
         "fcvtzs z4.s, p7/m, z17.d",
@@ -5042,8 +5042,8 @@
       ],
       "ExpectedArm64ASM": [
         "frinti v2.2d, v17.2d",
-        "ldr d3, [x28, #3552]",
-        "ldr q4, [x28, #3504]",
+        "ldr d3, [x28, #3568]",
+        "ldr q4, [x28, #3520]",
         "fcvtzs z5.s, p6/m, z2.d",
         "uzp1 z5.s, z5.s, z5.s",
         "mov v5.8b, v5.8b",
@@ -5060,7 +5060,7 @@
       ],
       "ExpectedArm64ASM": [
         "frinti z2.d, p7/m, z17.d",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "ldr x0, [x28, #2592]",
         "ld1b {z4.b}, p7/z, [x0]",
         "fcvtzs z5.s, p7/m, z2.d",
diff --git a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json
index 06133aa3c..c20308a7f 100644
--- a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json
+++ b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json
@@ -173,7 +173,7 @@
         "Map 1 0b01 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3552]",
+        "ldr q2, [x28, #3568]",
         "ldr x0, [x28, #2592]",
         "ld1b {z3.b}, p7/z, [x0]",
         "fcvtzs z4.s, p7/m, z17.d",
@@ -208,7 +208,7 @@
       ],
       "ExpectedArm64ASM": [
         "frinti z2.d, p7/m, z17.d",
-        "ldr q3, [x28, #3552]",
+        "ldr q3, [x28, #3568]",
         "ldr x0, [x28, #2592]",
         "ld1b {z4.b}, p7/z, [x0]",
         "fcvtzs z5.s, p7/m, z2.d",
diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json
index 29a823194..128c59a2b 100644
--- a/unittests/InstructionCountCI/VEX_map2.json
+++ b/unittests/InstructionCountCI/VEX_map2.json
@@ -1603,7 +1603,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3056]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
@@ -3657,7 +3657,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.4s, v16.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -3683,7 +3683,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.2d, v16.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -3709,7 +3709,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.4s, v16.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -3735,7 +3735,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3168]",
+        "ldr q2, [x28, #3184]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.2d, v16.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -4609,7 +4609,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.4s, v17.4s, v16.4s",
         "mov v16.16b, v2.16b"
@@ -4635,7 +4635,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.2d, v17.2d, v16.2d",
         "mov v16.16b, v2.16b"
@@ -4661,7 +4661,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.4s, v17.4s, v16.4s",
         "mov v16.16b, v2.16b"
@@ -4687,7 +4687,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3168]",
+        "ldr q2, [x28, #3184]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.2d, v17.2d, v16.2d",
         "mov v16.16b, v2.16b"
@@ -4713,7 +4713,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3072]",
+        "ldr q2, [x28, #3088]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.4s, v17.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -4738,7 +4738,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3104]",
+        "ldr q2, [x28, #3120]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.2d, v17.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -4763,7 +4763,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3136]",
+        "ldr q2, [x28, #3152]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.4s, v17.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -4788,7 +4788,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3168]",
+        "ldr q2, [x28, #3184]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.2d, v17.2d, v18.2d",
         "mov v16.16b, v2.16b"
diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json
index 539426d90..0372c517d 100644
--- a/unittests/InstructionCountCI/VEX_map3.json
+++ b/unittests/InstructionCountCI/VEX_map3.json
@@ -5372,7 +5372,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -5385,7 +5385,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3216]",
+        "ldr q2, [x28, #3232]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json
index 4ee49dce8..6d706bb89 100644
--- a/unittests/InstructionCountCI/x87.json
+++ b/unittests/InstructionCountCI/x87.json
@@ -2467,7 +2467,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "eor v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2481,7 +2481,7 @@
         "ldrb w20, [x28, #1051]",
         "add x20, x28, x20, lsl #4",
         "ldr q2, [x20, #1056]",
-        "ldr q3, [x28, #3584]",
+        "ldr q3, [x28, #3600]",
         "bic v2.16b, v2.16b, v3.16b",
         "str q2, [x20, #1056]"
       ]
@@ -2547,7 +2547,7 @@
         "0xd9 11b 0xe8 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3360]",
+        "ldr q2, [x28, #3376]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2567,7 +2567,7 @@
         "0xd9 11b 0xe9 /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3376]",
+        "ldr q2, [x28, #3392]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2587,7 +2587,7 @@
         "0xd9 11b 0xea /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3392]",
+        "ldr q2, [x28, #3408]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2607,7 +2607,7 @@
         "0xd9 11b 0xeb /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3408]",
+        "ldr q2, [x28, #3424]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2627,7 +2627,7 @@
         "0xd9 11b 0xec /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3424]",
+        "ldr q2, [x28, #3440]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2647,7 +2647,7 @@
         "0xd9 11b 0xed /5"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3440]",
+        "ldr q2, [x28, #3456]",
         "ldrb w20, [x28, #1051]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
@@ -2741,7 +2741,7 @@
         "blr x0",
         "ldr x30, [sp], #16",
         "mov v2.16b, v0.16b",
-        "ldr q3, [x28, #3360]",
+        "ldr q3, [x28, #3376]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
         "strb wzr, [x28, #1050]",
@@ -2899,7 +2899,7 @@
         "0xd9 11b 0xf9 /7"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3360]",
+        "ldr q2, [x28, #3376]",
         "ldrb w20, [x28, #1051]",
         "add x21, x28, x20, lsl #4",
         "ldr q3, [x21, #1056]",
diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json
index 557bfe7d2..7b4292f73 100644
--- a/unittests/InstructionCountCI/x87_f64.json
+++ b/unittests/InstructionCountCI/x87_f64.json
@@ -2305,7 +2305,7 @@
       ]
     },
     "fprem1": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 16,
       "Comment": [
         "0xd9 11b 0xf5 /6"
       ],
@@ -2317,11 +2317,10 @@
         "ldr d2, [x21, #1056]",
         "add x20, x28, x20, lsl #4",
         "ldr d3, [x20, #1056]",
-        "str x30, [sp, #-16]!",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #2296]",
-        "ldr x3, [x28, #2304]",
+        "ldr x0, [x28, #3048]",
+        "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",
@@ -2354,7 +2353,7 @@
       ]
     },
     "fprem": {
-      "ExpectedInstructionCount": 17,
+      "ExpectedInstructionCount": 16,
       "Comment": [
         "0xd9 11b 0xf8 /7"
       ],
@@ -2366,11 +2365,10 @@
         "ldr d2, [x21, #1056]",
         "add x20, x28, x20, lsl #4",
         "ldr d3, [x20, #1056]",
-        "str x30, [sp, #-16]!",
         "fmov d0, d3",
         "fmov d1, d2",
-        "ldr x0, [x28, #2280]",
-        "ldr x3, [x28, #2288]",
+        "ldr x0, [x28, #3040]",
+        "str x30, [sp, #-16]!",
         "blr x0",
         "ldr x30, [sp], #16",
         "fmov d2, d0",