FEXCore: Implements support for RPRES

This allows us to use reciprocal instructions which matches precision of
what x86 expects rather than converting everything to float divides.

Currently no hardware supports this, and even the upcoming X4/A720/A520
won't support it, but it was trivial to implement so wire it up.

Scripts/InstructionCountParser.py

@@ -49,6 +49,8 @@ class HostFeatures(Flag) :
     FEATURE_FCMA   = (1 << 4)
     FEATURE_CSSC   = (1 << 5)
     FEATURE_AFP    = (1 << 6)
+    FEATURE_RPRES  = (1 << 7)
+
 
 HostFeaturesLookup = {
     "SVE128"  : HostFeatures.FEATURE_SVE128,
@@ -58,6 +60,7 @@ HostFeaturesLookup = {
     "FCMA"    : HostFeatures.FEATURE_FCMA,
     "CSSC"    : HostFeatures.FEATURE_CSSC,
     "AFP"     : HostFeatures.FEATURE_AFP,
+    "RPRES"   : HostFeatures.FEATURE_RPRES,
 }
 
 def GetHostFeatures(data):