diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index 7b6dae994..bb538464a 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -2351,7 +2351,7 @@ void OpDispatchBuilder::BLSIBMIOp(OpcodeArgs) {
   // Equivalent to performing: SRC & -SRC
 
   auto* Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, -1);
-  auto NegatedSrc = _Neg(Src);
+  auto NegatedSrc = _Neg(IR::SizeToOpSize(GetSrcSize(Op)), Src);
   auto Result = _And(Src, NegatedSrc);
 
   // ...and we're done. Painless!
@@ -4336,11 +4336,11 @@ void OpDispatchBuilder::NEGOp(OpcodeArgs) {
     DestMem = AppendSegmentOffset(DestMem, Op->Flags);
 
     Dest = _AtomicFetchNeg(Size, DestMem);
-    Result = _Neg(Dest);
+    Result = _Neg(Size == 8 ? OpSize::i64Bit : OpSize::i32Bit, Dest);
   }
   else {
     Dest = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, -1);
-    Result = _Neg(Dest);
+    Result = _Neg(Size == 8 ? OpSize::i64Bit : OpSize::i32Bit, Dest);
 
     StoreResult(GPRClass, Op, Result, -1);
   }
diff --git a/FEXCore/include/FEXCore/IR/IREmitter.h b/FEXCore/include/FEXCore/IR/IREmitter.h
index f3e1f15b4..b62eb8e7d 100644
--- a/FEXCore/include/FEXCore/IR/IREmitter.h
+++ b/FEXCore/include/FEXCore/IR/IREmitter.h
@@ -152,9 +152,6 @@ friend class FEXCore::IR::PassManager;
     return _AtomicFetchNeg(static_cast<OpSize>(Size), _Addr);
   }
   ///< ALU
-  IRPair<IROp_Neg> _Neg(OrderedNode *_Src) {
-    return _Neg(static_cast<OpSize>(std::max<uint8_t>(4, GetOpSize(_Src))), _Src);
-  }
   IRPair<IROp_Abs> _Abs(OrderedNode *_Src) {
     return _Abs(static_cast<OpSize>(std::max<uint8_t>(4, GetOpSize(_Src))), _Src);
   }