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Merge pull request #3562 from Sonicadvance1/fix_rsp_store_tso

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OpcodeDispatcher: Fixes disabling TSO access on RSP SIB stores
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Ryan Houdek authored and GitHub committed 2024-04-11 00:32:14 -07:00
2 parents a0f2cae1cb 0e93fd0f3e
commit 1ba678f631
1 file changed
+12 -7
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FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+12 -7
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@@ -4457,9 +4457,6 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
auto Constant = _Constant(GPRSize * 8, Operand.Data.SIB.Scale);
Tmp = _Mul(IR::SizeToOpSize(GPRSize), Tmp, Constant);
}
if (Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP && AccessType == MemoryAccessType::DEFAULT) {
AccessType = MemoryAccessType::NONTSO;
}
}
if (Operand.Data.SIB.Base != FEXCore::X86State::REG_INVALID) {
@@ -4471,10 +4468,6 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
else {
Tmp = GPR;
}
if (Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP && AccessType == MemoryAccessType::DEFAULT) {
AccessType = MemoryAccessType::NONTSO;
}
}
}
@@ -4495,6 +4488,12 @@ OrderedNode *OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, X
}
}
if ((Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP ||
Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP)
&& AccessType == MemoryAccessType::DEFAULT) {
AccessType = MemoryAccessType::NONTSO;
}
LoadableType = true;
}
else {
@@ -4744,6 +4743,12 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
MemStoreDst = _Bfe(IR::SizeToOpSize(std::max<uint8_t>(4u, AddrSize)), AddrSize * 8, 0, MemStoreDst);
}
if ((Operand.Data.SIB.Base == FEXCore::X86State::REG_RSP ||
Operand.Data.SIB.Index == FEXCore::X86State::REG_RSP)
&& AccessType == MemoryAccessType::DEFAULT) {
AccessType = MemoryAccessType::NONTSO;
}
MemStore = true;
}