From 16d5ca447fa38d46df4e29d474ce51ea536cce41 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Thu, 19 Jun 2025 16:21:19 -0700
Subject: [PATCH] FEXCore: DebugData is never null now

This is a required data structure to exist.

CID 482036
---
 FEXCore/Source/Interface/Core/Core.cpp    | 11 +++++------
 FEXCore/Source/Interface/Core/JIT/JIT.cpp | 12 ++++--------
 2 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/FEXCore/Source/Interface/Core/Core.cpp b/FEXCore/Source/Interface/Core/Core.cpp
index 990ccb2ad..f726bd995 100644
--- a/FEXCore/Source/Interface/Core/Core.cpp
+++ b/FEXCore/Source/Interface/Core/Core.cpp
@@ -771,14 +771,8 @@ ContextImpl::CompileCodeResult ContextImpl::CompileCode(FEXCore::Core::InternalT
   if (!IRView) {
     return {nullptr, nullptr, 0, 0};
   }
-  auto DebugData = fextl::make_unique<FEXCore::Core::DebugData>();
-
-  // If the trap flag is set we generate single instruction blocks that each check to generate a single step exception.
-  bool TFSet = Thread->CurrentFrame->State.flags[X86State::RFLAG_TF_RAW_LOC];
 
   // Attempt to get the CPU backend to compile this code
-
-
   // Re-check if another thread raced us in compiling this block.
   // We could lock CodeBufferWriteMutex earlier to prevent this from happening,
   // but this would increase lock contention. Redundant frontend runs aren't
@@ -790,6 +784,11 @@ ContextImpl::CompileCodeResult ContextImpl::CompileCode(FEXCore::Core::InternalT
     }
   }
 
+  auto DebugData = fextl::make_unique<FEXCore::Core::DebugData>();
+
+  // If the trap flag is set we generate single instruction blocks that each check to generate a single step exception.
+  bool TFSet = Thread->CurrentFrame->State.flags[X86State::RFLAG_TF_RAW_LOC];
+
   auto CompiledCode = Thread->CPUBackend->CompileCode(GuestRIP, Length, TotalInstructions == 1, &*IRView, DebugData.get(), TFSet);
 
   // Release the IR
diff --git a/FEXCore/Source/Interface/Core/JIT/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/JIT.cpp
index f0666f501..79d8303ee 100644
--- a/FEXCore/Source/Interface/Core/JIT/JIT.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/JIT.cpp
@@ -793,10 +793,8 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size
       }
     }
 
-    if (DebugData) {
-      DebugData->Subblocks.push_back({static_cast<uint32_t>(BlockStartHostCode - CodeData.BlockEntry),
-                                      static_cast<uint32_t>(GetCursorAddress<uint8_t*>() - BlockStartHostCode)});
-    }
+    DebugData->Subblocks.push_back({static_cast<uint32_t>(BlockStartHostCode - CodeData.BlockEntry),
+                                    static_cast<uint32_t>(GetCursorAddress<uint8_t*>() - BlockStartHostCode)});
   }
 
   // Make sure last branch is generated. It certainly can't be eliminated here.
@@ -939,10 +937,8 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size
   }
 #endif
 
-  if (DebugData) {
-    DebugData->HostCodeSize = CodeData.Size;
-    DebugData->Relocations = &Relocations;
-  }
+  DebugData->HostCodeSize = CodeData.Size;
+  DebugData->Relocations = &Relocations;
 
   this->IR = nullptr;