From 13974df20487df394d72eb8ab76a1d4e2f0e6a41 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Date: Sat, 10 Aug 2024 16:15:00 -0400
Subject: [PATCH] IR: drop CASPair pair result

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
---
 .../Source/Interface/Core/JIT/Arm64/AtomicOps.cpp | 15 ++++++++-------
 .../Source/Interface/Core/OpcodeDispatcher.cpp    |  5 +++--
 FEXCore/Source/Interface/IR/IR.json               | 10 ++++------
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp
index 05412066c..6d1d93119 100644
--- a/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/Arm64/AtomicOps.cpp
@@ -15,7 +15,8 @@ DEF_OP(CASPair) {
   auto Op = IROp->C<IR::IROp_CASPair>();
   LOGMAN_THROW_AA_FMT(IROp->ElementSize == 4 || IROp->ElementSize == 8, "Wrong element size");
   // Size is the size of each pair element
-  auto Dst = GetRegPair(Node);
+  auto Dst0 = GetReg(Op->OutLo.ID());
+  auto Dst1 = GetReg(Op->OutHi.ID());
   auto Expected0 = GetReg(Op->ExpectedLo.ID());
   auto Expected1 = GetReg(Op->ExpectedHi.ID());
   auto Desired0 = GetReg(Op->DesiredLo.ID());
@@ -35,8 +36,8 @@ DEF_OP(CASPair) {
     mov(EmitSize, TMP4, Expected1);
 
     caspal(EmitSize, TMP3, TMP4, Desired0, Desired1, MemSrc);
-    mov(EmitSize, Dst.first, TMP3.R());
-    mov(EmitSize, Dst.second, TMP4.R());
+    mov(EmitSize, Dst0, TMP3.R());
+    mov(EmitSize, Dst1, TMP4.R());
   } else {
     // Save NZCV so we don't have to mark this op as clobbering NZCV (the
     // SupportsAtomics does not clobber atomics and this !SupportsAtomics path
@@ -57,14 +58,14 @@ DEF_OP(CASPair) {
     b(ARMEmitter::Condition::CC_NE, &LoopNotExpected);
     stlxp(EmitSize, TMP2, Desired0, Desired1, MemSrc);
     cbnz(EmitSize, TMP2, &LoopTop);
-    mov(EmitSize, Dst.first, Expected0);
-    mov(EmitSize, Dst.second, Expected1);
+    mov(EmitSize, Dst0, Expected0);
+    mov(EmitSize, Dst1, Expected1);
 
     b(&LoopExpected);
 
     Bind(&LoopNotExpected);
-    mov(EmitSize, Dst.first, TMP2.R());
-    mov(EmitSize, Dst.second, TMP3.R());
+    mov(EmitSize, Dst0, TMP2.R());
+    mov(EmitSize, Dst1, TMP3.R());
     // exclusive monitor needs to be cleared here
     // Might have hit the case where ldaxr was hit but stlxr wasn't
     clrex();
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index f52deacba..8924e6baf 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -3992,8 +3992,9 @@ void OpDispatchBuilder::CMPXCHGPairOp(OpcodeArgs) {
   // This will write to memory! Careful!
   // Third operand must be a calculated guest memory address
 
-  Ref CASResult = _CASPair(IR::SizeToOpSize(Size * 2), Expected_Lower, Expected_Upper, Desired_Lower, Desired_Upper, Src1);
-  auto [Result_Lower, Result_Upper] = ExtractPair(IR::SizeToOpSize(Size), CASResult);
+  Ref Result_Lower = _AllocateGPR();
+  Ref Result_Upper = _AllocateGPR();
+  _CASPair(IR::SizeToOpSize(Size), Expected_Lower, Expected_Upper, Desired_Lower, Desired_Upper, Src1, Result_Lower, Result_Upper);
 
   HandleNZCV_RMW();
   _CmpPairZ(IR::SizeToOpSize(Size), Result_Lower, Result_Upper, Expected_Lower, Expected_Upper);
diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index f92880f7e..0e72996a9 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -711,19 +711,17 @@
           "Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
         ]
       },
-      "GPRPair = CASPair OpSize:#Size, GPR:$ExpectedLo, GPR:$ExpectedHi, GPR:$DesiredLo, GPR:$DesiredHi, GPR:$Addr": {
-        "HasSideEffects": true,
+      "GPR:$Lo, GPR:$Hi = CASPair OpSize:#Size, GPR:$ExpectedLo, GPR:$ExpectedHi, GPR:$DesiredLo, GPR:$DesiredHi, GPR:$Addr": {
         "Desc": ["Does a compare and exchange with two pairs of values",
                  "ssa0 is the comparison value",
                  "ssa1 is the new value",
                  "ssa2 is the memory location",
-                 "Returns a pair containing the value in memory"
+                 "Returns the lower & upper halves of the value in memory."
                 ],
-        "HasDest": true,
+        "HasSideEffects": true,
         "DestSize": "Size",
-        "NumElements": "2",
         "EmitValidation": [
-          "Size == FEXCore::IR::OpSize::i64Bit || Size == FEXCore::IR::OpSize::i128Bit"
+          "Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
         ]
       },
       "AtomicAdd OpSize:#Size, GPR:$Value, GPR:$Addr": {