From 0ddd46ba44faf2ee6dc2e3d5c44baa6420c196c8 Mon Sep 17 00:00:00 2001 From: Justin Becker Date: Tue, 22 Sep 2026 11:20:26 -0700 Subject: [PATCH] Bump DiskCacheVersion --- FEXCore/Source/Interface/Core/DiskCache.h | 2 +- unittests/InstructionCountCI/AFP/H0F3A.json | 2 +- .../AFP/SVE256/Secondary.json | 2 +- .../AFP/SVE256/Secondary_REP.json | 2 +- .../AFP/SVE256/Secondary_REPNE.json | 2 +- .../InstructionCountCI/AFP/Secondary.json | 2 +- .../InstructionCountCI/AFP/Secondary_REP.json | 2 +- .../AFP/Secondary_REPNE.json | 2 +- .../InstructionCountCI/AFP/VEX_map1.json | 2 +- .../InstructionCountCI/AFP/VEX_map3.json | 2 +- unittests/InstructionCountCI/AVX128/FMA4.json | 62 +- .../InstructionCountCI/AVX128/VEX_map1.json | 68 +- .../AVX128/VEX_map1_FCMA.json | 2 +- .../AVX128/VEX_map1_SVE128.json | 2 +- .../AVX128/VEX_map1_flagm.json | 2 +- .../InstructionCountCI/AVX128/VEX_map2.json | 52 +- .../AVX128/VEX_map2_AFP.json | 2 +- .../AVX128/VEX_map2_DOTPROD.json | 2 +- .../AVX128/VEX_map2_I8MM.json | 2 +- .../AVX128/VEX_map2_SVE128.json | 50 +- .../AVX128/VEX_map2_flagm.json | 2 +- .../InstructionCountCI/AVX128/VEX_map3.json | 18 +- .../AVX128/VEX_map3_SVE128.json | 2 +- .../AVX128/VEX_map_group.json | 2 +- unittests/InstructionCountCI/Atomics.json | 2 +- .../InstructionCountCI/Crypto/H0F38.json | 2 +- .../Crypto/H0F38_SVE128.json | 2 +- .../InstructionCountCI/Crypto/H0F3A.json | 22 +- unittests/InstructionCountCI/DDD.json | 2 +- .../FEXOpt/AddressingLimitations.json | 2 +- .../FEXOpt/AddressingLimitations_32Bit.json | 2 +- .../InstructionCountCI/FEXOpt/MultiInst.json | 2 +- .../FEXOpt/MultiInst_32bit.json | 2 +- .../FEXOpt/MultiInst_AFP.json | 2 +- .../FEXOpt/MultiInst_TSO.json | 2 +- .../FEXOpt/MultiInst_TSO_32bit.json | 2 +- .../InstructionCountCI/FEXOpt/libnss.json | 2 +- .../InstructionCountCI/FlagM/Atomics.json | 2 +- .../InstructionCountCI/FlagM/FlagOpts.json | 2 +- unittests/InstructionCountCI/FlagM/H0F38.json | 2 +- .../InstructionCountCI/FlagM/HotBlocks.json | 4 +- .../FlagM/HotBlocks_32Bit.json | 2 +- .../FlagM/HotBlocks_AFP.json | 2 +- .../FlagM/HotBlocks_TSO_32Bit.json | 2 +- .../InstructionCountCI/FlagM/Primary.json | 2 +- .../FlagM/PrimaryGroup.json | 2 +- .../FlagM/Primary_32Bit.json | 2 +- .../InstructionCountCI/FlagM/Secondary.json | 4 +- .../FlagM/SecondaryGroup.json | 2 +- .../FlagM/SecondaryModRM.json | 2 +- .../FlagM/Secondary_OpSize.json | 4 +- .../FlagM/Secondary_REP.json | 2 +- .../FlagM/Secondary_REP_CSSC.json | 2 +- .../InstructionCountCI/FlagM/VEX_map1.json | 6 +- .../InstructionCountCI/FlagM/VEX_map2.json | 2 +- .../FlagM/VEX_map_group.json | 2 +- .../FlagM/x87-Crysis2Max-fmodel.json | 2 +- .../FlagM/x87-HalfLife.json | 14 +- .../FlagM/x87-Oblivion.json | 76 +- .../FlagM/x87-Psychonauts.json | 24 +- unittests/InstructionCountCI/FlagM/x87.json | 20 +- .../FlagM/x87_f64-Crysis2Max-fmodel.json | 2 +- .../FlagM/x87_f64-HalfLife.json | 2 +- .../FlagM/x87_f64-Oblivion.json | 2 +- .../FlagM/x87_f64-Psychonauts.json | 2 +- .../InstructionCountCI/FlagM/x87_f64.json | 26 +- unittests/InstructionCountCI/H0F38.json | 4 +- unittests/InstructionCountCI/H0F3A.json | 16 +- .../InstructionCountCI/H0F3A_SVE128.json | 2 +- .../InstructionCountCI/MOPS/Primary.json | 2 +- unittests/InstructionCountCI/Primary.json | 8 +- .../InstructionCountCI/PrimaryGroup.json | 6 +- .../InstructionCountCI/Primary_32Bit.json | 2 +- unittests/InstructionCountCI/RPRES/DDD.json | 2 +- .../InstructionCountCI/RPRES/Secondary.json | 2 +- .../RPRES/Secondary_REP_AFP.json | 2 +- .../RPRES/VEX_map1_AFP.json | 2 +- unittests/InstructionCountCI/Repeat.json | 2 +- .../InstructionCountCI/SSE42_Strings.json | 1282 ++++++++--------- unittests/InstructionCountCI/Secondary.json | 14 +- .../InstructionCountCI/SecondaryGroup.json | 2 +- .../InstructionCountCI/SecondaryModRM.json | 2 +- .../InstructionCountCI/Secondary_32Bit.json | 2 +- .../InstructionCountCI/Secondary_OpSize.json | 12 +- .../Secondary_OpSize_FCMA.json | 2 +- .../Secondary_OpSize_SVE128.json | 2 +- .../Secondary_OpSize_SVE256.json | 2 +- .../InstructionCountCI/Secondary_REP.json | 26 +- .../InstructionCountCI/Secondary_REPNE.json | 8 +- .../Secondary_REPNE_FCMA.json | 2 +- .../Secondary_REPNE_SVE128.json | 2 +- .../Secondary_REP_FRINTTS.json | 2 +- .../InstructionCountCI/Secondary_SVE128.json | 2 +- unittests/InstructionCountCI/VEX_map1.json | 124 +- .../InstructionCountCI/VEX_map1_FCMA.json | 2 +- .../InstructionCountCI/VEX_map1_FRINTTS.json | 18 +- unittests/InstructionCountCI/VEX_map2.json | 66 +- .../InstructionCountCI/VEX_map2_DOTPROD.json | 2 +- .../InstructionCountCI/VEX_map2_I8MM.json | 2 +- .../VEX_map2_svebitperm.json | 2 +- unittests/InstructionCountCI/VEX_map3.json | 6 +- .../InstructionCountCI/VEX_map_group.json | 2 +- unittests/InstructionCountCI/X87ldst-SVE.json | 2 +- unittests/InstructionCountCI/x87.json | 20 +- unittests/InstructionCountCI/x87_32Bit.json | 2 +- unittests/InstructionCountCI/x87_f64.json | 26 +- .../InstructionCountCI/x87_f64_32Bit.json | 2 +- 107 files changed, 1120 insertions(+), 1120 deletions(-) diff --git a/FEXCore/Source/Interface/Core/DiskCache.h b/FEXCore/Source/Interface/Core/DiskCache.h index a356a0f33..59ee62f18 100644 --- a/FEXCore/Source/Interface/Core/DiskCache.h +++ b/FEXCore/Source/Interface/Core/DiskCache.h @@ -249,7 +249,7 @@ namespace DiskCache { // The current version of the diskcache. // This must be changed any time codegen changes occur! // Be aware of the impact of changing this frequently! - static constexpr uint16_t FormatVersion = 27; + static constexpr uint16_t FormatVersion = 28; static constexpr uint32_t LOOKUP_KEY_MAX_BUCKET_DEPTH = 500; diff --git a/unittests/InstructionCountCI/AFP/H0F3A.json b/unittests/InstructionCountCI/AFP/H0F3A.json index 1ad129c8e..2d98dfad4 100644 --- a/unittests/InstructionCountCI/AFP/H0F3A.json +++ b/unittests/InstructionCountCI/AFP/H0F3A.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "roundss xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json index 0a2e7a5d3..aa127d7bc 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "cvtpi2ps xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json index d49e2807b..8c1f3588d 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "RPRES" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json index 68fb11a02..cf45cca06 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "cvtsi2sd xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/Secondary.json b/unittests/InstructionCountCI/AFP/Secondary.json index f8cdab791..0cb97ecf5 100644 --- a/unittests/InstructionCountCI/AFP/Secondary.json +++ b/unittests/InstructionCountCI/AFP/Secondary.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "cvtpi2ps xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AFP/Secondary_REP.json b/unittests/InstructionCountCI/AFP/Secondary_REP.json index 075871bca..1e65b092b 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REP.json @@ -9,7 +9,7 @@ "SVE256", "RPRES" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json index cb0d102ef..eda5da07a 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "cvtsi2sd xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/VEX_map1.json b/unittests/InstructionCountCI/AFP/VEX_map1.json index d4e68e11b..11e098176 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map1.json +++ b/unittests/InstructionCountCI/AFP/VEX_map1.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "RPRES" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vsqrtss xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AFP/VEX_map3.json b/unittests/InstructionCountCI/AFP/VEX_map3.json index 48873942e..63b2004ad 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map3.json +++ b/unittests/InstructionCountCI/AFP/VEX_map3.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vroundss xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/AVX128/FMA4.json b/unittests/InstructionCountCI/AVX128/FMA4.json index ff62ec31a..5e0201f30 100644 --- a/unittests/InstructionCountCI/AVX128/FMA4.json +++ b/unittests/InstructionCountCI/AVX128/FMA4.json @@ -7,7 +7,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vfmaddsubps xmm0, xmm1, xmm2, xmm3": { @@ -20,7 +20,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -34,7 +34,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -48,7 +48,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -62,7 +62,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -76,7 +76,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -90,7 +90,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -104,7 +104,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -118,7 +118,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -132,7 +132,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -146,7 +146,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -160,7 +160,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -174,7 +174,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -188,7 +188,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -202,7 +202,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -216,7 +216,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -230,7 +230,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -244,7 +244,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -258,7 +258,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -272,7 +272,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -286,7 +286,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -300,7 +300,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -314,7 +314,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -328,7 +328,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -342,7 +342,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -356,7 +356,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -370,7 +370,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -384,7 +384,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -398,7 +398,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -412,7 +412,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -426,7 +426,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] } diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index 5aff54635..2df7b06df 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -13,7 +13,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vmovups xmm0, xmm0": { @@ -486,7 +486,7 @@ ], "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #3296]", + "ldr q3, [x28, #3328]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -501,7 +501,7 @@ "ldr q2, [x28, #192]", "uzp2 v2.8h, v16.8h, v2.8h", "ushr v2.8h, v2.8h, #15", - "ldr q3, [x28, #3136]", + "ldr q3, [x28, #3152]", "ushl v2.8h, v2.8h, v3.8h", "addv h2, v2.8h", "umov w4, v2.h[0]" @@ -528,7 +528,7 @@ "ldr q2, [x28, #192]", "uzp2 v2.4s, v16.4s, v2.4s", "ushr v2.4s, v2.4s, #31", - "ldr q3, [x28, #3296]", + "ldr q3, [x28, #3328]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -1116,7 +1116,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1128,7 +1128,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1140,7 +1140,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1165,7 +1165,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1179,7 +1179,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1193,7 +1193,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1217,7 +1217,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1229,7 +1229,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1241,7 +1241,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1268,7 +1268,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1282,7 +1282,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1296,7 +1296,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1320,7 +1320,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1332,7 +1332,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1344,7 +1344,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -1371,7 +1371,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1385,7 +1385,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1399,7 +1399,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -2283,7 +2283,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -2297,7 +2297,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q4, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2310,7 +2310,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -2324,7 +2324,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q4, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2337,7 +2337,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" @@ -2351,7 +2351,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q4, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -3936,7 +3936,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d", "stp xzr, xzr, [x28, #192]" @@ -3950,7 +3950,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr q4, [x28, #3200]", + "ldr q4, [x28, #3232]", "eor v5.16b, v18.16b, v4.16b", "fadd v16.2d, v17.2d, v5.2d", "eor v3.16b, v3.16b, v4.16b", @@ -3964,7 +3964,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s", "stp xzr, xzr, [x28, #192]" @@ -3978,7 +3978,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #208]", "ldr q3, [x28, #224]", - "ldr q4, [x28, #3168]", + "ldr q4, [x28, #3200]", "eor v5.16b, v18.16b, v4.16b", "fadd v16.4s, v17.4s, v5.4s", "eor v3.16b, v3.16b, v4.16b", @@ -4149,7 +4149,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3424]", + "ldr q2, [x28, #3456]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -4165,7 +4165,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #192]", - "ldr q3, [x28, #3424]", + "ldr q3, [x28, #3456]", "cmlt v4.16b, v16.16b, #0", "and v4.16b, v4.16b, v3.16b", "addp v4.16b, v4.16b, v4.16b", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json index 16de00513..ea04f603e 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vaddsubpd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json index b3ad14f9d..c026c6c7e 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json @@ -10,7 +10,7 @@ "FLAGM2", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vmovntps [rax], xmm0": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json index ae23fc522..ece7fc421 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json @@ -10,7 +10,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index 8d367936e..13680e6fb 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -11,7 +11,7 @@ "I8MM", "DOTPROD" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { @@ -1902,7 +1902,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -4695,7 +4695,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4712,7 +4712,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3200]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4728,7 +4728,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4745,7 +4745,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3232]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4761,7 +4761,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3264]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4778,7 +4778,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3264]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4794,7 +4794,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3296]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4811,7 +4811,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3264]", + "ldr q5, [x28, #3296]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -5751,7 +5751,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5768,7 +5768,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3200]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5784,7 +5784,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5801,7 +5801,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3232]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5817,7 +5817,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3264]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5834,7 +5834,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3264]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5850,7 +5850,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3296]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5867,7 +5867,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3264]", + "ldr q5, [x28, #3296]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5883,7 +5883,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5899,7 +5899,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3200]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5914,7 +5914,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5930,7 +5930,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3232]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5945,7 +5945,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3264]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5961,7 +5961,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3264]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5976,7 +5976,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3296]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5992,7 +5992,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3264]", + "ldr q5, [x28, #3296]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json index 46ed95e29..cfb244d9b 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json @@ -8,7 +8,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vfmadd132ss xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json b/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json index a1533c3c3..69c6cc126 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_DOTPROD.json @@ -12,7 +12,7 @@ "SVE256", "I8MM" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vpdpbusd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json b/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json index 811de232b..a81c6b841 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_I8MM.json @@ -11,7 +11,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vpdpbusd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json index 36d1123ba..d752cc0d8 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json @@ -10,7 +10,7 @@ "FLAGM2", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vmovntdqa xmm0, [rax]": { @@ -2844,7 +2844,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2861,7 +2861,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3200]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2877,7 +2877,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2894,7 +2894,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3232]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2910,7 +2910,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3264]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2927,7 +2927,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3264]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2943,7 +2943,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3296]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2960,7 +2960,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3264]", + "ldr q5, [x28, #3296]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -3880,7 +3880,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3897,7 +3897,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3200]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3913,7 +3913,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3930,7 +3930,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3232]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3946,7 +3946,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3264]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3963,7 +3963,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3264]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3979,7 +3979,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3296]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3996,7 +3996,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3264]", + "ldr q5, [x28, #3296]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -4012,7 +4012,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4028,7 +4028,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3168]", + "ldr q5, [x28, #3200]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4043,7 +4043,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4059,7 +4059,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3200]", + "ldr q5, [x28, #3232]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4074,7 +4074,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3264]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4090,7 +4090,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3232]", + "ldr q5, [x28, #3264]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4105,7 +4105,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3296]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4121,7 +4121,7 @@ "ldr q2, [x28, #192]", "ldr q3, [x28, #208]", "ldr q4, [x28, #224]", - "ldr q5, [x28, #3264]", + "ldr q5, [x28, #3296]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json index 6972e1b8f..1936d1636 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json @@ -11,7 +11,7 @@ "SVE256", "SVEBITPERM" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vtestps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json index 5fd0c0871..bfa03b24b 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json @@ -7,7 +7,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vpermq ymm0, ymm1, 1": { @@ -338,7 +338,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3328]", + "ldr q2, [x28, #3360]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -349,7 +349,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3344]", + "ldr q2, [x28, #3376]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -370,7 +370,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3360]", + "ldr q2, [x28, #3392]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -392,7 +392,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3376]", + "ldr q2, [x28, #3408]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -413,7 +413,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3392]", + "ldr q2, [x28, #3424]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -424,7 +424,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3408]", + "ldr q2, [x28, #3440]", "tbx v16.16b, {v17.16b}, v2.16b", "stp xzr, xzr, [x28, #192]" ] @@ -3494,7 +3494,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr q3, [x28, #3312]", + "ldr q3, [x28, #3344]", "mov v16.16b, v17.16b", "aese v16.16b, v2.16b", "tbl v16.16b, {v16.16b}, v3.16b", @@ -3508,7 +3508,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr q3, [x28, #3312]", + "ldr q3, [x28, #3344]", "mov v16.16b, v17.16b", "aese v16.16b, v2.16b", "tbl v16.16b, {v16.16b}, v3.16b", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json index 10b3d113d..2e8813eee 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json @@ -8,7 +8,7 @@ "AFP", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vblendvps xmm0, xmm1, xmm2, xmm3": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map_group.json b/unittests/InstructionCountCI/AVX128/VEX_map_group.json index 112136112..3e8fbe8e4 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map_group.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map_group.json @@ -9,7 +9,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vpsrlw xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 5ed5af517..83e36bee4 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "lock add byte [rax], cl": { diff --git a/unittests/InstructionCountCI/Crypto/H0F38.json b/unittests/InstructionCountCI/Crypto/H0F38.json index a5e4911ec..d30a57a2c 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38.json +++ b/unittests/InstructionCountCI/Crypto/H0F38.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "sha1nexte xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json index ba82cc30d..e67fd2699 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json +++ b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "sha1nexte xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index a3ea14c78..3888f2112 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "pclmulqdq xmm0, xmm1, 00000b": { @@ -56,7 +56,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3312]", + "ldr q2, [x28, #3344]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", @@ -69,7 +69,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3312]", + "ldr q2, [x28, #3344]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", @@ -85,9 +85,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3728]", + "ldr q2, [x28, #3760]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", @@ -102,9 +102,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3744]", + "ldr q2, [x28, #3776]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", @@ -119,9 +119,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3760]", + "ldr q2, [x28, #3792]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", @@ -136,9 +136,9 @@ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3776]", + "ldr q2, [x28, #3808]", "movi v3.2d, #0x0", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q4, [x0, #432]", "tbl v5.16b, {v16.16b}, v4.16b", "tbl v6.16b, {v17.16b}, v4.16b", diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json index 651d27609..b0eae85e7 100644 --- a/unittests/InstructionCountCI/DDD.json +++ b/unittests/InstructionCountCI/DDD.json @@ -10,7 +10,7 @@ "AFP", "RPRES" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers", diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json index c03b1edff..221af10ac 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json @@ -8,7 +8,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "Instructions that explicitly push against the limits of ARM's loadstore instructions" diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json index d20244ee5..0dbc9d85f 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json @@ -8,7 +8,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "Instructions that explicitly push against the limits of ARM's loadstore instructions" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json index 5c0bae65e..b036dc577 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json @@ -13,7 +13,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json index dd1c087c5..f2abbf4bc 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json @@ -11,7 +11,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json index 0f99e0ace..d81eac4b9 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json @@ -9,7 +9,7 @@ "SVE256", "RPRES" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json index 1122068a2..a7593917e 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json @@ -14,7 +14,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json index 443f4b34c..fe2aa5065 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json @@ -14,7 +14,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json index 25e4df1b0..9326ddad9 100644 --- a/unittests/InstructionCountCI/FEXOpt/libnss.json +++ b/unittests/InstructionCountCI/FEXOpt/libnss.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [], "Instructions": { diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index 2350cb821..de24102fa 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "lock add byte [rax], cl": { diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index 148e0b6f8..54fda4bf5 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Chained add": { diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json index cec93f983..55a55b857 100644 --- a/unittests/InstructionCountCI/FlagM/H0F38.json +++ b/unittests/InstructionCountCI/FlagM/H0F38.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "ptest xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index b2a0aa916..5716fcbcf 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "The Witcher 3": { @@ -892,7 +892,7 @@ "Comes from vcruntime140.dll wcsstr" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json index 0a06c034d..fa7163da4 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Sonic Mania movie player": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json index 07e159a1f..59db30174 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json @@ -10,7 +10,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "FMOD scalar loop": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json index fecca76a4..036c22b6f 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "The Sims 1 hot block": { diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index fb5eaa464..92d8b3f48 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "add bl, cl": { diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index da156a27c..c138d0842 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "add al, 1": { diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json index 403877ab4..5f9a3ebda 100644 --- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "push es": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index b939bbbbe..bf43f9411 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -11,7 +11,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "ucomiss xmm0, xmm1": { @@ -1610,7 +1610,7 @@ "mov w20, #0xffff", "strb w20, [x28, #1202]", "ldr d2, [x28, #1056]", - "ldr d3, [x28, #3424]", + "ldr d3, [x28, #3456]", "cmlt v2.16b, v2.16b, #0", "and v2.8b, v2.8b, v3.8b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index bc6a6abce..1dd751be6 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -11,7 +11,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "sgdt [rax]": { diff --git a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json index 9ce93edf2..eb71c8f5f 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json @@ -11,7 +11,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "xgetbv": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index c8989a1fb..e2b44707b 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -11,7 +11,7 @@ "AFP", "FCMA" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "ucomisd xmm0, xmm1": { @@ -38,7 +38,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3424]", + "ldr q2, [x28, #3456]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json index af0f2d0da..5477de73a 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json @@ -12,7 +12,7 @@ "AFP", "CSSC" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "popcnt ax, bx": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json index e3941dcee..87ce82d5e 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "popcnt ax, bx": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index 772d16ea7..e56f07d95 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vucomiss xmm0, xmm1": { @@ -69,7 +69,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3424]", + "ldr q2, [x28, #3456]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -84,7 +84,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2544]", + "ldr x0, [x28, #2552]", "ld1b {z2.b}, p7/z, [x0]", "mrs x0, nzcv", "mov z0.d, #0", diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json index 25eff605d..a5bb9edcb 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map2.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json @@ -10,7 +10,7 @@ "AFP", "SVEBITPERM" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vtestps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json index c3dcb16a3..6da6503de 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map_group.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "blsr eax, ebx": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json index 78ba9ba16..b50f0514a 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index 876b4fa3f..89b2d57b2 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Block1": { @@ -560,7 +560,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "bic v2.16b, v2.16b, v3.16b", "ldr s3, [x4]", "str x30, [sp, #-16]!", @@ -570,7 +570,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q4, [x28, #3712]", + "ldr q4, [x28, #3744]", "bic v3.16b, v3.16b, v4.16b", "mov w27, #0x0", "strb wzr, [x28, #1049]", @@ -604,7 +604,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "bic v2.16b, v2.16b, v3.16b", "ldr s3, [x4, #4]", "str x30, [sp, #-16]!", @@ -614,7 +614,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q5, [x28, #3712]", + "ldr q5, [x28, #3744]", "bic v3.16b, v3.16b, v5.16b", "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", @@ -647,7 +647,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "bic v2.16b, v2.16b, v3.16b", "ldr s3, [x4, #8]", "str x30, [sp, #-16]!", @@ -657,7 +657,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q6, [x28, #3712]", + "ldr q6, [x28, #3744]", "bic v3.16b, v3.16b, v6.16b", "strb wzr, [x28, #1049]", "str x30, [sp, #-16]!", diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 5d1771ef0..c724c49ea 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Block1": { @@ -3790,7 +3790,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3712]", + "ldr q9, [x28, #3744]", "eor v2.16b, v2.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -3840,7 +3840,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3712]", + "ldr q9, [x28, #3744]", "eor v2.16b, v2.16b, v9.16b", "ldr s9, [x8, #28]", "str x30, [sp, #-16]!", @@ -4003,7 +4003,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3712]", + "ldr q9, [x28, #3744]", "eor v2.16b, v2.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -4053,7 +4053,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3712]", + "ldr q9, [x28, #3744]", "eor v2.16b, v2.16b, v9.16b", "ldr s9, [x8, #60]", "str x30, [sp, #-16]!", @@ -4239,7 +4239,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #3712]", + "ldr q9, [x28, #3744]", "eor v2.16b, v2.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -4260,7 +4260,7 @@ "ldr x30, [sp], #16", "mov v9.16b, v0.16b", "str s2, [x8, #176]", - "ldr q2, [x28, #3712]", + "ldr q2, [x28, #3744]", "eor v2.16b, v9.16b, v2.16b", "ldr s9, [x8, #8]", "str x30, [sp, #-16]!", @@ -7531,7 +7531,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q10, [x28, #3712]", + "ldr q10, [x28, #3744]", "eor v8.16b, v8.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v8.16b", @@ -7622,7 +7622,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q11, [x28, #3712]", + "ldr q11, [x28, #3744]", "eor v8.16b, v8.16b, v11.16b", "str x30, [sp, #-16]!", "mov v0.16b, v8.16b", @@ -7680,7 +7680,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q11, [x28, #3712]", + "ldr q11, [x28, #3744]", "eor v8.16b, v8.16b, v11.16b", "str x30, [sp, #-16]!", "mov v0.16b, v8.16b", @@ -7953,7 +7953,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v7.16b, v0.16b", - "ldr q9, [x28, #3712]", + "ldr q9, [x28, #3744]", "eor v7.16b, v7.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v7.16b", @@ -8113,7 +8113,7 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #1024]", - "ldr q2, [x28, #3712]", + "ldr q2, [x28, #3744]", "eor v2.16b, v3.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8131,7 +8131,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8142,7 +8142,7 @@ "fmov s2, s0", "str s2, [x4, #1152]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3712]", + "ldr q2, [x28, #3744]", "eor v2.16b, v6.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8160,7 +8160,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8178,7 +8178,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8189,7 +8189,7 @@ "fmov s2, s0", "str s2, [x4, #1344]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3712]", + "ldr q2, [x28, #3744]", "eor v2.16b, v11.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8207,7 +8207,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "eor v2.16b, v2.16b, v3.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8218,7 +8218,7 @@ "fmov s2, s0", "str s2, [x4, #1472]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3712]", + "ldr q2, [x28, #3744]", "eor v2.16b, v10.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8229,7 +8229,7 @@ "fmov s2, s0", "str s2, [x4, #1536]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3712]", + "ldr q2, [x28, #3744]", "eor v2.16b, v9.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8240,7 +8240,7 @@ "fmov s2, s0", "str s2, [x4, #1600]", "strb wzr, [x28, #1049]", - "ldr q2, [x28, #3712]", + "ldr q2, [x28, #3744]", "eor v2.16b, v8.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -8250,7 +8250,7 @@ "ldr x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #1664]", - "ldr q2, [x28, #3712]", + "ldr q2, [x28, #3744]", "eor v2.16b, v7.16b, v2.16b", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -12539,7 +12539,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "eor v3.16b, v2.16b, v3.16b", "ldr s4, [x4]", "str x30, [sp, #-16]!", @@ -12581,7 +12581,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v4.16b, v0.16b", - "ldr q5, [x28, #3712]", + "ldr q5, [x28, #3744]", "eor v5.16b, v4.16b, v5.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12616,7 +12616,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3712]", + "ldr q6, [x28, #3744]", "eor v6.16b, v5.16b, v6.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12651,7 +12651,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q7, [x28, #3712]", + "ldr q7, [x28, #3744]", "eor v7.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12686,7 +12686,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v7.16b, v0.16b", - "ldr q8, [x28, #3712]", + "ldr q8, [x28, #3744]", "eor v8.16b, v7.16b, v8.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12721,7 +12721,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q9, [x28, #3712]", + "ldr q9, [x28, #3744]", "eor v9.16b, v8.16b, v9.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12756,7 +12756,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #3712]", + "ldr q10, [x28, #3744]", "eor v9.16b, v9.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12790,7 +12790,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #3712]", + "ldr q10, [x28, #3744]", "eor v9.16b, v9.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -12824,7 +12824,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #3712]", + "ldr q10, [x28, #3744]", "eor v9.16b, v9.16b, v10.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -20013,7 +20013,7 @@ "mov x8, x26", "str s2, [x8, #16]", "uxtb w7, w4", - "ldr q2, [x28, #3488]", + "ldr q2, [x28, #3520]", "str w7, [x8, #56]", "str x30, [sp, #-16]!", "mov v0.16b, v2.16b", @@ -21709,7 +21709,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "eor v2.16b, v2.16b, v3.16b", "add x14, x28, x20, lsl #4", "ldr q3, [x14, #1056]", @@ -21764,7 +21764,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q5, [x28, #3712]", + "ldr q5, [x28, #3744]", "eor v2.16b, v2.16b, v5.16b", "mov w14, #0x7b90", "movk w14, #0xa7, lsl #16", @@ -21828,7 +21828,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q6, [x28, #3712]", + "ldr q6, [x28, #3744]", "eor v2.16b, v2.16b, v6.16b", "mov w15, #0x7b80", "movk w15, #0xa7, lsl #16", @@ -21956,7 +21956,7 @@ "fmov s7, s0", "str s7, [x8, #64]", "strb wzr, [x28, #1049]", - "ldr q7, [x28, #3712]", + "ldr q7, [x28, #3744]", "eor v7.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v7.16b", @@ -21980,7 +21980,7 @@ "fmov s7, s0", "str s7, [x8, #68]", "strb wzr, [x28, #1049]", - "ldr q7, [x28, #3712]", + "ldr q7, [x28, #3744]", "eor v2.16b, v2.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", @@ -22006,7 +22006,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q5, [x28, #3712]", + "ldr q5, [x28, #3744]", "eor v5.16b, v2.16b, v5.16b", "ldr d7, [x15]", "str x30, [sp, #-16]!", diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index b95cef808..748675152 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Block1": { @@ -10859,7 +10859,7 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x23, x28, x22, lsl #4", - "ldr q4, [x28, #3712]", + "ldr q4, [x28, #3744]", "eor v3.16b, v3.16b, v4.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -10904,7 +10904,7 @@ "add w22, w22, #0x7 (7)", "and w22, w22, #0x7", "add x12, x28, x22, lsl #4", - "ldr q5, [x28, #3712]", + "ldr q5, [x28, #3744]", "eor v4.16b, v4.16b, v5.16b", "ldur s5, [x5, #-4]", "str x30, [sp, #-16]!", @@ -11029,7 +11029,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3712]", + "ldr q6, [x28, #3744]", "eor v5.16b, v5.16b, v6.16b", "ldr s6, [x5, #4]", "str x30, [sp, #-16]!", @@ -12175,7 +12175,7 @@ "ldr x30, [sp], #16", "mov v4.16b, v0.16b", "ldr w9, [x8, #48]", - "ldr q5, [x28, #3712]", + "ldr q5, [x28, #3744]", "eor v4.16b, v4.16b, v5.16b", "ldr s5, [x9, #12]", "str x30, [sp, #-16]!", @@ -12303,7 +12303,7 @@ "ldr x30, [sp], #16", "mov v5.16b, v0.16b", "ldr w9, [x8, #48]", - "ldr q6, [x28, #3712]", + "ldr q6, [x28, #3744]", "eor v5.16b, v5.16b, v6.16b", "ldr s6, [x9, #4]", "str x30, [sp, #-16]!", @@ -14022,7 +14022,7 @@ "add w22, w20, #0x7 (7)", "and w22, w22, #0x7", "add x23, x28, x22, lsl #4", - "ldr q4, [x28, #3712]", + "ldr q4, [x28, #3744]", "eor v3.16b, v3.16b, v4.16b", "str x30, [sp, #-16]!", "mov v0.16b, v3.16b", @@ -22327,7 +22327,7 @@ "add w22, w22, #0x7 (7)", "and w22, w22, #0x7", "add x13, x28, x22, lsl #4", - "ldr q6, [x28, #3712]", + "ldr q6, [x28, #3744]", "eor v5.16b, v5.16b, v6.16b", "add w14, w4, w10, lsl #2", "ldur s6, [x14, #-4]", @@ -22928,7 +22928,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3712]", + "ldr q6, [x28, #3744]", "eor v5.16b, v5.16b, v6.16b", "add w15, w4, w10, lsl #2", "ldr s6, [x15, #4]", @@ -23398,7 +23398,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q7, [x28, #3712]", + "ldr q7, [x28, #3744]", "eor v6.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", @@ -23486,7 +23486,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #3712]", + "ldr q6, [x28, #3744]", "eor v5.16b, v5.16b, v6.16b", "add w15, w4, w10, lsl #2", "ldr s6, [x15, #12]", @@ -25587,7 +25587,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q7, [x28, #3712]", + "ldr q7, [x28, #3744]", "eor v6.16b, v6.16b, v7.16b", "str x30, [sp, #-16]!", "mov v0.16b, v5.16b", diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 358ad5a3b..2b96554be 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -11,7 +11,7 @@ "CSSC", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "fadd dword [rax]": { @@ -2554,7 +2554,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "eor v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2568,7 +2568,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "bic v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2636,7 +2636,7 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3488]", + "ldr q2, [x28, #3520]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2656,7 +2656,7 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3504]", + "ldr q2, [x28, #3536]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2676,7 +2676,7 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3520]", + "ldr q2, [x28, #3552]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2696,7 +2696,7 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3536]", + "ldr q2, [x28, #3568]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2716,7 +2716,7 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3552]", + "ldr q2, [x28, #3584]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2736,7 +2736,7 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3568]", + "ldr q2, [x28, #3600]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2835,7 +2835,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3488]", + "ldr q3, [x28, #3520]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", "strb wzr, [x28, #1050]", diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json index 43701b564..22bdef82a 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json index 0130109b1..0a9e933d6 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json index df06dd497..9edb53fbf 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json index 4a62bc5f5..35282e161 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index f8eaae9c3..a305add9b 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "fadd dword [rax]": { @@ -2201,7 +2201,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3080]", + "ldr x0, [x28, #3088]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2224,7 +2224,7 @@ "ldr d3, [x23, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3104]", + "ldr x0, [x28, #3112]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2248,7 +2248,7 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3072]", + "ldr x0, [x28, #3080]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2284,7 +2284,7 @@ "ldr d3, [x22, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3096]", + "ldr x0, [x28, #3104]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2361,7 +2361,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3128]", + "ldr x0, [x28, #3136]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2411,7 +2411,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3120]", + "ldr x0, [x28, #3128]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2435,7 +2435,7 @@ "ldr d3, [x23, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3112]", + "ldr x0, [x28, #3120]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2472,13 +2472,13 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3056]", + "ldr x0, [x28, #3064]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", "fmov d3, d0", "fmov d0, d2", - "ldr x0, [x28, #3064]", + "ldr x0, [x28, #3072]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2525,7 +2525,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3088]", + "ldr x0, [x28, #3096]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2543,7 +2543,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3056]", + "ldr x0, [x28, #3064]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2562,7 +2562,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3064]", + "ldr x0, [x28, #3072]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index 64e6a7f42..91aa0f578 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -10,7 +10,7 @@ "FLAGM2", "CRYPTO" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "pshufb mm0, mm1": { @@ -674,7 +674,7 @@ "0x66 0x0f 0x38 0x41" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index e531fb873..2ebc33d9c 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -8,7 +8,7 @@ "AFP", "CRYPTO" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "SSE4.2 string instructions are skipped here.", @@ -328,7 +328,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3328]", + "ldr q2, [x28, #3360]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -338,7 +338,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3344]", + "ldr q2, [x28, #3376]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -357,7 +357,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3360]", + "ldr q2, [x28, #3392]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -377,7 +377,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3376]", + "ldr q2, [x28, #3408]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -396,7 +396,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3392]", + "ldr q2, [x28, #3424]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -406,7 +406,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3408]", + "ldr q2, [x28, #3440]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -475,7 +475,7 @@ "0x66 0x0f 0x3a 0x0e" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2776]", + "ldr x0, [x28, #2784]", "ldr q2, [x0, #3440]", "tbx v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/H0F3A_SVE128.json b/unittests/InstructionCountCI/H0F3A_SVE128.json index 37373f1b8..e2aca800a 100644 --- a/unittests/InstructionCountCI/H0F3A_SVE128.json +++ b/unittests/InstructionCountCI/H0F3A_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "dpps xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/MOPS/Primary.json b/unittests/InstructionCountCI/MOPS/Primary.json index 0782b9d01..77dd6e10d 100644 --- a/unittests/InstructionCountCI/MOPS/Primary.json +++ b/unittests/InstructionCountCI/MOPS/Primary.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "rep movsb": { diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index edaebfc90..eb61eba12 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -10,7 +10,7 @@ "FLAGM2", "MOPS" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "add bl, cl": { @@ -2473,7 +2473,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -2488,7 +2488,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, @@ -2503,7 +2503,7 @@ "str x20, [x28, #24]", "mov w0, #0x401", "str x0, [x28, #1496]", - "ldr x0, [x28, #2992]", + "ldr x0, [x28, #3000]", "br x0" ] }, diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index d2e11c39e..7cda259dc 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "Instructions in this table that are marked optimal don't have their flag calculation part of this assumption", @@ -2787,7 +2787,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #3040]", + "ldr x3, [x28, #3048]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -2838,7 +2838,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #3048]", + "ldr x3, [x28, #3056]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index 1f02a56be..6f11582a1 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -9,7 +9,7 @@ "FlagM", "FlagM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "push es": { diff --git a/unittests/InstructionCountCI/RPRES/DDD.json b/unittests/InstructionCountCI/RPRES/DDD.json index b05f8efad..5f3416e0e 100644 --- a/unittests/InstructionCountCI/RPRES/DDD.json +++ b/unittests/InstructionCountCI/RPRES/DDD.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "pfrcpv mm0, mm1": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary.json b/unittests/InstructionCountCI/RPRES/Secondary.json index db43adca7..5142a93b6 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary.json +++ b/unittests/InstructionCountCI/RPRES/Secondary.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "rsqrtps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json index 0cfbf6a68..6fe86c84e 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json +++ b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "rsqrtss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json index 44b04c1d2..15d4b0e48 100644 --- a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json +++ b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json @@ -8,7 +8,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vrsqrtps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Repeat.json b/unittests/InstructionCountCI/Repeat.json index 466c4e295..71decd76a 100644 --- a/unittests/InstructionCountCI/Repeat.json +++ b/unittests/InstructionCountCI/Repeat.json @@ -6,7 +6,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": {} } diff --git a/unittests/InstructionCountCI/SSE42_Strings.json b/unittests/InstructionCountCI/SSE42_Strings.json index d5483a1c1..aeb231e99 100644 --- a/unittests/InstructionCountCI/SSE42_Strings.json +++ b/unittests/InstructionCountCI/SSE42_Strings.json @@ -33,7 +33,7 @@ " - 1b: ECX = MSB", "[7] - Reserved" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": { @@ -43,7 +43,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -114,7 +114,7 @@ "dup v3.16b, v3.b[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -139,7 +139,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -186,7 +186,7 @@ "dup v3.8h, v3.h[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -212,7 +212,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -283,7 +283,7 @@ "dup v3.16b, v3.b[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -308,7 +308,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -355,7 +355,7 @@ "dup v3.8h, v3.h[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -381,7 +381,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -464,7 +464,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -489,7 +489,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -540,7 +540,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -566,7 +566,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -649,7 +649,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -674,7 +674,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -725,7 +725,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -751,7 +751,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -775,7 +775,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -800,7 +800,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -824,7 +824,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -850,7 +850,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -874,7 +874,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -899,7 +899,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -923,7 +923,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -949,7 +949,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -1070,7 +1070,7 @@ "dup v4.16b, w20", "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -1094,7 +1094,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -1167,7 +1167,7 @@ "dup v4.8h, w20", "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -1192,7 +1192,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -1313,7 +1313,7 @@ "dup v4.16b, w20", "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -1337,7 +1337,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -1410,7 +1410,7 @@ "dup v4.8h, w20", "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -1435,7 +1435,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -1507,7 +1507,7 @@ "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -1532,7 +1532,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -1580,7 +1580,7 @@ "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -1606,7 +1606,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -1678,7 +1678,7 @@ "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -1703,7 +1703,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -1751,7 +1751,7 @@ "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -1777,7 +1777,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -1861,7 +1861,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -1886,7 +1886,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -1938,7 +1938,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -1964,7 +1964,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2048,7 +2048,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -2073,7 +2073,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2125,7 +2125,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -2151,7 +2151,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2176,7 +2176,7 @@ "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -2201,7 +2201,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2226,7 +2226,7 @@ "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -2252,7 +2252,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2277,7 +2277,7 @@ "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -2302,7 +2302,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2327,7 +2327,7 @@ "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -2353,7 +2353,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2475,7 +2475,7 @@ "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -2499,7 +2499,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2573,7 +2573,7 @@ "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -2598,7 +2598,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2720,7 +2720,7 @@ "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -2744,7 +2744,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2818,7 +2818,7 @@ "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -2843,7 +2843,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2914,7 +2914,7 @@ "dup v3.16b, v3.b[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -2939,7 +2939,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -2986,7 +2986,7 @@ "dup v3.8h, v3.h[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -3012,7 +3012,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3083,7 +3083,7 @@ "dup v3.16b, v3.b[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -3108,7 +3108,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3155,7 +3155,7 @@ "dup v3.8h, v3.h[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -3181,7 +3181,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3264,7 +3264,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -3289,7 +3289,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3340,7 +3340,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -3366,7 +3366,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3449,7 +3449,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -3474,7 +3474,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3525,7 +3525,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -3551,7 +3551,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3575,7 +3575,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -3600,7 +3600,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3624,7 +3624,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -3650,7 +3650,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3674,7 +3674,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -3699,7 +3699,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3723,7 +3723,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -3749,7 +3749,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3870,7 +3870,7 @@ "dup v4.16b, w20", "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -3894,7 +3894,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -3967,7 +3967,7 @@ "dup v4.8h, w20", "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -3992,7 +3992,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4113,7 +4113,7 @@ "dup v4.16b, w20", "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -4137,7 +4137,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4210,7 +4210,7 @@ "dup v4.8h, w20", "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -4235,7 +4235,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4307,7 +4307,7 @@ "and v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -4332,7 +4332,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4380,7 +4380,7 @@ "and v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -4406,7 +4406,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4478,7 +4478,7 @@ "and v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -4503,7 +4503,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4551,7 +4551,7 @@ "and v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -4577,7 +4577,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4661,7 +4661,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -4686,7 +4686,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4738,7 +4738,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -4764,7 +4764,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4848,7 +4848,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -4873,7 +4873,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4925,7 +4925,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -4951,7 +4951,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -4976,7 +4976,7 @@ "and v4.16b, v4.16b, v5.16b", "orn v3.16b, v4.16b, v3.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -5001,7 +5001,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5026,7 +5026,7 @@ "and v4.16b, v4.16b, v5.16b", "orn v3.16b, v4.16b, v3.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -5052,7 +5052,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5077,7 +5077,7 @@ "and v4.16b, v4.16b, v5.16b", "orn v3.16b, v4.16b, v3.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -5102,7 +5102,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5127,7 +5127,7 @@ "and v4.16b, v4.16b, v5.16b", "orn v3.16b, v4.16b, v3.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -5153,7 +5153,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5277,7 +5277,7 @@ "cmgt v2.16b, v5.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", "eor v2.16b, v2.16b, v4.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -5301,7 +5301,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5377,7 +5377,7 @@ "cmgt v2.8h, v5.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", "eor v2.16b, v2.16b, v4.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -5402,7 +5402,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5526,7 +5526,7 @@ "cmgt v2.16b, v5.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", "eor v2.16b, v2.16b, v4.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -5550,7 +5550,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5626,7 +5626,7 @@ "cmgt v2.8h, v5.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", "eor v2.16b, v2.16b, v4.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -5651,7 +5651,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5743,7 +5743,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5811,7 +5811,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5903,7 +5903,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -5971,7 +5971,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6075,7 +6075,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6147,7 +6147,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6251,7 +6251,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6323,7 +6323,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6368,7 +6368,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6413,7 +6413,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6458,7 +6458,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6503,7 +6503,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6644,7 +6644,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6737,7 +6737,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6878,7 +6878,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -6971,7 +6971,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7064,7 +7064,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7133,7 +7133,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7226,7 +7226,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7295,7 +7295,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7400,7 +7400,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7473,7 +7473,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7578,7 +7578,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7651,7 +7651,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7697,7 +7697,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7743,7 +7743,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7789,7 +7789,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7835,7 +7835,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -7977,7 +7977,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8071,7 +8071,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8213,7 +8213,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8307,7 +8307,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8399,7 +8399,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8467,7 +8467,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8559,7 +8559,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8627,7 +8627,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8731,7 +8731,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8803,7 +8803,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8907,7 +8907,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -8979,7 +8979,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9024,7 +9024,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9069,7 +9069,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9114,7 +9114,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9159,7 +9159,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9300,7 +9300,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9393,7 +9393,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9534,7 +9534,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9627,7 +9627,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9720,7 +9720,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9789,7 +9789,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9882,7 +9882,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -9951,7 +9951,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10056,7 +10056,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10129,7 +10129,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10234,7 +10234,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10307,7 +10307,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10353,7 +10353,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10399,7 +10399,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10445,7 +10445,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10491,7 +10491,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10635,7 +10635,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10731,7 +10731,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10875,7 +10875,7 @@ "0x66 0x0f 0x3A 0x60" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -10971,7 +10971,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11065,7 +11065,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11135,7 +11135,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11229,7 +11229,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11299,7 +11299,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11405,7 +11405,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11479,7 +11479,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11585,7 +11585,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11659,7 +11659,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11706,7 +11706,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11753,7 +11753,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11800,7 +11800,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11847,7 +11847,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -11990,7 +11990,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -12085,7 +12085,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -12228,7 +12228,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -12323,7 +12323,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -12418,7 +12418,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -12489,7 +12489,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -12584,7 +12584,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -12655,7 +12655,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -12762,7 +12762,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -12837,7 +12837,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -12944,7 +12944,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13019,7 +13019,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13067,7 +13067,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13115,7 +13115,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13163,7 +13163,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13211,7 +13211,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13355,7 +13355,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13451,7 +13451,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13595,7 +13595,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13691,7 +13691,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13785,7 +13785,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13855,7 +13855,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -13949,7 +13949,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14019,7 +14019,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14125,7 +14125,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14199,7 +14199,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14305,7 +14305,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14379,7 +14379,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14426,7 +14426,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14473,7 +14473,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14520,7 +14520,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14567,7 +14567,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14710,7 +14710,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14805,7 +14805,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -14948,7 +14948,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15043,7 +15043,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15138,7 +15138,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15209,7 +15209,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15304,7 +15304,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15375,7 +15375,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15482,7 +15482,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15557,7 +15557,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15664,7 +15664,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15739,7 +15739,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15787,7 +15787,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15835,7 +15835,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15883,7 +15883,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -15931,7 +15931,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -16077,7 +16077,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -16175,7 +16175,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -16321,7 +16321,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -16419,7 +16419,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -16518,7 +16518,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -16593,7 +16593,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -16692,7 +16692,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -16767,7 +16767,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -16878,7 +16878,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -16957,7 +16957,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17068,7 +17068,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17147,7 +17147,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17199,7 +17199,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17251,7 +17251,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17303,7 +17303,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17355,7 +17355,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17503,7 +17503,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17603,7 +17603,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17751,7 +17751,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17851,7 +17851,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -17951,7 +17951,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18027,7 +18027,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18127,7 +18127,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18203,7 +18203,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18315,7 +18315,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18395,7 +18395,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18507,7 +18507,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18587,7 +18587,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18640,7 +18640,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18693,7 +18693,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18746,7 +18746,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18799,7 +18799,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -18948,7 +18948,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -19049,7 +19049,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -19198,7 +19198,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -19299,7 +19299,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -19398,7 +19398,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -19473,7 +19473,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -19572,7 +19572,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -19647,7 +19647,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -19758,7 +19758,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -19837,7 +19837,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -19948,7 +19948,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20027,7 +20027,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20079,7 +20079,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20131,7 +20131,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20183,7 +20183,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20235,7 +20235,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20383,7 +20383,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20483,7 +20483,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20631,7 +20631,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20731,7 +20731,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20831,7 +20831,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -20907,7 +20907,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21007,7 +21007,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21083,7 +21083,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21195,7 +21195,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21275,7 +21275,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21387,7 +21387,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21467,7 +21467,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21520,7 +21520,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21573,7 +21573,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21626,7 +21626,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21679,7 +21679,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21830,7 +21830,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -21933,7 +21933,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -22084,7 +22084,7 @@ "0x66 0x0f 0x3A 0x61" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "mov w27, #0x0", "cmp w4, #0x0 (0)", "cneg w20, w4, mi", @@ -22187,7 +22187,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -22257,7 +22257,7 @@ "dup v3.16b, v3.b[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -22283,7 +22283,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -22329,7 +22329,7 @@ "dup v3.8h, v3.h[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -22356,7 +22356,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -22426,7 +22426,7 @@ "dup v3.16b, v3.b[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -22452,7 +22452,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -22498,7 +22498,7 @@ "dup v3.8h, v3.h[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -22525,7 +22525,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -22607,7 +22607,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -22633,7 +22633,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -22683,7 +22683,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -22710,7 +22710,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -22792,7 +22792,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -22818,7 +22818,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -22868,7 +22868,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -22895,7 +22895,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -22918,7 +22918,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -22944,7 +22944,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -22967,7 +22967,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -22994,7 +22994,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -23017,7 +23017,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -23043,7 +23043,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -23066,7 +23066,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -23093,7 +23093,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -23215,7 +23215,7 @@ "dup v4.16b, w20", "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -23239,7 +23239,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -23313,7 +23313,7 @@ "dup v4.8h, w20", "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -23338,7 +23338,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -23460,7 +23460,7 @@ "dup v4.16b, w20", "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -23484,7 +23484,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -23558,7 +23558,7 @@ "dup v4.8h, w20", "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -23583,7 +23583,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -23654,7 +23654,7 @@ "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -23680,7 +23680,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -23727,7 +23727,7 @@ "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -23754,7 +23754,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -23825,7 +23825,7 @@ "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -23851,7 +23851,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -23898,7 +23898,7 @@ "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -23925,7 +23925,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -24008,7 +24008,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -24034,7 +24034,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -24085,7 +24085,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -24112,7 +24112,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -24195,7 +24195,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -24221,7 +24221,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -24272,7 +24272,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -24299,7 +24299,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -24323,7 +24323,7 @@ "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -24349,7 +24349,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -24373,7 +24373,7 @@ "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -24400,7 +24400,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -24424,7 +24424,7 @@ "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -24450,7 +24450,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -24474,7 +24474,7 @@ "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -24501,7 +24501,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -24624,7 +24624,7 @@ "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -24648,7 +24648,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -24723,7 +24723,7 @@ "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -24748,7 +24748,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -24871,7 +24871,7 @@ "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -24895,7 +24895,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -24970,7 +24970,7 @@ "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", "mvn v2.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -24995,7 +24995,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -25065,7 +25065,7 @@ "dup v3.16b, v3.b[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -25091,7 +25091,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -25137,7 +25137,7 @@ "dup v3.8h, v3.h[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -25164,7 +25164,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -25234,7 +25234,7 @@ "dup v3.16b, v3.b[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -25260,7 +25260,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -25306,7 +25306,7 @@ "dup v3.8h, v3.h[0]", "and v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -25333,7 +25333,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -25415,7 +25415,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -25441,7 +25441,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -25491,7 +25491,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -25518,7 +25518,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -25600,7 +25600,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -25626,7 +25626,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -25676,7 +25676,7 @@ "bic v3.16b, v3.16b, v6.16b", "orr v3.16b, v4.16b, v3.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -25703,7 +25703,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -25726,7 +25726,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -25752,7 +25752,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -25775,7 +25775,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -25802,7 +25802,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -25825,7 +25825,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -25851,7 +25851,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -25874,7 +25874,7 @@ "orr v2.16b, v3.16b, v2.16b", "and v3.16b, v4.16b, v5.16b", "orn v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -25901,7 +25901,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -26023,7 +26023,7 @@ "dup v4.16b, w20", "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -26047,7 +26047,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -26121,7 +26121,7 @@ "dup v4.8h, w20", "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -26146,7 +26146,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -26268,7 +26268,7 @@ "dup v4.16b, w20", "cmgt v2.16b, v4.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -26292,7 +26292,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -26366,7 +26366,7 @@ "dup v4.8h, w20", "cmgt v2.8h, v4.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -26391,7 +26391,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -26462,7 +26462,7 @@ "and v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -26488,7 +26488,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -26535,7 +26535,7 @@ "and v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -26562,7 +26562,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -26633,7 +26633,7 @@ "and v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -26659,7 +26659,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -26706,7 +26706,7 @@ "and v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -26733,7 +26733,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -26816,7 +26816,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -26842,7 +26842,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -26893,7 +26893,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -26920,7 +26920,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -27003,7 +27003,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -27029,7 +27029,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -27080,7 +27080,7 @@ "orr v3.16b, v4.16b, v3.16b", "and v3.16b, v3.16b, v2.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -27107,7 +27107,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -27131,7 +27131,7 @@ "and v4.16b, v4.16b, v5.16b", "orn v3.16b, v4.16b, v3.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -27157,7 +27157,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -27181,7 +27181,7 @@ "and v4.16b, v4.16b, v5.16b", "orn v3.16b, v4.16b, v3.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -27208,7 +27208,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -27232,7 +27232,7 @@ "and v4.16b, v4.16b, v5.16b", "orn v3.16b, v4.16b, v3.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -27258,7 +27258,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -27282,7 +27282,7 @@ "and v4.16b, v4.16b, v5.16b", "orn v3.16b, v4.16b, v3.16b", "eor v2.16b, v3.16b, v2.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -27309,7 +27309,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -27434,7 +27434,7 @@ "cmgt v2.16b, v5.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", "eor v2.16b, v2.16b, v4.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -27458,7 +27458,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -27535,7 +27535,7 @@ "cmgt v2.8h, v5.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", "eor v2.16b, v2.16b, v4.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -27560,7 +27560,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -27685,7 +27685,7 @@ "cmgt v2.16b, v5.16b, v2.16b", "and v2.16b, v3.16b, v2.16b", "eor v2.16b, v2.16b, v4.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v4.16b", @@ -27709,7 +27709,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -27786,7 +27786,7 @@ "cmgt v2.8h, v5.8h, v2.8h", "and v2.16b, v3.16b, v2.16b", "eor v2.16b, v2.16b, v4.16b", - "ldr q3, [x28, #3440]", + "ldr q3, [x28, #3456]", "movi v4.2d, #0x0", "uzp1 v2.16b, v2.16b, v4.16b", "and v2.16b, v2.16b, v3.16b", @@ -27811,7 +27811,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -27903,7 +27903,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -27971,7 +27971,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -28063,7 +28063,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -28131,7 +28131,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -28235,7 +28235,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -28307,7 +28307,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -28411,7 +28411,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -28483,7 +28483,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -28528,7 +28528,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -28573,7 +28573,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -28618,7 +28618,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -28663,7 +28663,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -28805,7 +28805,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -28899,7 +28899,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -29041,7 +29041,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -29135,7 +29135,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -29228,7 +29228,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -29297,7 +29297,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -29390,7 +29390,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -29459,7 +29459,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -29564,7 +29564,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -29637,7 +29637,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -29742,7 +29742,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -29815,7 +29815,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -29861,7 +29861,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -29907,7 +29907,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -29953,7 +29953,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -29999,7 +29999,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -30142,7 +30142,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -30237,7 +30237,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -30380,7 +30380,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -30475,7 +30475,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -30567,7 +30567,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -30635,7 +30635,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -30727,7 +30727,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -30795,7 +30795,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -30899,7 +30899,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -30971,7 +30971,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -31075,7 +31075,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -31147,7 +31147,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -31192,7 +31192,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -31237,7 +31237,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -31282,7 +31282,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -31327,7 +31327,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -31469,7 +31469,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -31563,7 +31563,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -31705,7 +31705,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -31799,7 +31799,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -31892,7 +31892,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -31961,7 +31961,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -32054,7 +32054,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -32123,7 +32123,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -32228,7 +32228,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -32301,7 +32301,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -32406,7 +32406,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -32479,7 +32479,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -32525,7 +32525,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -32571,7 +32571,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -32617,7 +32617,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -32663,7 +32663,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -32808,7 +32808,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -32905,7 +32905,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -33050,7 +33050,7 @@ "0x66 0x0f 0x3A 0x62" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -33147,7 +33147,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -33240,7 +33240,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -33309,7 +33309,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -33402,7 +33402,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -33471,7 +33471,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -33576,7 +33576,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -33649,7 +33649,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -33754,7 +33754,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -33827,7 +33827,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -33873,7 +33873,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -33919,7 +33919,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -33965,7 +33965,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -34011,7 +34011,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -34154,7 +34154,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -34249,7 +34249,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -34392,7 +34392,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -34487,7 +34487,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -34581,7 +34581,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -34651,7 +34651,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -34745,7 +34745,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -34815,7 +34815,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -34921,7 +34921,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -34995,7 +34995,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -35101,7 +35101,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -35175,7 +35175,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -35222,7 +35222,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -35269,7 +35269,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -35316,7 +35316,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -35363,7 +35363,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -35507,7 +35507,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -35603,7 +35603,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -35747,7 +35747,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -35843,7 +35843,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -35936,7 +35936,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -36005,7 +36005,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -36098,7 +36098,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -36167,7 +36167,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -36272,7 +36272,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -36345,7 +36345,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -36450,7 +36450,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -36523,7 +36523,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -36569,7 +36569,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -36615,7 +36615,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -36661,7 +36661,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -36707,7 +36707,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -36850,7 +36850,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -36945,7 +36945,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -37088,7 +37088,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -37183,7 +37183,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -37277,7 +37277,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -37347,7 +37347,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -37441,7 +37441,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -37511,7 +37511,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -37617,7 +37617,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -37691,7 +37691,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -37797,7 +37797,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -37871,7 +37871,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -37918,7 +37918,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -37965,7 +37965,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -38012,7 +38012,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -38059,7 +38059,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -38205,7 +38205,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -38303,7 +38303,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -38449,7 +38449,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -38547,7 +38547,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -38646,7 +38646,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -38721,7 +38721,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -38820,7 +38820,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -38895,7 +38895,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -39006,7 +39006,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -39085,7 +39085,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -39196,7 +39196,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -39275,7 +39275,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -39327,7 +39327,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -39379,7 +39379,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -39431,7 +39431,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -39483,7 +39483,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -39631,7 +39631,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -39731,7 +39731,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -39879,7 +39879,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -39979,7 +39979,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -40079,7 +40079,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -40155,7 +40155,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -40255,7 +40255,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -40331,7 +40331,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -40443,7 +40443,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -40523,7 +40523,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -40635,7 +40635,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -40715,7 +40715,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -40768,7 +40768,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -40821,7 +40821,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -40874,7 +40874,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -40927,7 +40927,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -41076,7 +41076,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -41177,7 +41177,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -41326,7 +41326,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -41427,7 +41427,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -41526,7 +41526,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -41601,7 +41601,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -41700,7 +41700,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -41775,7 +41775,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -41886,7 +41886,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -41965,7 +41965,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -42076,7 +42076,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -42155,7 +42155,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -42207,7 +42207,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -42259,7 +42259,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -42311,7 +42311,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -42363,7 +42363,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -42511,7 +42511,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -42611,7 +42611,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -42759,7 +42759,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -42859,7 +42859,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -42959,7 +42959,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -43035,7 +43035,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -43135,7 +43135,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -43211,7 +43211,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -43323,7 +43323,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -43403,7 +43403,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -43515,7 +43515,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -43595,7 +43595,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -43648,7 +43648,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -43701,7 +43701,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -43754,7 +43754,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -43807,7 +43807,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -43958,7 +43958,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", @@ -44061,7 +44061,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3184]", "cmeq v3.16b, v16.16b, #0", "movi v4.16b, #0x10", "bsl v3.16b, v2.16b, v4.16b", @@ -44212,7 +44212,7 @@ "0x66 0x0f 0x3A 0x63" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "cmeq v3.8h, v16.8h, #0", "movi v4.8h, #0x8", "bsl v3.16b, v2.16b, v4.16b", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 0a7bbc7eb..714f34ea6 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Comment": [ "MMX instructions are defined as optimal without SRA being used for these instructions.", @@ -652,7 +652,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #3296]", + "ldr q3, [x28, #3328]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -663,7 +663,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #3296]", + "ldr q3, [x28, #3328]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -3549,7 +3549,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q2, [x0, #16]", "tbl v16.16b, {v16.16b, v17.16b}, v2.16b" ] @@ -3558,7 +3558,7 @@ "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q2, [x0, #16]", "mov v0.16b, v17.16b", "mov v1.16b, v16.16b", @@ -3570,7 +3570,7 @@ "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q3, [x0, #16]", "mov v0.16b, v16.16b", "mov v1.16b, v2.16b", @@ -3698,7 +3698,7 @@ "mov w20, #0xffff", "strb w20, [x28, #1202]", "ldr d2, [x28, #1056]", - "ldr d3, [x28, #3424]", + "ldr d3, [x28, #3456]", "cmlt v2.16b, v2.16b, #0", "and v2.8b, v2.8b, v3.8b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index fc309f5b1..43d8743e7 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "sgdt [rax]": { diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json index 28e55023b..8b1933524 100644 --- a/unittests/InstructionCountCI/SecondaryModRM.json +++ b/unittests/InstructionCountCI/SecondaryModRM.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "xgetbv": { diff --git a/unittests/InstructionCountCI/Secondary_32Bit.json b/unittests/InstructionCountCI/Secondary_32Bit.json index b0bb48ff9..8e880d33a 100644 --- a/unittests/InstructionCountCI/Secondary_32Bit.json +++ b/unittests/InstructionCountCI/Secondary_32Bit.json @@ -7,7 +7,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "push fs": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index eb558551e..c2c2ee5f4 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "movupd xmm0, xmm0": { @@ -526,7 +526,7 @@ "0x66 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -540,7 +540,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q3, [x0, #16]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -678,7 +678,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q3, [x0, #2480]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -1260,7 +1260,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x66 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.2d, v16.2d, v2.2d" ] @@ -1316,7 +1316,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3424]", + "ldr q2, [x28, #3456]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json index c862d7780..11c11062c 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "addsubpd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json index 04f2cdb22..41bac85d5 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "psrlw xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json index 6f1f85ac0..f6d499553 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "pmulhuw xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index f445c174a..d04c53649 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -12,7 +12,7 @@ "FRINTTS", "CSSC" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "movss xmm0, xmm1": { @@ -119,7 +119,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, s16", "mov w21, #0x80000000", - "ldr s2, [x28, #3584]", + "ldr s2, [x28, #3616]", "mrs x22, nzcv", "fcmp s2, s16", "csel w4, w20, w21, gt", @@ -133,7 +133,7 @@ "ldr s2, [x6]", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3584]", + "ldr s3, [x28, #3616]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -146,7 +146,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, s16", "mov x21, #0x8000000000000000", - "ldr s2, [x28, #3616]", + "ldr s2, [x28, #3648]", "mrs x22, nzcv", "fcmp s2, s16", "csel x4, x20, x21, gt", @@ -160,7 +160,7 @@ "ldr s2, [x6]", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3616]", + "ldr s3, [x28, #3648]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -174,7 +174,7 @@ "frinti s2, s16", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3584]", + "ldr s3, [x28, #3616]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -189,7 +189,7 @@ "frinti s2, s2", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3584]", + "ldr s3, [x28, #3616]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -203,7 +203,7 @@ "frinti s2, s16", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3616]", + "ldr s3, [x28, #3648]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -218,7 +218,7 @@ "frinti s2, s2", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3616]", + "ldr s3, [x28, #3648]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -297,8 +297,8 @@ "ExpectedInstructionCount": 6, "Comment": "0xf3 0x0f 0x5b", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3680]", - "ldr q3, [x28, #3584]", + "ldr q2, [x28, #3712]", + "ldr q3, [x28, #3616]", "fcvtzs v4.4s, v17.4s", "fcmgt v3.4s, v3.4s, v17.4s", "mov v16.16b, v3.16b", @@ -398,7 +398,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #1280]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -411,7 +411,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 34a759464..748b0ed51 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -10,7 +10,7 @@ "FCMA", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "movsd xmm0, xmm1": { @@ -291,7 +291,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #1280]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -304,7 +304,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -500,7 +500,7 @@ "ExpectedInstructionCount": 3, "Comment": "0xf2 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.4s, v16.4s, v2.4s" ] diff --git a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json index 2245d7046..945b2c751 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "addsubps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json index fa5fc8810..690ad15ca 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json @@ -10,7 +10,7 @@ "FCMA", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "cvtpd2dq xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json index 9b1053283..bb3aade91 100644 --- a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json +++ b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "cvttss2si eax, xmm0": { diff --git a/unittests/InstructionCountCI/Secondary_SVE128.json b/unittests/InstructionCountCI/Secondary_SVE128.json index bbddfab18..5f9794fbc 100644 --- a/unittests/InstructionCountCI/Secondary_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "movmskps eax, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 98274b6cf..b70dbb926 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -13,7 +13,7 @@ "FLAGM2", "FRINTTS" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vmovups xmm0, xmm0": { @@ -927,7 +927,7 @@ "sqxtnb z2.b, z17.h", "uzp1 z2.b, z2.b, z2.b", "splice z2.b, p6, z2.b, z1.b", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -1022,7 +1022,7 @@ "sqxtunb z2.b, z17.h", "uzp1 z2.b, z2.b, z2.b", "splice z2.b, p6, z2.b, z1.b", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -1042,7 +1042,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1053,7 +1053,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1064,7 +1064,7 @@ "Map 1 0b01 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1100,7 +1100,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q3, [x0, #16]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1117,7 +1117,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q3, [x0, #32]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1134,7 +1134,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2744]", + "ldr x0, [x28, #2752]", "ldr q3, [x0, #48]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1173,7 +1173,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1184,7 +1184,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1195,7 +1195,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1233,7 +1233,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q3, [x0, #16]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1250,7 +1250,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q3, [x0, #32]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1267,7 +1267,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2736]", + "ldr x0, [x28, #2744]", "ldr q3, [x0, #48]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1306,7 +1306,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1317,7 +1317,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1328,7 +1328,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -1366,7 +1366,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #16]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1383,7 +1383,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #32]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -1400,7 +1400,7 @@ ], "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", - "ldr x0, [x28, #2728]", + "ldr x0, [x28, #2736]", "ldr q3, [x0, #48]", "tbl v2.16b, {v2.16b}, v3.16b", "tbl v3.16b, {v17.16b}, v3.16b", @@ -2526,7 +2526,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2537,7 +2537,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2548,7 +2548,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2603,7 +2603,7 @@ "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", "mov z3.q, z18.q[1]", - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q4, [x0, #16]", "tbl v5.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2621,7 +2621,7 @@ "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", "mov z3.q, z18.q[1]", - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q4, [x0, #32]", "tbl v5.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2639,7 +2639,7 @@ "ExpectedArm64ASM": [ "mov z2.q, z17.q[1]", "mov z3.q, z18.q[1]", - "ldr x0, [x28, #2752]", + "ldr x0, [x28, #2760]", "ldr q4, [x0, #48]", "tbl v5.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -3168,7 +3168,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, s16", "mov w21, #0x80000000", - "ldr s2, [x28, #3584]", + "ldr s2, [x28, #3616]", "mrs x22, nzcv", "fcmp s2, s16", "csel w4, w20, w21, gt", @@ -3183,7 +3183,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, s16", "mov x21, #0x8000000000000000", - "ldr s2, [x28, #3616]", + "ldr s2, [x28, #3648]", "mrs x22, nzcv", "fcmp s2, s16", "csel x4, x20, x21, gt", @@ -3198,7 +3198,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, d16", "mov w21, #0x80000000", - "ldr d2, [x28, #3632]", + "ldr d2, [x28, #3664]", "mrs x22, nzcv", "fcmp d2, d16", "csel w4, w20, w21, gt", @@ -3213,7 +3213,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, d16", "mov x21, #0x8000000000000000", - "ldr d2, [x28, #3664]", + "ldr d2, [x28, #3696]", "mrs x22, nzcv", "fcmp d2, d16", "csel x4, x20, x21, gt", @@ -3229,7 +3229,7 @@ "frinti s2, s16", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #3584]", + "ldr s3, [x28, #3616]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -3245,7 +3245,7 @@ "frinti s2, s16", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #3616]", + "ldr s3, [x28, #3648]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -3261,7 +3261,7 @@ "frinti d2, d16", "fcvtzs w20, d2", "mov w21, #0x80000000", - "ldr d3, [x28, #3632]", + "ldr d3, [x28, #3664]", "mrs x22, nzcv", "fcmp d3, d2", "csel w4, w20, w21, gt", @@ -3277,7 +3277,7 @@ "frinti d2, d16", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #3664]", + "ldr d3, [x28, #3696]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -3626,8 +3626,8 @@ ], "ExpectedArm64ASM": [ "frinti v2.4s, v17.4s", - "ldr q3, [x28, #3680]", - "ldr q4, [x28, #3584]", + "ldr q3, [x28, #3712]", + "ldr q4, [x28, #3616]", "fcvtzs v5.4s, v2.4s", "fcmgt v2.4s, v4.4s, v2.4s", "mov v16.16b, v2.16b", @@ -3641,9 +3641,9 @@ ], "ExpectedArm64ASM": [ "frinti z2.s, p7/m, z17.s", - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2680]", "ld1b {z3.b}, p7/z, [x0]", - "ldr x0, [x28, #2624]", + "ldr x0, [x28, #2632]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.s", "fcmgt p0.s, p7/z, z4.s, z2.s", @@ -3661,8 +3661,8 @@ "Map 1 0b10 0x5b 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3680]", - "ldr q3, [x28, #3584]", + "ldr q2, [x28, #3712]", + "ldr q3, [x28, #3616]", "fcvtzs v4.4s, v17.4s", "fcmgt v3.4s, v3.4s, v17.4s", "mov v16.16b, v3.16b", @@ -3675,9 +3675,9 @@ "Map 1 0b10 0x5b 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2680]", "ld1b {z2.b}, p7/z, [x0]", - "ldr x0, [x28, #2624]", + "ldr x0, [x28, #2632]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.s", "fcmgt p0.s, p7/z, z3.s, z17.s", @@ -4090,7 +4090,7 @@ "sqxtnb z2.h, z17.s", "uzp1 z2.h, z2.h, z2.h", "splice z2.h, p6, z2.h, z1.h", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -4214,7 +4214,7 @@ "uzp1 z2.d, z0.d, z0.d", "uzp2 z1.d, z0.d, z0.d", "splice z2.d, p6, z2.d, z1.d", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -4239,7 +4239,7 @@ "uzp1 z2.s, z0.s, z0.s", "uzp2 z1.s, z0.s, z0.s", "splice z2.d, p6, z2.d, z1.d", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -4264,7 +4264,7 @@ "uzp1 z2.d, z17.d, z18.d", "uzp2 z3.d, z17.d, z18.d", "fsub z2.d, z2.d, z3.d", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -4289,7 +4289,7 @@ "uzp1 z2.s, z17.s, z18.s", "uzp2 z3.s, z17.s, z18.s", "fsub z2.s, z2.s, z3.s", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -4356,7 +4356,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d" ] @@ -4367,7 +4367,7 @@ "Map 1 0b01 0xd0 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2432]", + "ldr x0, [x28, #2440]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "fadd z16.d, z17.d, z2.d" @@ -4379,7 +4379,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s" ] @@ -4390,7 +4390,7 @@ "Map 1 0b11 0xd0 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2416]", + "ldr x0, [x28, #2424]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "fadd z16.s, z17.s, z2.s" @@ -4514,7 +4514,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3424]", + "ldr q2, [x28, #3456]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -4529,7 +4529,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2544]", + "ldr x0, [x28, #2552]", "ld1b {z2.b}, p7/z, [x0]", "mrs x0, nzcv", "mov z0.d, #0", @@ -4903,8 +4903,8 @@ "Map 1 0b01 0xe6 128-bit" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #3680]", - "ldr q3, [x28, #3632]", + "ldr d2, [x28, #3712]", + "ldr q3, [x28, #3664]", "fcvtzs z4.s, p6/m, z17.d", "uzp1 z4.s, z4.s, z4.s", "mov v4.8b, v4.8b", @@ -4920,8 +4920,8 @@ "Map 1 0b01 0xe6 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3680]", - "ldr x0, [x28, #2648]", + "ldr q2, [x28, #3712]", + "ldr x0, [x28, #2656]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.d", "uzp1 z4.s, z4.s, z4.s", @@ -4964,8 +4964,8 @@ ], "ExpectedArm64ASM": [ "frinti v2.2d, v17.2d", - "ldr d3, [x28, #3680]", - "ldr q4, [x28, #3632]", + "ldr d3, [x28, #3712]", + "ldr q4, [x28, #3664]", "fcvtzs z5.s, p6/m, z2.d", "uzp1 z5.s, z5.s, z5.s", "mov v5.8b, v5.8b", @@ -4982,8 +4982,8 @@ ], "ExpectedArm64ASM": [ "frinti z2.d, p7/m, z17.d", - "ldr q3, [x28, #3680]", - "ldr x0, [x28, #2648]", + "ldr q3, [x28, #3712]", + "ldr x0, [x28, #2656]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.d", "uzp1 z5.s, z5.s, z5.s", diff --git a/unittests/InstructionCountCI/VEX_map1_FCMA.json b/unittests/InstructionCountCI/VEX_map1_FCMA.json index 98fe3805f..60ecca131 100644 --- a/unittests/InstructionCountCI/VEX_map1_FCMA.json +++ b/unittests/InstructionCountCI/VEX_map1_FCMA.json @@ -8,7 +8,7 @@ "FCMA" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vaddsubpd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json index b3a50ad55..542ef9d79 100644 --- a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json +++ b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json @@ -13,7 +13,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vcvttss2si eax, xmm0": { @@ -113,9 +113,9 @@ ], "ExpectedArm64ASM": [ "frinti z2.s, p7/m, z17.s", - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2680]", "ld1b {z3.b}, p7/z, [x0]", - "ldr x0, [x28, #2624]", + "ldr x0, [x28, #2632]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.s", "fcmgt p0.s, p7/z, z4.s, z2.s", @@ -143,9 +143,9 @@ "Map 1 0b10 0x5b 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2672]", + "ldr x0, [x28, #2680]", "ld1b {z2.b}, p7/z, [x0]", - "ldr x0, [x28, #2624]", + "ldr x0, [x28, #2632]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.s", "fcmgt p0.s, p7/z, z3.s, z17.s", @@ -174,8 +174,8 @@ "Map 1 0b01 0xe6 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3680]", - "ldr x0, [x28, #2648]", + "ldr q2, [x28, #3712]", + "ldr x0, [x28, #2656]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.d", "uzp1 z4.s, z4.s, z4.s", @@ -209,8 +209,8 @@ ], "ExpectedArm64ASM": [ "frinti z2.d, p7/m, z17.d", - "ldr q3, [x28, #3680]", - "ldr x0, [x28, #2648]", + "ldr q3, [x28, #3712]", + "ldr x0, [x28, #2656]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.d", "uzp1 z5.s, z5.s, z5.s", diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 1ff0f136c..573e984e7 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -13,7 +13,7 @@ "I8MM", "DOTPROD" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { @@ -64,7 +64,7 @@ "uzp2 z1.h, z0.h, z0.h", "uzp1 z2.h, z0.h, z0.h", "splice z2.d, p6, z2.d, z1.d", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -89,7 +89,7 @@ "uzp2 z1.s, z0.s, z0.s", "uzp1 z2.s, z0.s, z0.s", "splice z2.d, p6, z2.d, z1.d", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -114,7 +114,7 @@ "uzp1 z2.h, z17.h, z18.h", "uzp2 z3.h, z17.h, z18.h", "sqadd z2.h, z2.h, z3.h", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -173,7 +173,7 @@ "uzp1 z2.h, z17.h, z18.h", "uzp2 z3.h, z17.h, z18.h", "sub z2.h, z2.h, z3.h", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -198,7 +198,7 @@ "uzp1 z2.s, z17.s, z18.s", "uzp2 z3.s, z17.s, z18.s", "sub z2.s, z2.s, z3.s", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -223,7 +223,7 @@ "uzp1 z2.h, z17.h, z18.h", "uzp2 z3.h, z17.h, z18.h", "sqsub z2.h, z2.h, z3.h", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -917,7 +917,7 @@ "sqxtunb z2.h, z17.s", "uzp1 z2.h, z2.h, z2.h", "splice z2.h, p6, z2.h, z1.h", - "ldr x0, [x28, #2560]", + "ldr x0, [x28, #2568]", "ld1b {z3.b}, p7/z, [x0]", "tbl z16.b, {z2.b}, z3.b" ] @@ -1511,7 +1511,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3136]", + "ldr q2, [x28, #3152]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -3757,7 +3757,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.4s, v16.4s, v18.4s", "mov v16.16b, v2.16b" @@ -3769,7 +3769,7 @@ "Map 2 0b01 0x96 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2416]", + "ldr x0, [x28, #2424]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z17.d, z2.d", "mov z0.d, z2.d", @@ -3783,7 +3783,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.2d, v16.2d, v18.2d", "mov v16.16b, v2.16b" @@ -3795,7 +3795,7 @@ "Map 2 0b01 0x96 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2432]", + "ldr x0, [x28, #2440]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z17.d, z2.d", "mov z0.d, z2.d", @@ -3809,7 +3809,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3264]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.4s, v16.4s, v18.4s", "mov v16.16b, v2.16b" @@ -3821,7 +3821,7 @@ "Map 2 0b01 0x97 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2448]", + "ldr x0, [x28, #2456]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z17.d, z2.d", "mov z0.d, z2.d", @@ -3835,7 +3835,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3296]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.2d, v16.2d, v18.2d", "mov v16.16b, v2.16b" @@ -3847,7 +3847,7 @@ "Map 2 0b01 0x97 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2464]", + "ldr x0, [x28, #2472]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z17.d, z2.d", "mov z0.d, z2.d", @@ -4709,7 +4709,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.4s, v17.4s, v16.4s", "mov v16.16b, v2.16b" @@ -4721,7 +4721,7 @@ "Map 2 0b01 0xa6 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2416]", + "ldr x0, [x28, #2424]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "mov z0.d, z2.d", @@ -4735,7 +4735,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.2d, v17.2d, v16.2d", "mov v16.16b, v2.16b" @@ -4747,7 +4747,7 @@ "Map 2 0b01 0xa6 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2432]", + "ldr x0, [x28, #2440]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "mov z0.d, z2.d", @@ -4761,7 +4761,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3264]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.4s, v17.4s, v16.4s", "mov v16.16b, v2.16b" @@ -4773,7 +4773,7 @@ "Map 2 0b01 0xa7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2448]", + "ldr x0, [x28, #2456]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "mov z0.d, z2.d", @@ -4787,7 +4787,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3296]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.2d, v17.2d, v16.2d", "mov v16.16b, v2.16b" @@ -4799,7 +4799,7 @@ "Map 2 0b01 0xa7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2464]", + "ldr x0, [x28, #2472]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z18.d, z2.d", "mov z0.d, z2.d", @@ -4813,7 +4813,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3168]", + "ldr q2, [x28, #3200]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.4s, v17.4s, v18.4s", "mov v16.16b, v2.16b" @@ -4825,7 +4825,7 @@ "Map 2 0b01 0xb6 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2416]", + "ldr x0, [x28, #2424]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z16.d, z2.d", "mov z16.d, z2.d", @@ -4838,7 +4838,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3200]", + "ldr q2, [x28, #3232]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.2d, v17.2d, v18.2d", "mov v16.16b, v2.16b" @@ -4850,7 +4850,7 @@ "Map 2 0b01 0xb6 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2432]", + "ldr x0, [x28, #2440]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z16.d, z2.d", "mov z16.d, z2.d", @@ -4863,7 +4863,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3232]", + "ldr q2, [x28, #3264]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.4s, v17.4s, v18.4s", "mov v16.16b, v2.16b" @@ -4875,7 +4875,7 @@ "Map 2 0b01 0xb7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2448]", + "ldr x0, [x28, #2456]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z16.d, z2.d", "mov z16.d, z2.d", @@ -4888,7 +4888,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3264]", + "ldr q2, [x28, #3296]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.2d, v17.2d, v18.2d", "mov v16.16b, v2.16b" @@ -4900,7 +4900,7 @@ "Map 2 0b01 0xb7 256-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2464]", + "ldr x0, [x28, #2472]", "ld1b {z2.b}, p7/z, [x0]", "eor z2.d, z16.d, z2.d", "mov z16.d, z2.d", diff --git a/unittests/InstructionCountCI/VEX_map2_DOTPROD.json b/unittests/InstructionCountCI/VEX_map2_DOTPROD.json index 2e072ac0f..55cc06b15 100644 --- a/unittests/InstructionCountCI/VEX_map2_DOTPROD.json +++ b/unittests/InstructionCountCI/VEX_map2_DOTPROD.json @@ -13,7 +13,7 @@ "SVEBITPERM", "I8MM" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vpdpbusd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map2_I8MM.json b/unittests/InstructionCountCI/VEX_map2_I8MM.json index 700bd83b9..1270c3d92 100644 --- a/unittests/InstructionCountCI/VEX_map2_I8MM.json +++ b/unittests/InstructionCountCI/VEX_map2_I8MM.json @@ -12,7 +12,7 @@ "FLAGM2", "SVEBITPERM" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vpdpbusd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map2_svebitperm.json b/unittests/InstructionCountCI/VEX_map2_svebitperm.json index 4d7bf4b0d..b13bfc58a 100644 --- a/unittests/InstructionCountCI/VEX_map2_svebitperm.json +++ b/unittests/InstructionCountCI/VEX_map2_svebitperm.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "pext eax, ebx, ecx": { diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index d72052f00..54cbaf085 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -8,7 +8,7 @@ "DisabledHostFeatures": [ "AFP" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vpermq ymm0, ymm1, 1": { @@ -4199,7 +4199,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3312]", + "ldr q2, [x28, #3344]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", @@ -4212,7 +4212,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3312]", + "ldr q2, [x28, #3344]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "aese v16.16b, v3.16b", diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json index e5bde5d3f..1ac81d579 100644 --- a/unittests/InstructionCountCI/VEX_map_group.json +++ b/unittests/InstructionCountCI/VEX_map_group.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "vpsrlw xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json index 7c1f1e1df..721bc6a02 100644 --- a/unittests/InstructionCountCI/X87ldst-SVE.json +++ b/unittests/InstructionCountCI/X87ldst-SVE.json @@ -11,7 +11,7 @@ "FLAGM2", "RPRES" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "fstp tword [rax]": { diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 9b22a49f2..16221d3ab 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -10,7 +10,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "fadd dword [rax]": { @@ -2553,7 +2553,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "eor v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2567,7 +2567,7 @@ "ldrb w20, [x28, #1051]", "add x20, x28, x20, lsl #4", "ldr q2, [x20, #1056]", - "ldr q3, [x28, #3712]", + "ldr q3, [x28, #3744]", "bic v2.16b, v2.16b, v3.16b", "str q2, [x20, #1056]" ] @@ -2635,7 +2635,7 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3488]", + "ldr q2, [x28, #3520]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2655,7 +2655,7 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3504]", + "ldr q2, [x28, #3536]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2675,7 +2675,7 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3520]", + "ldr q2, [x28, #3552]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2695,7 +2695,7 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3536]", + "ldr q2, [x28, #3568]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2715,7 +2715,7 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3552]", + "ldr q2, [x28, #3584]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2735,7 +2735,7 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #3568]", + "ldr q2, [x28, #3600]", "ldrb w20, [x28, #1051]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", @@ -2834,7 +2834,7 @@ "blr x0", "ldr x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #3488]", + "ldr q3, [x28, #3520]", "add w20, w20, #0x7 (7)", "and w20, w20, #0x7", "strb wzr, [x28, #1050]", diff --git a/unittests/InstructionCountCI/x87_32Bit.json b/unittests/InstructionCountCI/x87_32Bit.json index 7ae0f2dcb..aac2473a9 100644 --- a/unittests/InstructionCountCI/x87_32Bit.json +++ b/unittests/InstructionCountCI/x87_32Bit.json @@ -10,7 +10,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "Multiple fld/fst": { diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index 2ae6c3327..1b4fb9fe1 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "fadd dword [rax]": { @@ -2219,7 +2219,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3080]", + "ldr x0, [x28, #3088]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2242,7 +2242,7 @@ "ldr d3, [x23, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3104]", + "ldr x0, [x28, #3112]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2266,7 +2266,7 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3072]", + "ldr x0, [x28, #3080]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2302,7 +2302,7 @@ "ldr d3, [x22, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3096]", + "ldr x0, [x28, #3104]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2379,7 +2379,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3128]", + "ldr x0, [x28, #3136]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2429,7 +2429,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3120]", + "ldr x0, [x28, #3128]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2453,7 +2453,7 @@ "ldr d3, [x23, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3112]", + "ldr x0, [x28, #3120]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2490,13 +2490,13 @@ "add x21, x28, x20, lsl #4", "ldr d2, [x21, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3056]", + "ldr x0, [x28, #3064]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", "fmov d3, d0", "fmov d0, d2", - "ldr x0, [x28, #3064]", + "ldr x0, [x28, #3072]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2543,7 +2543,7 @@ "ldr d3, [x20, #1056]", "fmov d0, d3", "fmov d1, d2", - "ldr x0, [x28, #3088]", + "ldr x0, [x28, #3096]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2561,7 +2561,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3056]", + "ldr x0, [x28, #3064]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", @@ -2580,7 +2580,7 @@ "add x20, x28, x20, lsl #4", "ldr d2, [x20, #1056]", "fmov d0, d2", - "ldr x0, [x28, #3064]", + "ldr x0, [x28, #3072]", "str x30, [sp, #-16]!", "blr x0", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/x87_f64_32Bit.json b/unittests/InstructionCountCI/x87_f64_32Bit.json index 70d4e205c..0d7c8290b 100644 --- a/unittests/InstructionCountCI/x87_f64_32Bit.json +++ b/unittests/InstructionCountCI/x87_f64_32Bit.json @@ -15,7 +15,7 @@ "SVE256", "CSSC" ], - "BinaryCacheVersion": 27 + "BinaryCacheVersion": 28 }, "Instructions": { "fstp dword [ebx*4+0x204a20]": {