From 0d7c086b69be3ecae358bf24e4a3345fe70f92a4 Mon Sep 17 00:00:00 2001
From: Ryan Houdek <Sonicadvance1@gmail.com>
Date: Sun, 18 Dec 2022 14:56:40 -0800
Subject: [PATCH] Arm64: Enables debug option for disassembling the JIT code

This is useful as a debug option and will be useful to have in upstream
while comparing output between current vixl emitter and the new emitter.

With this in place I can easily do binary comparisons to see where I
have mistakes in the new emitter.

We don't want this enabled in release builds as it is a debug feature.
This has already caught a bunch of mistakes, so make it easier by
upstreaming.
It'll likely be useful in the future as well when we are inspecting code
running in the vixl simulator.
---
 CMakeLists.txt                                           | 1 +
 External/FEXCore/Source/CMakeLists.txt                   | 4 ++++
 .../Source/Interface/Core/ArchHelpers/Arm64Emitter.h     | 7 ++++++-
 .../Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp | 8 ++++++++
 External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp | 9 +++++++++
 5 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 3c0007498..d90c8e2e6 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -29,6 +29,7 @@ option(ENABLE_INTERPRETER "Enables FEX's Interpreter" FALSE)
 option(ENABLE_CCACHE "Enables ccache for compile caching" TRUE)
 option(ENABLE_TERMUX_BUILD "Forces building for Termux on a non-Termux build machine" FALSE)
 option(ENABLE_VIXL_SIMULATOR "Forces the FEX JIT to use the VIXL simulator" FALSE)
+option(ENABLE_VIXL_DISASSEMBLER "Enables debug disassembler output with VIXL" FALSE)
 option(ENABLE_FEXCORE_PROFILER "Enables use of the FEXCore timeline profiling capabilities" FALSE)
 set (FEXCORE_PROFILER_BACKEND "gpuvis" CACHE STRING "Set which backend you want to use for the FEXCore profiler")
 
diff --git a/External/FEXCore/Source/CMakeLists.txt b/External/FEXCore/Source/CMakeLists.txt
index 122aac6ba..44dd2b45b 100644
--- a/External/FEXCore/Source/CMakeLists.txt
+++ b/External/FEXCore/Source/CMakeLists.txt
@@ -182,6 +182,10 @@ if (ENABLE_VIXL_SIMULATOR)
   list(APPEND DEFINES -DVIXL_SIMULATOR=1 -DVIXL_INCLUDE_SIMULATOR_AARCH64=1)
 endif()
 
+if (ENABLE_VIXL_DISASSEMBLER)
+  list(APPEND DEFINES -DVIXL_DISASSEMBLER=1)
+endif()
+
 if (ENABLE_JIT_X86_64)
   list(APPEND SRCS
     Interface/Core/JIT/x86_64/JIT.cpp
diff --git a/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h b/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
index 2e9ae4b34..2fe99cebc 100644
--- a/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
+++ b/External/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.h
@@ -8,6 +8,9 @@
 #include <aarch64/cpu-aarch64.h>
 #include <aarch64/operands-aarch64.h>
 #include <platform-vixl.h>
+#ifdef VIXL_DISASSEMBLER
+#include <aarch64/disasm-aarch64.h>
+#endif
 #ifdef VIXL_SIMULATOR
 #include <aarch64/simulator-aarch64.h>
 #include <aarch64/simulator-constants-aarch64.h>
@@ -172,7 +175,9 @@ protected:
   }
 
 #endif
-
+#ifdef VIXL_DISASSEMBLER
+  vixl::aarch64::PrintDisassembler Disasm {stderr};
+#endif
   FEX_CONFIG_OPT(StaticRegisterAllocation, SRA);
 };
 
diff --git a/External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp b/External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp
index 2be4a025f..2b220ed76 100644
--- a/External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp
+++ b/External/FEXCore/Source/Interface/Core/Dispatcher/Arm64Dispatcher.cpp
@@ -46,6 +46,10 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
   , Simulator {&Decoder}
 #endif
 {
+#ifdef VIXL_DISASSEMBLER
+  const auto DisasmBegin = GetCursorAddress<const Instruction*>();
+#endif
+
 #ifdef VIXL_SIMULATOR
   // Hardcode a 256-bit vector width if we are running in the simulator.
   Simulator.SetVectorLengthInBits(256);
@@ -538,6 +542,10 @@ Arm64Dispatcher::Arm64Dispatcher(FEXCore::Context::Context *ctx, const Dispatche
   if (CTX->Config.GlobalJITNaming()) {
     CTX->Symbols.RegisterJITSpace(reinterpret_cast<void*>(DispatchPtr), End - reinterpret_cast<uint64_t>(DispatchPtr));
   }
+#ifdef VIXL_DISASSEMBLER
+  const auto DisasmEnd = GetCursorAddress<const Instruction*>();
+  Disasm.DisassembleBuffer(DisasmBegin, DisasmEnd);
+#endif
 }
 
 #ifdef VIXL_SIMULATOR
diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
index 970ab187e..4ffcb0ad0 100644
--- a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
+++ b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JIT.cpp
@@ -664,6 +664,10 @@ void *Arm64JITCore::CompileCode(uint64_t Entry,
   this->RAData = RAData;
   this->DebugData = DebugData;
 
+#ifdef VIXL_DISASSEMBLER
+  const auto DisasmBegin = GetCursorAddress<const Instruction*>();
+#endif
+
   #ifndef NDEBUG
   LoadConstant(x0, Entry);
   #endif
@@ -770,6 +774,11 @@ void *Arm64JITCore::CompileCode(uint64_t Entry,
   auto CodeEnd = GetCursorAddress<uint8_t *>();
   CPU.EnsureIAndDCacheCoherency(GuestEntry, CodeEnd - GuestEntry);
 
+#ifdef VIXL_DISASSEMBLER
+  const auto DisasmEnd = GetCursorAddress<const Instruction*>();
+  Disasm.DisassembleBuffer(DisasmBegin, DisasmEnd);
+#endif
+
   if (DebugData) {
     DebugData->HostCodeSize = CodeEnd - GuestEntry;
     DebugData->Relocations = &Relocations;