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@@ -4407,9 +4407,13 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
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LOGMAN_THROW_A_FMT(OpSize == 8, "full");
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LOGMAN_THROW_A_FMT(Class == FPRClass, "MMX is floaty");
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// Partial store into bottom 64-bits, leave the upper bits unaffected.
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// XXX: We actually should set the upper bits to all-1s?
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StoreContextPartial(MM0Index + gpr - FEXCore::X86State::REG_MM_0, Src);
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if (MMXState != MMXState_MMX) {
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ChgStateX87_MMX();
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}
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uint8_t Index = MM0Index + gpr - FEXCore::X86State::REG_MM_0;
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StoreContext(Index, Src);
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RegCache.Partial |= (1ull << (uint64_t)Index);
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} else if (gpr >= FEXCore::X86State::REG_XMM_0) {
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const auto gprIndex = gpr - X86State::REG_XMM_0;
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const auto VectorSize = GetGuestVectorLength();
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