From 068599b1ecdd4ebbcd11607fa78b5d30bd633ef2 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Wed, 29 Nov 2023 14:18:30 -0400 Subject: [PATCH] OpcodeDispatcher: use size-appropriate alu in bt* saves zero-extending move for 32-bit ops. Signed-off-by: Alyssa Rosenzweig --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index e0e499b9e..94d46fa74 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -2780,21 +2780,21 @@ void OpDispatchBuilder::BTOp(OpcodeArgs) { case BTAction::BTClear: { OrderedNode *BitMask = _Lshl(IR::SizeToOpSize(LshrSize), _Constant(1), BitSelect); - Dest = _Andn(OpSize::i64Bit, Dest, BitMask); + Dest = _Andn(IR::SizeToOpSize(LshrSize), Dest, BitMask); StoreResult(GPRClass, Op, Dest, -1); break; } case BTAction::BTSet: { OrderedNode *BitMask = _Lshl(IR::SizeToOpSize(LshrSize), _Constant(1), BitSelect); - Dest = _Or(OpSize::i64Bit, Dest, BitMask); + Dest = _Or(IR::SizeToOpSize(LshrSize), Dest, BitMask); StoreResult(GPRClass, Op, Dest, -1); break; } case BTAction::BTComplement: { OrderedNode *BitMask = _Lshl(IR::SizeToOpSize(LshrSize), _Constant(1), BitSelect); - Dest = _Xor(OpSize::i64Bit, Dest, BitMask); + Dest = _Xor(IR::SizeToOpSize(LshrSize), Dest, BitMask); StoreResult(GPRClass, Op, Dest, -1); break; }