From 03e0ca9833bf55f2af0cc00900c5cdf0314c17ee Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Tue, 26 Nov 2024 08:38:44 -0500 Subject: [PATCH] InstCountCI: Update Signed-off-by: Alyssa Rosenzweig --- unittests/InstructionCountCI/Atomics.json | 144 ++--- .../InstructionCountCI/FlagM/HotBlocks.json | 4 +- .../FlagM/Primary_32Bit.json | 12 +- .../InstructionCountCI/FlagM/Secondary.json | 36 +- .../FlagM/SecondaryGroup.json | 72 +-- unittests/InstructionCountCI/Primary.json | 249 ++++---- .../InstructionCountCI/PrimaryGroup.json | 168 +++--- .../InstructionCountCI/Primary_32Bit.json | 18 +- unittests/InstructionCountCI/Secondary.json | 276 ++++----- .../InstructionCountCI/SecondaryGroup.json | 540 +++++++++--------- .../InstructionCountCI/Secondary_REP.json | 8 +- unittests/InstructionCountCI/x87.json | 372 ++++++------ 12 files changed, 970 insertions(+), 929 deletions(-) diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 894d7a9c9..d5642d9b6 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -99,13 +99,13 @@ "cset x22, hs", "cmn wzr, w26, lsl #24", "mrs x23, nzcv", - "orr w22, w23, w22, lsl #29", + "bfi w23, w22, #29, #1", "eor w21, w20, w21", "eor w20, w26, w20", "bic w20, w20, w21", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", - "msr nzcv, x20" + "bfi w23, w20, #28, #1", + "msr nzcv, x23" ] }, "lock adc word [rax], cx": { @@ -123,13 +123,13 @@ "cset x22, hs", "cmn wzr, w26, lsl #16", "mrs x23, nzcv", - "orr w22, w23, w22, lsl #29", + "bfi w23, w22, #29, #1", "eor w21, w20, w21", "eor w20, w26, w20", "bic w20, w20, w21", "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", - "msr nzcv, x20" + "bfi w23, w20, #28, #1", + "msr nzcv, x23" ] }, "lock adc dword [rax], ecx": { @@ -165,13 +165,13 @@ "cset x22, hs", "cmn wzr, w26, lsl #24", "mrs x23, nzcv", - "orr w22, w23, w22, lsl #29", + "bfi w23, w22, #29, #1", "eor w21, w20, w21", "eor w20, w26, w20", "and w20, w20, w21", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", - "msr nzcv, x20" + "bfi w23, w20, #28, #1", + "msr nzcv, x23" ] }, "lock sbb word [rax], cx": { @@ -191,13 +191,13 @@ "cset x22, hs", "cmn wzr, w26, lsl #16", "mrs x23, nzcv", - "orr w22, w23, w22, lsl #29", + "bfi w23, w22, #29, #1", "eor w21, w20, w21", "eor w20, w26, w20", "and w20, w20, w21", "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", - "msr nzcv, x20" + "bfi w23, w20, #28, #1", + "msr nzcv, x23" ] }, "lock sbb dword [rax], ecx": { @@ -700,13 +700,13 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w27, #0x1", + "bfi w21, w20, #29, #1", + "eor w20, w27, #0x1", "eor w22, w26, w27", - "bic w21, w22, w21", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20" + "bic w20, w22, w20", + "ubfx x20, x20, #7, #1", + "bfi w21, w20, #28, #1", + "msr nzcv, x21" ] }, "lock adc byte [rax], 0xFF": { @@ -724,13 +724,13 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0xff", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0xff", "eor w21, w26, w21", - "bic w21, w21, w22", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20" + "bic w20, w21, w20", + "ubfx x20, x20, #7, #1", + "bfi w22, w20, #28, #1", + "msr nzcv, x22" ] }, "lock adc word [rax], 0x100": { @@ -747,13 +747,13 @@ "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w27, #0x100", + "bfi w21, w20, #29, #1", + "eor w20, w27, #0x100", "eor w22, w26, w27", - "bic w21, w22, w21", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20" + "bic w20, w22, w20", + "ubfx x20, x20, #15, #1", + "bfi w21, w20, #28, #1", + "msr nzcv, x21" ] }, "lock adc word [rax], 0xFFFF": { @@ -771,13 +771,13 @@ "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0xffff", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0xffff", "eor w21, w26, w21", - "bic w21, w21, w22", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20" + "bic w20, w21, w20", + "ubfx x20, x20, #15, #1", + "bfi w22, w20, #28, #1", + "msr nzcv, x22" ] }, "lock adc dword [rax], 0x100": { @@ -859,13 +859,13 @@ "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w27, #0x1", + "bfi w21, w20, #29, #1", + "eor w20, w27, #0x1", "eor w22, w26, w27", - "bic w21, w22, w21", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20" + "bic w20, w22, w20", + "ubfx x20, x20, #15, #1", + "bfi w21, w20, #28, #1", + "msr nzcv, x21" ] }, "lock adc dword [rax], 1": { @@ -916,13 +916,13 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0x1", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0x1", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20" + "and w20, w21, w20", + "ubfx x20, x20, #7, #1", + "bfi w22, w20, #28, #1", + "msr nzcv, x22" ] }, "lock sbb byte [rax], 0xFF": { @@ -942,13 +942,13 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0xff", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0xff", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20" + "and w20, w21, w20", + "ubfx x20, x20, #7, #1", + "bfi w22, w20, #28, #1", + "msr nzcv, x22" ] }, "lock sbb word [rax], 0x100": { @@ -967,13 +967,13 @@ "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0x100", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0x100", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20" + "and w20, w21, w20", + "ubfx x20, x20, #15, #1", + "bfi w22, w20, #28, #1", + "msr nzcv, x22" ] }, "lock sbb word [rax], 0xFFFF": { @@ -993,13 +993,13 @@ "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0xffff", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0xffff", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20" + "and w20, w21, w20", + "ubfx x20, x20, #15, #1", + "bfi w22, w20, #28, #1", + "msr nzcv, x22" ] }, "lock sbb dword [rax], 0x100": { @@ -1063,13 +1063,13 @@ "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0x1", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0x1", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20" + "and w20, w21, w20", + "ubfx x20, x20, #15, #1", + "bfi w22, w20, #28, #1", + "msr nzcv, x22" ] }, "lock sbb dword [rax], 1": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index 0eaef8f8e..1ecf8eb9c 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -322,8 +322,8 @@ "mov w15, w10", "and w15, w15, #0x7", "lsr w20, w14, w15", - "eor x20, x20, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x20, #0, #1", + "cmp wzr, w20", "add x12, x12, x12, lsl #2", "add x20, x6, #0x10 (16)", "add x12, x20, x12, lsl #2", diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json index 0f9e77d14..813c15c33 100644 --- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json @@ -139,7 +139,7 @@ ] }, "aaa": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0x37", "ExpectedArm64ASM": [ "and x20, x4, #0xf", @@ -148,10 +148,8 @@ "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x21, x20", - "eor x21, x20, #0x1", - "lsl x21, x21, #29", + "cmp wzr, w20", "eor w27, w26, w20, lsl #4", - "msr nzcv, x21", "add w20, w4, #0x106 (262)", "csel w20, w20, w4, lo", "mov w21, #0xff0f", @@ -160,7 +158,7 @@ ] }, "aas": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0x3f", "ExpectedArm64ASM": [ "and x20, x4, #0xf", @@ -169,10 +167,8 @@ "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x21, x20", - "eor x21, x20, #0x1", - "lsl x21, x21, #29", + "cmp wzr, w20", "eor w27, w26, w20, lsl #4", - "msr nzcv, x21", "sub w20, w4, #0x106 (262)", "csel w20, w20, w4, lo", "mov w21, #0xff0f", diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 8330157d3..7ec21f5b9 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -561,8 +561,8 @@ "ExpectedArm64ASM": [ "and x20, x6, #0xf", "lsr w20, w4, w20", - "eor x20, x20, #0x1", - "rmif x20, #63, #nzCv" + "ubfx x20, x20, #0, #1", + "cmp wzr, w20" ] }, "bt [rax], bx": { @@ -582,8 +582,8 @@ "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "lsr w20, w4, w6", - "eor x20, x20, #0x1", - "rmif x20, #63, #nzCv" + "ubfx x20, x20, #0, #1", + "cmp wzr, w20" ] }, "bt [rax], ebx": { @@ -603,8 +603,8 @@ "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "lsr x20, x4, x6", - "eor x20, x20, #0x1", - "rmif x20, #63, #nzCv" + "ubfx x20, x20, #0, #1", + "cmp wzr, w20" ] }, "bt [rax], rbx": { @@ -855,8 +855,8 @@ "ExpectedArm64ASM": [ "and x20, x6, #0xf", "lsr w21, w4, w20", - "eor x21, x21, #0x1", - "rmif x21, #63, #nzCv", + "ubfx x21, x21, #0, #1", + "cmp wzr, w21", "mov w21, #0x1", "lsl w20, w21, w20", "orr w20, w4, w20", @@ -884,8 +884,8 @@ "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "lsr w20, w4, w6", - "eor x20, x20, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x20, #0, #1", + "cmp wzr, w20", "mov w20, #0x1", "lsl w20, w20, w6", "orr w4, w4, w20" @@ -912,8 +912,8 @@ "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "lsr x20, x4, x6", - "eor x20, x20, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x20, #0, #1", + "cmp wzr, w20", "mov w20, #0x1", "lsl x20, x20, x6", "orr x4, x4, x20" @@ -1180,8 +1180,8 @@ "ExpectedArm64ASM": [ "and x20, x6, #0xf", "lsr w21, w4, w20", - "eor x21, x21, #0x1", - "rmif x21, #63, #nzCv", + "ubfx x21, x21, #0, #1", + "cmp wzr, w21", "mov w21, #0x1", "lsl w20, w21, w20", "bic w20, w4, w20", @@ -1209,8 +1209,8 @@ "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "lsr w20, w4, w6", - "eor x20, x20, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x20, #0, #1", + "cmp wzr, w20", "mov w20, #0x1", "lsl w20, w20, w6", "bic w4, w4, w20" @@ -1237,8 +1237,8 @@ "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "lsr x20, x4, x6", - "eor x20, x20, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x20, #0, #1", + "cmp wzr, w20", "mov w20, #0x1", "lsl x20, x20, x6", "bic x4, x4, x20" diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index 8a31b5944..c6a1d1828 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -27,48 +27,48 @@ "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "rmif x20, #63, #nzCv" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20" ] }, "bt eax, 0": { "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "rmif x20, #63, #nzCv" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20" ] }, "bt rax, 0": { "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "rmif x20, #63, #nzCv" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20" ] }, "bt ax, 15": { "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000", - "rmif x20, #14, #nzCv" + "ubfx x20, x4, #15, #1", + "cmp wzr, w20" ] }, "bt eax, 31": { "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x80000000", - "rmif x20, #30, #nzCv" + "ubfx x20, x4, #31, #1", + "cmp wzr, w20" ] }, "bt rax, 63": { "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000000000000000", - "rmif x20, #62, #nzCv" + "lsr x20, x4, #63", + "cmp wzr, w20" ] }, "bt word [rax], 0": { @@ -132,8 +132,8 @@ "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", "orr w20, w4, #0x1", "bfxil x4, x20, #0, #16" ] @@ -142,8 +142,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", "orr w4, w4, #0x1" ] }, @@ -151,8 +151,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", "orr x4, x4, #0x1" ] }, @@ -160,8 +160,8 @@ "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000", - "rmif x20, #14, #nzCv", + "ubfx x20, x4, #15, #1", + "cmp wzr, w20", "orr w20, w4, #0x8000", "bfxil x4, x20, #0, #16" ] @@ -170,8 +170,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x80000000", - "rmif x20, #30, #nzCv", + "ubfx x20, x4, #31, #1", + "cmp wzr, w20", "orr w4, w4, #0x80000000" ] }, @@ -179,8 +179,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000000000000000", - "rmif x20, #62, #nzCv", + "lsr x20, x4, #63", + "cmp wzr, w20", "orr x4, x4, #0x8000000000000000" ] }, @@ -326,8 +326,8 @@ "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", "and w20, w4, #0xfffffffe", "bfxil x4, x20, #0, #16" ] @@ -336,8 +336,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", "and w4, w4, #0xfffffffe" ] }, @@ -345,8 +345,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "rmif x20, #63, #nzCv", + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", "and x4, x4, #0xfffffffffffffffe" ] }, @@ -354,8 +354,8 @@ "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000", - "rmif x20, #14, #nzCv", + "ubfx x20, x4, #15, #1", + "cmp wzr, w20", "and w20, w4, #0xffff7fff", "bfxil x4, x20, #0, #16" ] @@ -364,8 +364,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x80000000", - "rmif x20, #30, #nzCv", + "ubfx x20, x4, #31, #1", + "cmp wzr, w20", "and w4, w4, #0x7fffffff" ] }, @@ -373,8 +373,8 @@ "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000000000000000", - "rmif x20, #62, #nzCv", + "lsr x20, x4, #63", + "cmp wzr, w20", "and x4, x4, #0x7fffffffffffffff" ] }, diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 8d6bb8021..9d81d4ac5 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -447,14 +447,14 @@ "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w21, w22, w21, lsl #29", + "bfi w22, w21, #29, #1", "eor w20, w6, w20", - "eor w22, w26, w6", - "bic w20, w22, w20", + "eor w21, w26, w6", + "bic w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "bfi w22, w20, #28, #1", "bfxil x6, x26, #0, #8", - "msr nzcv, x20" + "msr nzcv, x22" ] }, "adc bx, cx": { @@ -470,14 +470,14 @@ "cset x21, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", - "orr w21, w22, w21, lsl #29", + "bfi w22, w21, #29, #1", "eor w20, w6, w20", - "eor w22, w26, w6", - "bic w20, w22, w20", + "eor w21, w26, w6", + "bic w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "bfi w22, w20, #28, #1", "bfxil x6, x26, #0, #16", - "msr nzcv, x20" + "msr nzcv, x22" ] }, "adc ebx, ecx": { @@ -526,14 +526,14 @@ "cset x21, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w21, w22, w21, lsl #29", + "bfi w22, w21, #29, #1", "eor w20, w7, w20", - "eor w22, w26, w7", - "bic w20, w22, w20", + "eor w21, w26, w7", + "bic w20, w21, w20", "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", + "bfi w22, w20, #28, #1", "bfxil x7, x26, #0, #8", - "msr nzcv, x20" + "msr nzcv, x22" ] }, "db 0x66, 0x13, 0xcb": { @@ -552,14 +552,14 @@ "cset x21, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", - "orr w21, w22, w21, lsl #29", + "bfi w22, w21, #29, #1", "eor w20, w7, w20", - "eor w22, w26, w7", - "bic w20, w22, w20", + "eor w21, w26, w7", + "bic w20, w21, w20", "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", + "bfi w22, w20, #28, #1", "bfxil x7, x26, #0, #16", - "msr nzcv, x20" + "msr nzcv, x22" ] }, "db 0x13, 0xcb": { @@ -610,17 +610,17 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w4, #0x1", + "bfi w21, w20, #29, #1", + "eor w20, w4, #0x1", "eor w22, w26, w4", - "bic w21, w22, w21", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", - "mov x21, x4", - "bfxil x21, x26, #0, #8", - "msr nzcv, x20", + "bic w20, w22, w20", + "ubfx x20, x20, #7, #1", + "bfi w21, w20, #28, #1", + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "msr nzcv, x21", "mov x27, x4", - "mov x4, x21" + "mov x4, x20" ] }, "adc ax, 1": { @@ -635,17 +635,17 @@ "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w4, #0x1", + "bfi w21, w20, #29, #1", + "eor w20, w4, #0x1", "eor w22, w26, w4", - "bic w21, w22, w21", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", - "mov x21, x4", - "bfxil x21, x26, #0, #16", - "msr nzcv, x20", + "bic w20, w22, w20", + "ubfx x20, x20, #15, #1", + "bfi w21, w20, #28, #1", + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "msr nzcv, x21", "mov x27, x4", - "mov x4, x21" + "mov x4, x20" ] }, "adc eax, 1": { @@ -693,14 +693,14 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w4, #0xff", + "bfi w21, w20, #29, #1", + "eor w20, w4, #0xff", "eor w22, w26, w4", - "bic w21, w22, w21", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "bic w20, w22, w20", + "ubfx x20, x20, #7, #1", + "bfi w21, w20, #28, #1", "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "msr nzcv, x21" ] }, "adc ax, -1": { @@ -716,14 +716,14 @@ "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w4, #0xffff", + "bfi w21, w20, #29, #1", + "eor w20, w4, #0xffff", "eor w22, w26, w4", - "bic w21, w22, w21", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", + "bic w20, w22, w20", + "ubfx x20, x20, #15, #1", + "bfi w21, w20, #28, #1", "bfxil x4, x26, #0, #16", - "msr nzcv, x20" + "msr nzcv, x21" ] }, "adc eax, -1": { @@ -772,14 +772,14 @@ "cset x22, hs", "cmn wzr, w26, lsl #24", "mrs x23, nzcv", - "orr w22, w23, w22, lsl #29", + "bfi w23, w22, #29, #1", "eor w21, w20, w21", "eor w20, w26, w20", "and w20, w20, w21", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "bfi w23, w20, #28, #1", "bfxil x6, x26, #0, #8", - "msr nzcv, x20" + "msr nzcv, x23" ] }, "sbb bx, cx": { @@ -796,14 +796,14 @@ "cset x22, hs", "cmn wzr, w26, lsl #16", "mrs x23, nzcv", - "orr w22, w23, w22, lsl #29", + "bfi w23, w22, #29, #1", "eor w21, w20, w21", "eor w20, w26, w20", "and w20, w20, w21", "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "bfi w23, w20, #28, #1", "bfxil x6, x26, #0, #16", - "msr nzcv, x20" + "msr nzcv, x23" ] }, "sbb ebx, ecx": { @@ -841,14 +841,14 @@ "cset x22, hs", "cmn wzr, w26, lsl #24", "mrs x23, nzcv", - "orr w22, w23, w22, lsl #29", + "bfi w23, w22, #29, #1", "eor w21, w20, w21", "eor w20, w26, w20", "and w20, w20, w21", "ubfx x20, x20, #7, #1", - "orr w20, w22, w20, lsl #28", + "bfi w23, w20, #28, #1", "bfxil x7, x26, #0, #8", - "msr nzcv, x20" + "msr nzcv, x23" ] }, "db 0x66, 0x1B, 0xcb": { @@ -868,14 +868,14 @@ "cset x22, hs", "cmn wzr, w26, lsl #16", "mrs x23, nzcv", - "orr w22, w23, w22, lsl #29", + "bfi w23, w22, #29, #1", "eor w21, w20, w21", "eor w20, w26, w20", "and w20, w20, w21", "ubfx x20, x20, #15, #1", - "orr w20, w22, w20, lsl #28", + "bfi w23, w20, #28, #1", "bfxil x7, x26, #0, #16", - "msr nzcv, x20" + "msr nzcv, x23" ] }, "db 0x1B, 0xcb": { @@ -915,17 +915,17 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0x1", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0x1", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", - "mov x21, x4", - "bfxil x21, x26, #0, #8", - "msr nzcv, x20", + "and w20, w21, w20", + "ubfx x20, x20, #7, #1", + "bfi w22, w20, #28, #1", + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "msr nzcv, x22", "mov x27, x4", - "mov x4, x21" + "mov x4, x20" ] }, "sbb ax, 1": { @@ -941,17 +941,17 @@ "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0x1", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0x1", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", - "mov x21, x4", - "bfxil x21, x26, #0, #16", - "msr nzcv, x20", + "and w20, w21, w20", + "ubfx x20, x20, #15, #1", + "bfi w22, w20, #28, #1", + "mov x20, x4", + "bfxil x20, x26, #0, #16", + "msr nzcv, x22", "mov x27, x4", - "mov x4, x21" + "mov x4, x20" ] }, "sbb eax, 1": { @@ -988,14 +988,14 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0xff", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0xff", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "and w20, w21, w20", + "ubfx x20, x20, #7, #1", + "bfi w22, w20, #28, #1", "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "msr nzcv, x22" ] }, "sbb ax, -1": { @@ -1012,14 +1012,14 @@ "cset x20, hs", "cmn wzr, w26, lsl #16", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0xffff", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0xffff", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", + "and w20, w21, w20", + "ubfx x20, x20, #15, #1", + "bfi w22, w20, #28, #1", "bfxil x4, x26, #0, #16", - "msr nzcv, x20" + "msr nzcv, x22" ] }, "sbb eax, -1": { @@ -2690,7 +2690,7 @@ ] }, "popf": { - "ExpectedInstructionCount": 38, + "ExpectedInstructionCount": 39, "Comment": "0x9d", "ExpectedArm64ASM": [ "ldr x20, [x8], #8", @@ -2698,39 +2698,40 @@ "orr x27, x20, x21", "mvn w20, w27", "ubfx x21, x20, #0, #1", - "lsl x21, x21, #29", + "mrs x22, nzcv", + "bfi w22, w21, #29, #1", "ubfx w26, w20, #2, #1", "ubfx x20, x27, #6, #1", - "orr w20, w21, w20, lsl #30", - "ubfx x21, x27, #7, #1", - "orr w20, w20, w21, lsl #31", - "ubfx w21, w27, #8, #1", - "strb w21, [x28, #984]", - "ubfx w21, w27, #9, #1", - "strb w21, [x28, #985]", - "ubfx w21, w27, #10, #1", - "mov w22, #0x1", - "sub x21, x22, x21, lsl #1", - "ubfx x22, x27, #11, #1", - "orr w20, w20, w22, lsl #28", - "ubfx w22, w27, #12, #1", - "strb w22, [x28, #988]", - "ubfx w22, w27, #14, #1", - "strb w22, [x28, #990]", - "ubfx w22, w27, #16, #1", - "strb w22, [x28, #992]", - "ubfx w22, w27, #17, #1", - "strb w22, [x28, #993]", - "ubfx w22, w27, #18, #1", - "strb w22, [x28, #994]", - "ubfx w22, w27, #19, #1", - "strb w22, [x28, #995]", - "ubfx w22, w27, #20, #1", - "strb w22, [x28, #996]", - "ubfx w22, w27, #21, #1", - "strb w22, [x28, #997]", - "msr nzcv, x20", - "strb w21, [x28, #986]" + "bfi w22, w20, #30, #1", + "ubfx x20, x27, #7, #1", + "bfi w22, w20, #31, #1", + "ubfx w20, w27, #8, #1", + "strb w20, [x28, #984]", + "ubfx w20, w27, #9, #1", + "strb w20, [x28, #985]", + "ubfx w20, w27, #10, #1", + "mov w21, #0x1", + "sub x20, x21, x20, lsl #1", + "ubfx x21, x27, #11, #1", + "bfi w22, w21, #28, #1", + "ubfx w21, w27, #12, #1", + "strb w21, [x28, #988]", + "ubfx w21, w27, #14, #1", + "strb w21, [x28, #990]", + "ubfx w21, w27, #16, #1", + "strb w21, [x28, #992]", + "ubfx w21, w27, #17, #1", + "strb w21, [x28, #993]", + "ubfx w21, w27, #18, #1", + "strb w21, [x28, #994]", + "ubfx w21, w27, #19, #1", + "strb w21, [x28, #995]", + "ubfx w21, w27, #20, #1", + "strb w21, [x28, #996]", + "ubfx w21, w27, #21, #1", + "strb w21, [x28, #997]", + "msr nzcv, x22", + "strb w20, [x28, #986]" ] }, "sahf": { diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 7bdaa431d..d2d75a8cd 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -56,17 +56,17 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w4, #0x1", + "bfi w21, w20, #29, #1", + "eor w20, w4, #0x1", "eor w22, w26, w4", - "bic w21, w22, w21", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", - "mov x21, x4", - "bfxil x21, x26, #0, #8", - "msr nzcv, x20", + "bic w20, w22, w20", + "ubfx x20, x20, #7, #1", + "bfi w21, w20, #28, #1", + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "msr nzcv, x21", "mov x27, x4", - "mov x4, x21" + "mov x4, x20" ] }, "sbb al, 1": { @@ -82,17 +82,17 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0x1", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0x1", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", - "mov x21, x4", - "bfxil x21, x26, #0, #8", - "msr nzcv, x20", + "and w20, w21, w20", + "ubfx x20, x20, #7, #1", + "bfi w22, w20, #28, #1", + "mov x20, x4", + "bfxil x20, x26, #0, #8", + "msr nzcv, x22", "mov x27, x4", - "mov x4, x21" + "mov x4, x20" ] }, "and al, 1": { @@ -184,14 +184,14 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w4, #0xff", + "bfi w21, w20, #29, #1", + "eor w20, w4, #0xff", "eor w22, w26, w4", - "bic w21, w22, w21", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "bic w20, w22, w20", + "ubfx x20, x20, #7, #1", + "bfi w21, w20, #28, #1", "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "msr nzcv, x21" ] }, "sbb al, -1": { @@ -208,14 +208,14 @@ "cset x20, hs", "cmn wzr, w26, lsl #24", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w22, w21, #0xff", + "bfi w22, w20, #29, #1", + "eor w20, w21, #0xff", "eor w21, w26, w21", - "and w21, w21, w22", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", + "and w20, w21, w20", + "ubfx x20, x20, #7, #1", + "bfi w22, w20, #28, #1", "bfxil x4, x26, #0, #8", - "msr nzcv, x20" + "msr nzcv, x22" ] }, "and al, -1": { @@ -1094,8 +1094,8 @@ "eor x20, x4, #0x40", "ubfx x20, x20, #6, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #8" ] }, @@ -1109,8 +1109,8 @@ "eor x20, x20, #0x2", "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #8" ] }, @@ -1124,8 +1124,8 @@ "eor x20, x20, #0x2", "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #8" ] }, @@ -1232,7 +1232,7 @@ ] }, "rcl eax, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "lsl w20, w4, #2", @@ -1240,13 +1240,14 @@ "orr w20, w20, w4, lsr #31", "eor x22, x4, #0x40000000", "ubfx x22, x22, #30, #1", - "lsl x22, x22, #29", + "mrs x23, nzcv", + "bfi w23, w22, #29, #1", "orr w4, w20, w21, lsl #1", - "msr nzcv, x22" + "msr nzcv, x23" ] }, "rcl rax, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /2", "ExpectedArm64ASM": [ "lsl x20, x4, #2", @@ -1254,9 +1255,10 @@ "orr x20, x20, x4, lsr #63", "eor x22, x4, #0x4000000000000000", "ubfx x22, x22, #62, #1", - "lsl x22, x22, #29", + "mrs x23, nzcv", + "bfi w23, w22, #29, #1", "orr x4, x20, x21, lsl #1", - "msr nzcv, x22" + "msr nzcv, x23" ] }, "rcr ax, 2": { @@ -1278,7 +1280,7 @@ ] }, "rcr eax, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "lsr w20, w4, #2", @@ -1286,13 +1288,14 @@ "orr w20, w20, w4, lsl #31", "eor x22, x4, #0x2", "ubfx x22, x22, #1, #1", - "lsl x22, x22, #29", + "mrs x23, nzcv", + "bfi w23, w22, #29, #1", "orr w4, w20, w21, lsl #30", - "msr nzcv, x22" + "msr nzcv, x23" ] }, "rcr rax, 2": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP2 0xC1 /3", "ExpectedArm64ASM": [ "lsr x20, x4, #2", @@ -1300,9 +1303,10 @@ "orr x20, x20, x4, lsl #63", "eor x22, x4, #0x2", "ubfx x22, x22, #1, #1", - "lsl x22, x22, #29", + "mrs x23, nzcv", + "bfi w23, w22, #29, #1", "orr x4, x20, x21, lsl #62", - "msr nzcv, x22" + "msr nzcv, x23" ] }, "shl ax, 2": { @@ -1314,8 +1318,8 @@ "eor x20, x4, #0x4000", "ubfx x20, x20, #14, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #16" ] }, @@ -1357,8 +1361,8 @@ "eor x20, x20, #0x2", "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #16" ] }, @@ -1400,8 +1404,8 @@ "eor x20, x20, #0x2", "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #16" ] }, @@ -1515,11 +1519,11 @@ "eor x20, x4, #0x80", "ubfx x20, x20, #7, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w26, w4", - "ubfx x21, x21, #7, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "eor w20, w26, w4", + "ubfx x20, x20, #7, #1", + "bfi w21, w20, #28, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #8" ] }, @@ -1533,10 +1537,10 @@ "eor x21, x20, #0x1", "ubfx x21, x21, #0, #1", "mrs x22, nzcv", - "orr w21, w22, w21, lsl #29", + "bfi w22, w21, #29, #1", "ubfx x20, x20, #7, #1", - "orr w20, w21, w20, lsl #28", - "msr nzcv, x20", + "bfi w22, w20, #28, #1", + "msr nzcv, x22", "bfxil x4, x26, #0, #8" ] }, @@ -1550,8 +1554,8 @@ "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #8" ] }, @@ -1762,11 +1766,11 @@ "eor x20, x4, #0x8000", "ubfx x20, x20, #15, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "eor w21, w26, w4", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "eor w20, w26, w4", + "ubfx x20, x20, #15, #1", + "bfi w21, w20, #28, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #16" ] }, @@ -1782,8 +1786,8 @@ "bfi w21, w20, #29, #1", "eor w20, w26, w4", "ubfx x20, x20, #31, #1", - "orr w20, w21, w20, lsl #28", - "msr nzcv, x20", + "bfi w21, w20, #28, #1", + "msr nzcv, x21", "mov x4, x26" ] }, @@ -1799,8 +1803,8 @@ "bfi w21, w20, #29, #1", "eor x20, x26, x4", "lsr x20, x20, #63", - "orr w20, w21, w20, lsl #28", - "msr nzcv, x20", + "bfi w21, w20, #28, #1", + "msr nzcv, x21", "mov x4, x26" ] }, @@ -1814,10 +1818,10 @@ "eor x21, x20, #0x1", "ubfx x21, x21, #0, #1", "mrs x22, nzcv", - "orr w21, w22, w21, lsl #29", + "bfi w22, w21, #29, #1", "ubfx x20, x20, #15, #1", - "orr w20, w21, w20, lsl #28", - "msr nzcv, x20", + "bfi w22, w20, #28, #1", + "msr nzcv, x22", "bfxil x4, x26, #0, #16" ] }, @@ -1832,8 +1836,8 @@ "mrs x21, nzcv", "bfi w21, w20, #29, #1", "ubfx x20, x4, #31, #1", - "orr w20, w21, w20, lsl #28", - "msr nzcv, x20", + "bfi w21, w20, #28, #1", + "msr nzcv, x21", "mov x4, x26" ] }, @@ -1848,8 +1852,8 @@ "mrs x21, nzcv", "bfi w21, w20, #29, #1", "lsr x20, x4, #63", - "orr w20, w21, w20, lsl #28", - "msr nzcv, x20", + "bfi w21, w20, #28, #1", + "msr nzcv, x21", "mov x4, x26" ] }, @@ -1863,8 +1867,8 @@ "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #16" ] }, diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index bae7f6611..e13efb425 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -103,7 +103,7 @@ "bfxil w4, w26, #0, #8", "cmn wzr, w26, lsl #24", "mrs x20, nzcv", - "orr w20, w20, w21, lsl #29", + "bfi w20, w21, #29, #1", "eor w27, w26, w22, lsl #4", "msr nzcv, x20" ] @@ -136,13 +136,13 @@ "cmn wzr, w26, lsl #24", "eor x20, x23, #0x1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", + "bfi w21, w20, #29, #1", "eor w27, w26, w22, lsl #4", - "msr nzcv, x20" + "msr nzcv, x21" ] }, "aaa": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0x37", "ExpectedArm64ASM": [ "and x20, x4, #0xf", @@ -151,10 +151,8 @@ "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x21, x20", - "eor x21, x20, #0x1", - "lsl x21, x21, #29", + "cmp wzr, w20", "eor w27, w26, w20, lsl #4", - "msr nzcv, x21", "add w20, w4, #0x106 (262)", "csel w20, w20, w4, lo", "mov w21, #0xff0f", @@ -163,7 +161,7 @@ ] }, "aas": { - "ExpectedInstructionCount": 15, + "ExpectedInstructionCount": 13, "Comment": "0x3f", "ExpectedArm64ASM": [ "and x20, x4, #0xf", @@ -172,10 +170,8 @@ "eor w21, w27, w26", "ubfx w21, w21, #4, #1", "orr x20, x21, x20", - "eor x21, x20, #0x1", - "lsl x21, x21, #29", + "cmp wzr, w20", "eor w27, w26, w20, lsl #4", - "msr nzcv, x21", "sub w20, w4, #0x106 (262)", "csel w20, w20, w4, lo", "mov w21, #0xff0f", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index 37d45c9fb..e3b85a382 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -1373,19 +1373,17 @@ ] }, "bt ax, bx": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "and x20, x6, #0xf", "lsr w20, w4, w20", - "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "cmp wzr, w20" ] }, "bt [rax], bx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -1394,23 +1392,22 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bt eax, ebx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "lsr w20, w4, w6", - "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "cmp wzr, w20" ] }, "bt [rax], ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -1419,23 +1416,22 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bt rax, rbx": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "lsr x20, x4, x6", - "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "cmp wzr, w20" ] }, "bt [rax], rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "0x0f 0xa3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -1444,8 +1440,9 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "shld ax, bx, 0": { @@ -1466,11 +1463,11 @@ "eor x20, x21, #0x8000", "ubfx x20, x20, #15, #1", "mrs x22, nzcv", - "orr w20, w22, w20, lsl #29", - "eor w21, w26, w21", - "ubfx x21, x21, #15, #1", - "orr w20, w20, w21, lsl #28", - "msr nzcv, x20", + "bfi w22, w20, #29, #1", + "eor w20, w26, w21", + "ubfx x20, x20, #15, #1", + "bfi w22, w20, #28, #1", + "msr nzcv, x22", "bfxil x4, x26, #0, #16" ] }, @@ -1487,8 +1484,8 @@ "eor x20, x21, #0x2", "ubfx x20, x20, #1, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20", + "bfi w21, w20, #29, #1", + "msr nzcv, x21", "bfxil x4, x26, #0, #16" ] }, @@ -1542,8 +1539,8 @@ "bfi w21, w20, #29, #1", "eor w20, w26, w4", "ubfx x20, x20, #31, #1", - "orr w20, w21, w20, lsl #28", - "msr nzcv, x20", + "bfi w21, w20, #28, #1", + "msr nzcv, x21", "mov x4, x26" ] }, @@ -1606,8 +1603,8 @@ "bfi w21, w20, #29, #1", "eor x20, x26, x4", "lsr x20, x20, #63", - "orr w20, w21, w20, lsl #28", - "msr nzcv, x20", + "bfi w21, w20, #28, #1", + "msr nzcv, x21", "mov x4, x26" ] }, @@ -1763,23 +1760,21 @@ ] }, "bts ax, bx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "and x20, x6, #0xf", "lsr w21, w4, w20", - "eor x21, x21, #0x1", "ubfx x21, x21, #0, #1", - "lsl x21, x21, #29", - "mov w22, #0x1", - "lsl w20, w22, w20", + "cmp wzr, w21", + "mov w21, #0x1", + "lsl w20, w21, w20", "orr w20, w4, w20", - "bfxil x4, x20, #0, #16", - "msr nzcv, x21" + "bfxil x4, x20, #0, #16" ] }, "bts [rax], bx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -1792,26 +1787,25 @@ "lsr w20, w23, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bts eax, ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "lsr w20, w4, w6", - "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "mov w21, #0x1", - "lsl w21, w21, w6", - "orr w4, w4, w21", - "msr nzcv, x20" + "cmp wzr, w20", + "mov w20, #0x1", + "lsl w20, w20, w6", + "orr w4, w4, w20" ] }, "bts [rax], ebx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -1824,26 +1818,25 @@ "lsr w20, w23, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bts rax, rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "lsr x20, x4, x6", - "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "mov w21, #0x1", - "lsl x21, x21, x6", - "orr x4, x4, x21", - "msr nzcv, x20" + "cmp wzr, w20", + "mov w20, #0x1", + "lsl x20, x20, x6", + "orr x4, x4, x20" ] }, "bts [rax], rbx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xab", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -1856,12 +1849,13 @@ "lsr w20, w23, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock bts [rax], bx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -1873,12 +1867,13 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock bts [rax], ebx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -1890,12 +1885,13 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock bts [rax], rbx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -1907,8 +1903,9 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "imul ax, bx": { @@ -2048,23 +2045,21 @@ ] }, "btr ax, bx": { - "ExpectedInstructionCount": 10, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "and x20, x6, #0xf", "lsr w21, w4, w20", - "eor x21, x21, #0x1", "ubfx x21, x21, #0, #1", - "lsl x21, x21, #29", - "mov w22, #0x1", - "lsl w20, w22, w20", + "cmp wzr, w21", + "mov w21, #0x1", + "lsl w20, w21, w20", "bic w20, w4, w20", - "bfxil x4, x20, #0, #16", - "msr nzcv, x21" + "bfxil x4, x20, #0, #16" ] }, "btr [rax], bx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2077,26 +2072,25 @@ "lsr w20, w23, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btr eax, ebx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "lsr w20, w4, w6", - "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "mov w21, #0x1", - "lsl w21, w21, w6", - "bic w4, w4, w21", - "msr nzcv, x20" + "cmp wzr, w20", + "mov w20, #0x1", + "lsl w20, w20, w6", + "bic w4, w4, w20" ] }, "btr [rax], ebx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2109,26 +2103,25 @@ "lsr w20, w23, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btr rax, rbx": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "lsr x20, x4, x6", - "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "mov w21, #0x1", - "lsl x21, x21, x6", - "bic x4, x4, x21", - "msr nzcv, x20" + "cmp wzr, w20", + "mov w20, #0x1", + "lsl x20, x20, x6", + "bic x4, x4, x20" ] }, "btr [rax], rbx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2141,8 +2134,9 @@ "lsr w20, w23, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "movzx ax, bl": { @@ -2154,7 +2148,7 @@ ] }, "lock btr [rax], bx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2166,12 +2160,13 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btr [rax], ebx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2183,12 +2178,13 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btr [rax], rbx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2200,8 +2196,9 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "movzx ax, byte [rax]": { @@ -2269,7 +2266,7 @@ ] }, "btc ax, bx": { - "ExpectedInstructionCount": 9, + "ExpectedInstructionCount": 8, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "and x20, x6, #0xf", @@ -2278,13 +2275,12 @@ "eor w21, w4, w21", "lsr w20, w21, w20", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "bfxil x4, x21, #0, #16", - "msr nzcv, x20" + "cmp w20, #0x1 (1)", + "bfxil x4, x21, #0, #16" ] }, "btc [rax], bx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2297,12 +2293,13 @@ "lsr w20, w23, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btc eax, ebx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -2310,12 +2307,11 @@ "eor w4, w4, w20", "lsr w20, w4, w6", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "cmp w20, #0x1 (1)" ] }, "btc [rax], ebx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2328,12 +2324,13 @@ "lsr w20, w23, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btc rax, rbx": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 6, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -2341,12 +2338,11 @@ "eor x4, x4, x20", "lsr x20, x4, x6", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "cmp w20, #0x1 (1)" ] }, "btc [rax], rbx": { - "ExpectedInstructionCount": 12, + "ExpectedInstructionCount": 13, "Comment": "0x0f 0xbb", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2359,12 +2355,13 @@ "lsr w20, w23, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btc [rax], bx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2376,12 +2373,13 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btc [rax], ebx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2393,12 +2391,13 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btc [rax], rbx": { - "ExpectedInstructionCount": 11, + "ExpectedInstructionCount": 12, "Comment": "0x0f 0xb3", "ExpectedArm64ASM": [ "ubfx x20, x6, #0, #3", @@ -2410,8 +2409,9 @@ "lsr w20, w21, w20", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bsf ax, bx": { diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index 7e5f0bc23..2f1848d05 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -24,204 +24,186 @@ ] }, "bt ax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20" ] }, "bt eax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20" ] }, "bt rax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20" ] }, "bt ax, 15": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000", - "ubfx x20, x20, #15, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "ubfx x20, x4, #15, #1", + "cmp wzr, w20" ] }, "bt eax, 31": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x80000000", - "ubfx x20, x20, #31, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "ubfx x20, x4, #31, #1", + "cmp wzr, w20" ] }, "bt rax, 63": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 2, "Comment": "GROUP8 0x0F 0xBA /4", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000000000000000", - "lsr x20, x20, #63", - "lsl x20, x20, #29", - "msr nzcv, x20" + "lsr x20, x4, #63", + "cmp wzr, w20" ] }, "bt word [rax], 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bt dword [rax], 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bt qword [rax], 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 6, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bt word [rax], 15": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bt dword [rax], 31": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bt qword [rax], 63": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 7, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bts ax, 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "orr w21, w4, #0x1", - "bfxil x4, x21, #0, #16", - "msr nzcv, x20" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", + "orr w20, w4, #0x1", + "bfxil x4, x20, #0, #16" ] }, "bts eax, 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "orr w4, w4, #0x1", - "msr nzcv, x20" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", + "orr w4, w4, #0x1" ] }, "bts rax, 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "orr x4, x4, #0x1", - "msr nzcv, x20" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", + "orr x4, x4, #0x1" ] }, "bts ax, 15": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000", - "ubfx x20, x20, #15, #1", - "lsl x20, x20, #29", - "orr w21, w4, #0x8000", - "bfxil x4, x21, #0, #16", - "msr nzcv, x20" + "ubfx x20, x4, #15, #1", + "cmp wzr, w20", + "orr w20, w4, #0x8000", + "bfxil x4, x20, #0, #16" ] }, "bts eax, 31": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x80000000", - "ubfx x20, x20, #31, #1", - "lsl x20, x20, #29", - "orr w4, w4, #0x80000000", - "msr nzcv, x20" + "ubfx x20, x4, #31, #1", + "cmp wzr, w20", + "orr w4, w4, #0x80000000" ] }, "bts rax, 63": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /5", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000000000000000", - "lsr x20, x20, #63", - "lsl x20, x20, #29", - "orr x4, x4, #0x8000000000000000", - "msr nzcv, x20" + "lsr x20, x4, #63", + "cmp wzr, w20", + "orr x4, x4, #0x8000000000000000" ] }, "bts word [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", @@ -229,12 +211,13 @@ "strb w21, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bts dword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", @@ -242,12 +225,13 @@ "strb w21, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bts qword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", @@ -255,12 +239,13 @@ "strb w21, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bts word [rax], 15": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", @@ -269,12 +254,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bts dword [rax], 31": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", @@ -283,12 +269,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "bts qword [rax], 63": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", @@ -297,12 +284,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock bts word [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -310,12 +298,13 @@ "ldsetalb w20, w20, [x21]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock bts dword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -323,12 +312,13 @@ "ldsetalb w20, w20, [x21]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock bts qword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -336,12 +326,13 @@ "ldsetalb w20, w20, [x21]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock bts word [rax], 15": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", @@ -350,12 +341,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock bts dword [rax], 31": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", @@ -364,12 +356,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock bts qword [rax], 63": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", @@ -378,80 +371,69 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btr ax, 0": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "and w21, w4, #0xfffffffe", - "bfxil x4, x21, #0, #16", - "msr nzcv, x20" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", + "and w20, w4, #0xfffffffe", + "bfxil x4, x20, #0, #16" ] }, "btr eax, 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "and w4, w4, #0xfffffffe", - "msr nzcv, x20" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", + "and w4, w4, #0xfffffffe" ] }, "btr rax, 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x1", - "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "and x4, x4, #0xfffffffffffffffe", - "msr nzcv, x20" + "ubfx x20, x4, #0, #1", + "cmp wzr, w20", + "and x4, x4, #0xfffffffffffffffe" ] }, "btr ax, 15": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000", - "ubfx x20, x20, #15, #1", - "lsl x20, x20, #29", - "and w21, w4, #0xffff7fff", - "bfxil x4, x21, #0, #16", - "msr nzcv, x20" + "ubfx x20, x4, #15, #1", + "cmp wzr, w20", + "and w20, w4, #0xffff7fff", + "bfxil x4, x20, #0, #16" ] }, "btr eax, 31": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x80000000", - "ubfx x20, x20, #31, #1", - "lsl x20, x20, #29", - "and w4, w4, #0x7fffffff", - "msr nzcv, x20" + "ubfx x20, x4, #31, #1", + "cmp wzr, w20", + "and w4, w4, #0x7fffffff" ] }, "btr rax, 63": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ - "eor x20, x4, #0x8000000000000000", - "lsr x20, x20, #63", - "lsl x20, x20, #29", - "and x4, x4, #0x7fffffffffffffff", - "msr nzcv, x20" + "lsr x20, x4, #63", + "cmp wzr, w20", + "and x4, x4, #0x7fffffffffffffff" ] }, "btr word [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", @@ -459,12 +441,13 @@ "strb w21, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btr dword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", @@ -472,12 +455,13 @@ "strb w21, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btr qword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", @@ -485,12 +469,13 @@ "strb w21, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btr word [rax], 15": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", @@ -499,12 +484,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btr dword [rax], 31": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", @@ -513,12 +499,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btr qword [rax], 63": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", @@ -527,12 +514,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btr word [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -540,12 +528,13 @@ "ldclralb w20, w20, [x21]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btr dword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -553,12 +542,13 @@ "ldclralb w20, w20, [x21]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btr qword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -566,12 +556,13 @@ "ldclralb w20, w20, [x21]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btr word [rax], 15": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", @@ -580,12 +571,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btr dword [rax], 31": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", @@ -594,12 +586,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btr qword [rax], 63": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", @@ -608,74 +601,69 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btc ax, 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ "eor w20, w4, #0x1", "ubfx x21, x20, #0, #1", - "lsl x21, x21, #29", - "bfxil x4, x20, #0, #16", - "msr nzcv, x21" + "cmp w21, #0x1 (1)", + "bfxil x4, x20, #0, #16" ] }, "btc eax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ "eor w4, w4, #0x1", "ubfx x20, x4, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "cmp w20, #0x1 (1)" ] }, "btc rax, 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ "eor x4, x4, #0x1", "ubfx x20, x4, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "cmp w20, #0x1 (1)" ] }, "btc ax, 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ "eor w20, w4, #0x8000", "ubfx x21, x20, #15, #1", - "lsl x21, x21, #29", - "bfxil x4, x20, #0, #16", - "msr nzcv, x21" + "cmp w21, #0x1 (1)", + "bfxil x4, x20, #0, #16" ] }, "btc eax, 31": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ "eor w4, w4, #0x80000000", "ubfx x20, x4, #31, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "cmp w20, #0x1 (1)" ] }, "btc rax, 63": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Comment": "GROUP8 0x0F 0xBA /7", "ExpectedArm64ASM": [ "eor x4, x4, #0x8000000000000000", "lsr x20, x4, #63", - "lsl x20, x20, #29", - "msr nzcv, x20" + "cmp w20, #0x1 (1)" ] }, "btc word [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", @@ -683,12 +671,13 @@ "strb w21, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btc dword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", @@ -696,12 +685,13 @@ "strb w21, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btc qword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4]", @@ -709,12 +699,13 @@ "strb w21, [x4]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btc word [rax], 15": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #1]", @@ -723,12 +714,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btc dword [rax], 31": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #3]", @@ -737,12 +729,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "btc qword [rax], 63": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "ldrb w20, [x4, #7]", @@ -751,12 +744,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btc word [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -764,12 +758,13 @@ "ldeoralb w20, w20, [x21]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btc dword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -777,12 +772,13 @@ "ldeoralb w20, w20, [x21]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btc qword [rax], 0": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 8, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x1", @@ -790,12 +786,13 @@ "ldeoralb w20, w20, [x21]", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btc word [rax], 15": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", @@ -804,12 +801,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btc dword [rax], 31": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", @@ -818,12 +816,13 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lock btc qword [rax], 63": { - "ExpectedInstructionCount": 8, + "ExpectedInstructionCount": 9, "Comment": "GROUP8 0x0F 0xBA /6", "ExpectedArm64ASM": [ "mov w20, #0x80", @@ -832,8 +831,9 @@ "lsr w20, w20, #7", "eor x20, x20, #0x1", "ubfx x20, x20, #0, #1", - "lsl x20, x20, #29", - "msr nzcv, x20" + "mrs x21, nzcv", + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "cmpxchg8b [rbp]": { @@ -871,7 +871,7 @@ ] }, "rdrand ax": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", @@ -879,12 +879,14 @@ "mov w26, #0x1", "mov w27, #0x0", "cset w20, eq", - "lsl x20, x20, #29", + "mov w0, w27", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "rdrand eax": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x20, rndr", @@ -892,24 +894,28 @@ "mov w26, #0x1", "mov w27, #0x0", "cset w20, eq", - "lsl x20, x20, #29", + "mov w0, w27", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "rdrand rax": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "GROUP9 0x0F 0xC7 /6", "ExpectedArm64ASM": [ "mrs x4, rndr", "mov w26, #0x1", "mov w27, #0x0", "cset w20, eq", - "lsl x20, x20, #29", + "mov w0, w27", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "rdseed ax": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", @@ -917,12 +923,14 @@ "mov w26, #0x1", "mov w27, #0x0", "cset w20, eq", - "lsl x20, x20, #29", + "mov w0, w27", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "rdseed eax": { - "ExpectedInstructionCount": 7, + "ExpectedInstructionCount": 9, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x20, rndrrs", @@ -930,19 +938,23 @@ "mov w26, #0x1", "mov w27, #0x0", "cset w20, eq", - "lsl x20, x20, #29", + "mov w0, w27", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, "rdseed rax": { - "ExpectedInstructionCount": 6, + "ExpectedInstructionCount": 8, "Comment": "GROUP9 0x0F 0xC7 /7", "ExpectedArm64ASM": [ "mrs x4, rndrrs", "mov w26, #0x1", "mov w27, #0x0", "cset w20, eq", - "lsl x20, x20, #29", + "mov w0, w27", + "bfi w0, w20, #29, #1", + "mov w20, w0", "msr nzcv, x20" ] }, diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 17e7b56a6..540e2f7f9 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -452,8 +452,8 @@ "eor x20, x20, #0x10", "ubfx x20, x20, #4, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "tzcnt eax, ebx": { @@ -496,8 +496,8 @@ "eor x20, x20, #0x10", "ubfx x20, x20, #4, #1", "mrs x21, nzcv", - "orr w20, w21, w20, lsl #29", - "msr nzcv, x20" + "bfi w21, w20, #29, #1", + "msr nzcv, x21" ] }, "lzcnt eax, ebx": { diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 665ec21db..1421f6a7b 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -7590,7 +7590,7 @@ ] }, "fucomi st0, st0": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xe8 /5" ], @@ -7634,14 +7634,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fucomi st0, st1": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xe9 /5" ], @@ -7687,14 +7688,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fucomi st0, st2": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xea /5" ], @@ -7740,14 +7742,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fucomi st0, st3": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xeb /5" ], @@ -7793,14 +7796,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fucomi st0, st4": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xec /5" ], @@ -7846,14 +7850,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fucomi st0, st5": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xed /5" ], @@ -7899,14 +7904,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fucomi st0, st6": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xee /5" ], @@ -7952,14 +7958,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fucomi st0, st7": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xef /5" ], @@ -8005,14 +8012,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fcomi st0, st0": { - "ExpectedInstructionCount": 43, + "ExpectedInstructionCount": 44, "Comment": [ "0xdb 11b 0xf0 /6" ], @@ -8056,14 +8064,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fcomi st0, st1": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xf1 /6" ], @@ -8109,14 +8118,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fcomi st0, st2": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xf2 /6" ], @@ -8162,14 +8172,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fcomi st0, st3": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xf3 /6" ], @@ -8215,14 +8226,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fcomi st0, st4": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xf4 /6" ], @@ -8268,14 +8280,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fcomi st0, st5": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xf5 /6" ], @@ -8321,14 +8334,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fcomi st0, st6": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xf6 /6" ], @@ -8374,14 +8388,15 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fcomi st0, st7": { - "ExpectedInstructionCount": 45, + "ExpectedInstructionCount": 46, "Comment": [ "0xdb 11b 0xf7 /6" ], @@ -8427,10 +8442,11 @@ "orr w21, w21, w20", "orr w22, w22, w20", "eor x21, x21, #0x1", - "lsl x21, x21, #29", - "orr w21, w21, w22, lsl #30", + "mrs x23, nzcv", + "bfi w23, w21, #29, #1", + "bfi w23, w22, #30, #1", "eor w26, w20, #0x1", - "msr nzcv, x21" + "msr nzcv, x23" ] }, "fadd qword [rax]": { @@ -16745,7 +16761,7 @@ ] }, "fucomip st0": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xe8 /5" ], @@ -16789,22 +16805,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fucomip st1": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xe9 /5" ], @@ -16851,8 +16868,9 @@ "orr w23, w23, w22", "orr w24, w24, w22", "eor x23, x23, #0x1", - "lsl x23, x23, #29", - "orr w23, w23, w24, lsl #30", + "mrs x25, nzcv", + "bfi w25, w23, #29, #1", + "bfi w25, w24, #30, #1", "eor w26, w22, #0x1", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", @@ -16861,11 +16879,11 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x23" + "msr nzcv, x25" ] }, "fucomip st2": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xea /5" ], @@ -16911,22 +16929,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fucomip st3": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xeb /5" ], @@ -16972,22 +16991,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fucomip st4": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xec /5" ], @@ -17033,22 +17053,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fucomip st5": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xed /5" ], @@ -17094,22 +17115,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fucomip st6": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xee /5" ], @@ -17155,22 +17177,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fucomip st7": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xef /5" ], @@ -17216,22 +17239,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fcomip st0": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 52, "Comment": [ "0xdf 11b 0xf0 /6" ], @@ -17275,22 +17299,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fcomip st1": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xf1 /6" ], @@ -17337,8 +17362,9 @@ "orr w23, w23, w22", "orr w24, w24, w22", "eor x23, x23, #0x1", - "lsl x23, x23, #29", - "orr w23, w23, w24, lsl #30", + "mrs x25, nzcv", + "bfi w25, w23, #29, #1", + "bfi w25, w24, #30, #1", "eor w26, w22, #0x1", "ldrb w22, [x28, #1298]", "lsl w21, w21, w20", @@ -17347,11 +17373,11 @@ "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x23" + "msr nzcv, x25" ] }, "fcomip st2": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xf2 /6" ], @@ -17397,22 +17423,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fcomip st3": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xf3 /6" ], @@ -17458,22 +17485,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fcomip st4": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xf4 /6" ], @@ -17519,22 +17547,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fcomip st5": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xf5 /6" ], @@ -17580,22 +17609,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fcomip st6": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xf6 /6" ], @@ -17641,22 +17671,23 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "fcomip st7": { - "ExpectedInstructionCount": 53, + "ExpectedInstructionCount": 54, "Comment": [ "0xdf 11b 0xf7 /6" ], @@ -17702,18 +17733,19 @@ "orr w22, w22, w21", "orr w23, w23, w21", "eor x22, x22, #0x1", - "lsl x22, x22, #29", - "orr w22, w22, w23, lsl #30", - "mov w23, #0x1", + "mrs x24, nzcv", + "bfi w24, w22, #29, #1", + "bfi w24, w23, #30, #1", + "mov w22, #0x1", "eor w26, w21, #0x1", "ldrb w21, [x28, #1298]", - "lsl w23, w23, w20", - "bic w21, w21, w23", + "lsl w22, w22, w20", + "bic w21, w21, w22", "strb w21, [x28, #1298]", "add w20, w20, #0x1 (1)", "and w20, w20, #0x7", "strb w20, [x28, #1019]", - "msr nzcv, x22" + "msr nzcv, x24" ] }, "memcpy4_32": {