diff --git a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp
index 1e2ab0742..f6da5304c 100644
--- a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp
@@ -411,6 +411,7 @@ DEF_OP(ThreadRemoveCodeEntry) {
 DEF_OP(CPUID) {
   auto Op = IROp->C<IR::IROp_CPUID>();
 
+  isb();
   mov(ARMEmitter::Size::i64Bit, TMP2, GetReg(Op->Function));
   mov(ARMEmitter::Size::i64Bit, TMP3, GetReg(Op->Leaf));
 
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index ce60f1113..efb5fc558 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -1311,7 +1311,6 @@ void OpDispatchBuilder::CPUIDOp(OpcodeArgs) {
   Ref RCX = _AllocateGPR(false);
   Ref RDX = _AllocateGPR(false);
 
-  _Fence({FEXCore::IR::Fence_Inst});
   _CPUID(Src, Leaf, RAX, RBX, RCX, RDX);
 
   StoreGPRRegister(X86State::REG_RAX, RAX);