From 8bf22b63829b4a93961fa0004ade5a23fd7172d2 Mon Sep 17 00:00:00 2001 From: "Pierre-Loup A. Griffais" Date: Thu, 3 Sep 2026 17:51:11 -0700 Subject: [PATCH 1/2] DiskCache: add plumbing for guest-patching for branches To catch many conditional jumps found in Mono JITted code. --- FEXCore/Source/Interface/Core/CodeCache.cpp | 30 ++++++++++++++ FEXCore/Source/Interface/Core/DiskCache.cpp | 5 ++- FEXCore/Source/Interface/Core/Frontend.cpp | 39 ++++++++++++++++++- FEXCore/Source/Interface/Core/Frontend.h | 4 ++ .../Interface/Core/JIT/Arm64Relocations.cpp | 33 +++++++++++++++- .../Source/Interface/Core/JIT/BranchOps.cpp | 9 ++++- FEXCore/Source/Interface/Core/JIT/JIT.cpp | 12 ++++-- FEXCore/Source/Interface/Core/JIT/JITClass.h | 12 +++++- .../Source/Interface/Core/JIT/Relocations.h | 8 ++++ .../Source/Interface/Core/OpcodeDispatcher.h | 19 ++++++--- .../Interface/Core/X86Tables/X86Tables.h | 2 +- FEXCore/Source/Interface/IR/IR.json | 4 +- FEXCore/include/FEXCore/Core/DiskCache.h | 2 +- 13 files changed, 159 insertions(+), 20 deletions(-) diff --git a/FEXCore/Source/Interface/Core/CodeCache.cpp b/FEXCore/Source/Interface/Core/CodeCache.cpp index 5246c0247..f6feedca4 100644 --- a/FEXCore/Source/Interface/Core/CodeCache.cpp +++ b/FEXCore/Source/Interface/Core/CodeCache.cpp @@ -544,6 +544,27 @@ static inline void ApplyPatchableDataRelocation(uint64_t SiteAddress, uint8_t Va Emitter.LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(RegisterIndex), Value, CPU::Arm64Emitter::PadType::DOPAD); } +static inline int64_t ReadLiveGuestDisplacement(uint64_t SiteAddress, uint8_t ValueSize) { + uint64_t Raw = 0; + memcpy(&Raw, reinterpret_cast(SiteAddress), ValueSize); + // manual sign-extension from guest live bytes + // 1/2 sizes not permitted in DetectDataMasks currently + if (ValueSize == 4) { + return (int32_t)Raw; + } else { + return (int64_t)Raw; + } +} + +static inline void ApplyPatchableRIPLiteralRelocation(uint64_t SiteAddress, uint8_t ValueSize, CPU::Arm64Emitter& Emitter) { + Emitter.dc64(SiteAddress + ValueSize + ReadLiveGuestDisplacement(SiteAddress, ValueSize)); +} + +static inline void ApplyPatchableRIPMoveRelocation(uint64_t SiteAddress, uint8_t ValueSize, uint8_t RegisterIndex, CPU::Arm64Emitter& Emitter) { + const uint64_t Target = SiteAddress + ValueSize + ReadLiveGuestDisplacement(SiteAddress, ValueSize); + Emitter.LoadConstant(ARMEmitter::Size::i64Bit, ARMEmitter::Register(RegisterIndex), Target, CPU::Arm64Emitter::PadType::DOPAD); +} + bool CodeCache::ApplyPackedCodeRelocations(uint64_t GuestEntry, std::span Code, std::span SmallRelocs, std::span ThunkRelocs) { @@ -569,6 +590,15 @@ bool CodeCache::ApplyPackedCodeRelocations(uint64_t GuestEntry, std::spanOP >= 0xB8 && DecodeInst->OP <= 0xBF) { @@ -1416,12 +1417,20 @@ void Decoder::DetectDataMasks(uint64_t OpAddress, DecodedBlocks& Block) { // if (LiteralToPatch && Value < 0x1000000ULL) { // LiteralToPatch = nullptr; // } + Type = DataMaskType::MOV; + } + + // jmp/call branches that use a literal rip-relative offset + // some of those may be inlined by multiblock and will be cleaned up at decode end + if (DecodeInst->TableInfo->Flags & X86Tables::InstFlags::FLAGS_SETS_RIP && DecodeInst->Src[0].IsLiteral()) { + LiteralToPatch = &DecodeInst->Src[0]; + Type = DataMaskType::BRANCH; } // todo add a bunch more if (LiteralToPatch) { - Block.DataMasks.push_back({OpAddress + LastFieldReadOffset, LastFieldReadSize}); + Block.DataMasks.push_back({OpAddress + LastFieldReadOffset, Type, LastFieldReadSize}); LiteralToPatch->Type = X86Tables::DecodedOperand::OpType::LiteralPatchable; LiteralToPatch->Data.LiteralPatchable.FieldOffset = LastFieldReadOffset; @@ -1429,6 +1438,29 @@ void Decoder::DetectDataMasks(uint64_t OpAddress, DecodedBlocks& Block) { } } +void Decoder::PruneInlinedBranchDataMasks() { + for (auto& Block : BlockInfo.Blocks) { + if (!Block.DataMasks.size()) { + continue; + } + const auto& LastInst = Block.DecodedInstructions[Block.NumInstructions - 1]; + const auto& LastMask = Block.DataMasks.back(); + + if (LastMask.Type != DataMaskType::BRANCH) { + continue; + } + + const uint64_t NextInst = LastInst.PC + LastInst.InstSize; + if (LastMask.FieldAddress < LastInst.PC || LastMask.FieldAddress + LastMask.ValueSize > NextInst) { + continue; + } + + if (std::ranges::binary_search(BlockInfo.Blocks, NextInst + LastInst.Src[0].Data.LiteralPatchable.Value, std::less {}, &DecodedBlocks::Entry)) { + Block.DataMasks.pop_back(); + } + } +} + void Decoder::DecodeLoop(const uint8_t* _InstStream, uint64_t GuestSizePause) { // counter-intuitively, the masks are also needed for lookup on anon prefix decodes, not just stores bool WantsDataMasks = CTX->DiskCache.IsReadingDiskCache() || CTX->DiskCache.IsWritingDiskCache(); @@ -1640,6 +1672,11 @@ void Decoder::DecodeLoop(const uint8_t* _InstStream, uint64_t GuestSizePause) { for (auto& Block : BlockInfo.Blocks) { Block.IsEntryPoint = BlockInfo.EntryPoints.contains(Block.Entry); } + + // now that multiblock has settled down, remove any branch masks we put down that didn't end the block + if (WantsDataMasks) { + PruneInlinedBranchDataMasks(); + } } void Decoder::SetupDecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState* Thread, uint64_t PC, uint64_t MaxInst) { diff --git a/FEXCore/Source/Interface/Core/Frontend.h b/FEXCore/Source/Interface/Core/Frontend.h index 5a3ec199f..d71a9c073 100644 --- a/FEXCore/Source/Interface/Core/Frontend.h +++ b/FEXCore/Source/Interface/Core/Frontend.h @@ -32,8 +32,11 @@ public: UNIMPLEMENTED_INST, }; + enum class DataMaskType : uint8_t { MOV, BRANCH }; + struct DataMask final { uint64_t FieldAddress; + DataMaskType Type; uint8_t ValueSize; }; @@ -110,6 +113,7 @@ private: void AddBranchTarget(uint64_t Target); void DetectDataMasks(uint64_t OpAddress, DecodedBlocks& Block); + void PruneInlinedBranchDataMasks(); bool CheckRangeExecutable(uint64_t Address, uint64_t Size); diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp index 47c4f1159..587784468 100644 --- a/FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp +++ b/FEXCore/Source/Interface/Core/JIT/Arm64Relocations.cpp @@ -58,7 +58,8 @@ Arm64JITCore::NamedSymbolLiteralPair Arm64JITCore::InsertNamedSymbolLiteral(FEXC void Arm64JITCore::PlaceNamedSymbolLiteral(NamedSymbolLiteralPair Lit) { switch (Lit.MoveABI.Header.Type) { case RelocationTypes::RELOC_NAMED_SYMBOL_LITERAL: - case RelocationTypes::RELOC_GUEST_RIP_LITERAL: { + case RelocationTypes::RELOC_GUEST_RIP_LITERAL: + case RelocationTypes::RELOC_GUEST_PATCHABLE_RIP_LITERAL: { Lit.MoveABI.Header.Offset = GetCursorOffset(); break; } @@ -102,6 +103,24 @@ void Arm64JITCore::InsertGuestRIPMove(ARMEmitter::Register Reg, uint64_t Constan Relocations.emplace_back(MoveABI); } +auto Arm64JITCore::InsertGuestPatchableRIPLiteral(uint64_t GuestRIP, uint64_t SiteAddress, uint8_t ValueSize) -> NamedSymbolLiteralPair { + return { + .Lit = GuestRIP, + .MoveABI = + { + .GuestPatchableData = {.Header = + { + .Offset = 0, // Set by PlaceNamedSymbolLiteral + .Type = FEXCore::CPU::RelocationTypes::RELOC_GUEST_PATCHABLE_RIP_LITERAL, + }, + .RegisterIndex = 0, // unused + .ValueSize = ValueSize, + // NOTE: Cache serialization will subtract the unit entry address later + .SiteAddress = SiteAddress}, + }, + }; +} + void Arm64JITCore::InsertGuestPatchableDataMove(ARMEmitter::Register Reg, uint64_t Value, uint64_t SiteAddress, uint8_t ValueSize) { Relocation MoveABI = Relocation::Default(); MoveABI.GuestPatchableData.Header = {.Offset = GetCursorOffset(), .Type = FEXCore::CPU::RelocationTypes::RELOC_GUEST_PATCHABLE_DATA_MOVE}; @@ -114,6 +133,18 @@ void Arm64JITCore::InsertGuestPatchableDataMove(ARMEmitter::Register Reg, uint64 Relocations.emplace_back(MoveABI); } +void Arm64JITCore::InsertGuestPatchableRIPMove(ARMEmitter::Register Reg, uint64_t Value, uint64_t SiteAddress, uint8_t ValueSize) { + Relocation MoveABI = Relocation::Default(); + MoveABI.GuestPatchableData.Header = {.Offset = GetCursorOffset(), .Type = FEXCore::CPU::RelocationTypes::RELOC_GUEST_PATCHABLE_RIP_MOVE}; + MoveABI.GuestPatchableData.RegisterIndex = Reg.Idx(); + MoveABI.GuestPatchableData.ValueSize = ValueSize; + MoveABI.GuestPatchableData.SiteAddress = SiteAddress; + + // this might get patched on disk cache load + LoadConstant(ARMEmitter::Size::i64Bit, Reg, Value, FEXCore::CPU::Arm64Emitter::PadType::DOPAD); + Relocations.emplace_back(MoveABI); +} + fextl::vector Arm64JITCore::TakeRelocations(uint64_t GuestBaseAddress) { // Rebase relocations to library base address for (auto& Relocation : Relocations) { diff --git a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp index ddf3e870a..4cbf45c39 100644 --- a/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp +++ b/FEXCore/Source/Interface/Core/JIT/BranchOps.cpp @@ -83,7 +83,11 @@ DEF_OP(ExitFunction) { if (NewRIP < EC_CODE_BITMAP_MAX_ADDRESS && RtlIsEcCode(NewRIP)) { str(REG_CALLRET_SP, STATE_PTR(CpuStateFrame, State.callret_sp)); add(ARMEmitter::Size::i64Bit, ARMEmitter::Reg::rsp, StaticRegisters[X86State::REG_RSP], 0); - InsertGuestRIPMove(EC_CALL_CHECKER_PC_REG, NewRIP); + if (Op->PatchSiteAddress) { + InsertGuestPatchableRIPMove(EC_CALL_CHECKER_PC_REG, NewRIP, Op->PatchSiteAddress, Op->PatchSiteSize); + } else { + InsertGuestRIPMove(EC_CALL_CHECKER_PC_REG, NewRIP); + } ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.ExitFunctionEC)); br(TMP2); } else { @@ -173,6 +177,7 @@ DEF_OP(ExitFunction) { ARMEmitter::ForwardLabel TFUnset; ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC])); (void)cbz(ARMEmitter::Size::i32Bit, TMP1, &TFUnset); + // todo do we need to account for cache patching here? InsertGuestRIPMove(TMP1, NewRIP); str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip)); ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.DispatcherLoopTop)); @@ -180,7 +185,7 @@ DEF_OP(ExitFunction) { (void)Bind(&TFUnset); } - EmitLinkedBranch(NewRIP, Op->Hint == IR::BranchHint::Call); + EmitLinkedBranch(NewRIP, Op->Hint == IR::BranchHint::Call, Op->PatchSiteAddress, Op->PatchSiteSize); (void)Bind(&l_CallReturn); #ifdef ARCHITECTURE_arm64ec } diff --git a/FEXCore/Source/Interface/Core/JIT/JIT.cpp b/FEXCore/Source/Interface/Core/JIT/JIT.cpp index 7330e40a6..c23f01a3d 100644 --- a/FEXCore/Source/Interface/Core/JIT/JIT.cpp +++ b/FEXCore/Source/Interface/Core/JIT/JIT.cpp @@ -1019,9 +1019,15 @@ CPUBackend::CompiledCode Arm64JITCore::CompileCode(uint64_t Entry, uint64_t Size // This is a ExitFunctionLinkData struct BindOrRestart(&l_ExitLink); - dc64(0); // HostCode - PlaceNamedSymbolLiteral(InsertGuestRIPLiteral(PendingJumpThunk.GuestRIP)); // GuestRIP - dc64(PendingJumpThunk.CallerAddress - ThunkAddress); // CallerOffset + dc64(0); // HostCode + if (PendingJumpThunk.PatchSiteAddress) { + // GuestRIP with an extra step + PlaceNamedSymbolLiteral( + InsertGuestPatchableRIPLiteral(PendingJumpThunk.GuestRIP, PendingJumpThunk.PatchSiteAddress, PendingJumpThunk.PatchSiteSize)); + } else { + PlaceNamedSymbolLiteral(InsertGuestRIPLiteral(PendingJumpThunk.GuestRIP)); // GuestRIP + } + dc64(PendingJumpThunk.CallerAddress - ThunkAddress); // CallerOffset } BindOrRestart(&l_ExitLink); diff --git a/FEXCore/Source/Interface/Core/JIT/JITClass.h b/FEXCore/Source/Interface/Core/JIT/JITClass.h index 2a56a7efe..8758f9a64 100644 --- a/FEXCore/Source/Interface/Core/JIT/JITClass.h +++ b/FEXCore/Source/Interface/Core/JIT/JITClass.h @@ -105,6 +105,8 @@ private: uint64_t CallerAddress; uint64_t GuestRIP; ARMEmitter::ForwardLabel Label; + uint64_t PatchSiteAddress = 0; + uint8_t PatchSiteSize = 0; }; fextl::vector PendingJumpThunks; @@ -345,8 +347,8 @@ private: uint32_t End; }; - void EmitLinkedBranch(uint64_t GuestRIP, bool Call) { - PendingJumpThunks.push_back({GetCursorAddress(), GuestRIP, {}}); + void EmitLinkedBranch(uint64_t GuestRIP, bool Call, uint64_t PatchSiteAddress = 0, uint8_t PatchSiteSize = 0) { + PendingJumpThunks.push_back({GetCursorAddress(), GuestRIP, {}, PatchSiteAddress, PatchSiteSize}); auto& Thunk = PendingJumpThunks.back(); BindOrRestart(&Thunk.Label); if (Call) { @@ -563,6 +565,7 @@ private: void InsertGuestRIPMove(ARMEmitter::Register Reg, uint64_t Constant); void InsertGuestPatchableDataMove(ARMEmitter::Register Reg, uint64_t Value, uint64_t SiteAddress, uint8_t ValueSize); + void InsertGuestPatchableRIPMove(ARMEmitter::Register Reg, uint64_t Value, uint64_t SiteAddress, uint8_t ValueSize); /** * @brief Inserts a named symbol as a literal in memory @@ -583,6 +586,11 @@ private: */ NamedSymbolLiteralPair InsertGuestRIPLiteral(uint64_t GuestRIP); + /** + * @brief Like InsertGuestRIPLiteral, but with patch information to recompute value from live guest bytes at cache load time + */ + NamedSymbolLiteralPair InsertGuestPatchableRIPLiteral(uint64_t GuestRIP, uint64_t SiteAddress, uint8_t ValueSize); + /** * @brief Place the named symbol literal relocation in memory * diff --git a/FEXCore/Source/Interface/Core/JIT/Relocations.h b/FEXCore/Source/Interface/Core/JIT/Relocations.h index ec268874d..c2b7db98d 100644 --- a/FEXCore/Source/Interface/Core/JIT/Relocations.h +++ b/FEXCore/Source/Interface/Core/JIT/Relocations.h @@ -29,6 +29,14 @@ enum class RelocationTypes : uint32_t { // The frontend flagged those regions as patchable by the disk cache // Aligned to struct RelocGuestPatchableData RELOC_GUEST_PATCHABLE_DATA_MOVE, + + // Same as GuestRipLiteral but patchable + // Aligned to struct RelocGuestPatchableData + RELOC_GUEST_PATCHABLE_RIP_LITERAL, + + // Like PATCHABLE_RIP_LITERAL but puts it in a register + // Aligned to struct RelocGuestPatchableData + RELOC_GUEST_PATCHABLE_RIP_MOVE, }; struct FEX_PACKED RelocationHeader final { diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h index 5a5737131..ff5c38951 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.h +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.h @@ -202,9 +202,10 @@ public: FlushRegisterCache(); return _ExitFunction(GetOpSize(NewRIP), NewRIP, Hint, InvalidNode, InvalidNode); } - IRPair ExitFunction(Ref NewRIP, BranchHint Hint, Ref CallReturnAddress, Ref CallReturnBlock) { + IRPair ExitFunction(Ref NewRIP, BranchHint Hint, Ref CallReturnAddress, Ref CallReturnBlock, + uint64_t PatchSiteAddress = 0, uint64_t PatchSiteSize = 0) { FlushRegisterCache(); - return _ExitFunction(GetOpSize(NewRIP), NewRIP, Hint, CallReturnAddress, CallReturnBlock); + return _ExitFunction(GetOpSize(NewRIP), NewRIP, Hint, CallReturnAddress, CallReturnBlock, PatchSiteAddress, PatchSiteSize); } IRPair Break(BreakDefinition Reason) { FlushRegisterCache(); @@ -1510,12 +1511,18 @@ private: return _GetRelocatedPC(Op, Offset, false); } - void ExitRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset = 0) { - ExitFunction(_GetRelocatedPC(Op, Offset, true /* Inline */)); + void ExitRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset, BranchHint Hint, Ref CallReturnAddress, Ref CallReturnBlock) { + uint64_t PatchOffset = 0; + uint64_t PatchSize = 0; + if (Op->Src[0].IsLiteralPatchable() && Offset && Offset == (int64_t)Op->Src[0].Literal()) { + PatchOffset = Op->PC + Op->Src[0].Data.LiteralPatchable.FieldOffset; + PatchSize = Op->Src[0].Data.LiteralPatchable.Width; + } + ExitFunction(_GetRelocatedPC(Op, Offset, true /* Inline */), Hint, CallReturnAddress, CallReturnBlock, PatchOffset, PatchSize); } - void ExitRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset, BranchHint Hint, Ref CallReturnAddress, Ref CallReturnBlock) { - ExitFunction(_GetRelocatedPC(Op, Offset, true /* Inline */), Hint, CallReturnAddress, CallReturnBlock); + void ExitRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset = 0) { + ExitRelocatedPC(Op, Offset, BranchHint::None, InvalidNode, InvalidNode); } [[nodiscard]] diff --git a/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h b/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h index 9ab0cfbaa..bae27564a 100644 --- a/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h +++ b/FEXCore/Source/Interface/Core/X86Tables/X86Tables.h @@ -171,7 +171,7 @@ struct DecodedOperand { } uint64_t Literal() const { - LOGMAN_THROW_A_FMT(IsLiteral(), "Precondition: must be a literal"); + LOGMAN_THROW_A_FMT(IsLiteral() || IsLiteralPatchable(), "Precondition: must be a literal"); return Data.Literal.Value; } diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json index 61d0e0fd0..c1a80970f 100644 --- a/FEXCore/Source/Interface/IR/IR.json +++ b/FEXCore/Source/Interface/IR/IR.json @@ -312,8 +312,8 @@ "HasSideEffects": true, "RAOverride": "2" }, - "ExitFunction OpSize:#Size, GPR:$NewRIP, BranchHint:$Hint, GPR:$CallReturnAddress, SSA:$CallReturnBlock": { - "Desc": ["Exits the current JIT function with a target RIP" + "ExitFunction OpSize:#Size, GPR:$NewRIP, BranchHint:$Hint, GPR:$CallReturnAddress, SSA:$CallReturnBlock, i64:$PatchSiteAddress{0}, i64:$PatchSiteSize{0}": { + "Desc": ["Exits the current JIT function with a target RIP - optionally patchable from guest bytes for caching" ], "Inline": ["Any"], "HasSideEffects": true, diff --git a/FEXCore/include/FEXCore/Core/DiskCache.h b/FEXCore/include/FEXCore/Core/DiskCache.h index 4071a8572..7ece69444 100644 --- a/FEXCore/include/FEXCore/Core/DiskCache.h +++ b/FEXCore/include/FEXCore/Core/DiskCache.h @@ -221,7 +221,7 @@ namespace DiskCache { // TODO: This header is in global installed header path, but uses internal headers. // Migrate this once that is fixed. - static constexpr uint16_t FormatVersion = 17; + static constexpr uint16_t FormatVersion = 18; FEX_DEFAULT_VISIBILITY uint16_t GetFormatVersion(); } // namespace DiskCache From ffaa5d63161f010df95c43d8ae684021674dea3a Mon Sep 17 00:00:00 2001 From: "Pierre-Loup A. Griffais" Date: Mon, 7 Sep 2026 00:56:39 -0700 Subject: [PATCH 2/2] InstcountCI: Update --- unittests/InstructionCountCI/AFP/H0F3A.json | 2 +- unittests/InstructionCountCI/AFP/SVE256/Secondary.json | 2 +- unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json | 2 +- unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json | 2 +- unittests/InstructionCountCI/AFP/Secondary.json | 2 +- unittests/InstructionCountCI/AFP/Secondary_REP.json | 2 +- unittests/InstructionCountCI/AFP/Secondary_REPNE.json | 2 +- unittests/InstructionCountCI/AFP/VEX_map1.json | 2 +- unittests/InstructionCountCI/AFP/VEX_map3.json | 2 +- unittests/InstructionCountCI/AVX128/FMA4.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map1.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map2.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map3.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json | 2 +- unittests/InstructionCountCI/AVX128/VEX_map_group.json | 2 +- unittests/InstructionCountCI/Atomics.json | 2 +- unittests/InstructionCountCI/Crypto/H0F38.json | 2 +- unittests/InstructionCountCI/Crypto/H0F38_SVE128.json | 2 +- unittests/InstructionCountCI/Crypto/H0F3A.json | 2 +- unittests/InstructionCountCI/DDD.json | 2 +- unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json | 2 +- .../InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json | 2 +- unittests/InstructionCountCI/FEXOpt/MultiInst.json | 2 +- unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json | 2 +- unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json | 2 +- unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json | 2 +- unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json | 2 +- unittests/InstructionCountCI/FEXOpt/libnss.json | 2 +- unittests/InstructionCountCI/FlagM/Atomics.json | 2 +- unittests/InstructionCountCI/FlagM/FlagOpts.json | 2 +- unittests/InstructionCountCI/FlagM/H0F38.json | 2 +- unittests/InstructionCountCI/FlagM/HotBlocks.json | 2 +- unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json | 2 +- unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json | 2 +- unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json | 2 +- unittests/InstructionCountCI/FlagM/Primary.json | 2 +- unittests/InstructionCountCI/FlagM/PrimaryGroup.json | 2 +- unittests/InstructionCountCI/FlagM/Primary_32Bit.json | 2 +- unittests/InstructionCountCI/FlagM/Secondary.json | 2 +- unittests/InstructionCountCI/FlagM/SecondaryGroup.json | 2 +- unittests/InstructionCountCI/FlagM/SecondaryModRM.json | 2 +- unittests/InstructionCountCI/FlagM/Secondary_OpSize.json | 2 +- unittests/InstructionCountCI/FlagM/Secondary_REP.json | 2 +- unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json | 2 +- unittests/InstructionCountCI/FlagM/VEX_map1.json | 2 +- unittests/InstructionCountCI/FlagM/VEX_map2.json | 2 +- unittests/InstructionCountCI/FlagM/VEX_map_group.json | 2 +- unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json | 2 +- unittests/InstructionCountCI/FlagM/x87-HalfLife.json | 2 +- unittests/InstructionCountCI/FlagM/x87-Oblivion.json | 2 +- unittests/InstructionCountCI/FlagM/x87-Psychonauts.json | 2 +- unittests/InstructionCountCI/FlagM/x87.json | 2 +- .../InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json | 2 +- unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json | 2 +- unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json | 2 +- unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json | 2 +- unittests/InstructionCountCI/FlagM/x87_f64.json | 2 +- unittests/InstructionCountCI/H0F38.json | 2 +- unittests/InstructionCountCI/H0F3A.json | 2 +- unittests/InstructionCountCI/H0F3A_SVE128.json | 2 +- unittests/InstructionCountCI/MOPS/Primary.json | 2 +- unittests/InstructionCountCI/Primary.json | 2 +- unittests/InstructionCountCI/PrimaryGroup.json | 2 +- unittests/InstructionCountCI/Primary_32Bit.json | 2 +- unittests/InstructionCountCI/RPRES/DDD.json | 2 +- unittests/InstructionCountCI/RPRES/Secondary.json | 2 +- unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json | 2 +- unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json | 2 +- unittests/InstructionCountCI/Repeat.json | 2 +- unittests/InstructionCountCI/SSE42_Strings.json | 2 +- unittests/InstructionCountCI/Secondary.json | 2 +- unittests/InstructionCountCI/SecondaryGroup.json | 2 +- unittests/InstructionCountCI/SecondaryModRM.json | 2 +- unittests/InstructionCountCI/Secondary_32Bit.json | 2 +- unittests/InstructionCountCI/Secondary_OpSize.json | 2 +- unittests/InstructionCountCI/Secondary_OpSize_FCMA.json | 2 +- unittests/InstructionCountCI/Secondary_OpSize_SVE128.json | 2 +- unittests/InstructionCountCI/Secondary_OpSize_SVE256.json | 2 +- unittests/InstructionCountCI/Secondary_REP.json | 2 +- unittests/InstructionCountCI/Secondary_REPNE.json | 2 +- unittests/InstructionCountCI/Secondary_REPNE_FCMA.json | 2 +- unittests/InstructionCountCI/Secondary_REPNE_SVE128.json | 2 +- unittests/InstructionCountCI/Secondary_REP_FRINTTS.json | 2 +- unittests/InstructionCountCI/Secondary_SVE128.json | 2 +- unittests/InstructionCountCI/VEX_map1.json | 2 +- unittests/InstructionCountCI/VEX_map1_FCMA.json | 2 +- unittests/InstructionCountCI/VEX_map1_FRINTTS.json | 2 +- unittests/InstructionCountCI/VEX_map2.json | 2 +- unittests/InstructionCountCI/VEX_map2_svebitperm.json | 2 +- unittests/InstructionCountCI/VEX_map3.json | 2 +- unittests/InstructionCountCI/VEX_map_group.json | 2 +- unittests/InstructionCountCI/X87ldst-SVE.json | 2 +- unittests/InstructionCountCI/x87.json | 2 +- unittests/InstructionCountCI/x87_32Bit.json | 2 +- unittests/InstructionCountCI/x87_f64.json | 2 +- unittests/InstructionCountCI/x87_f64_32Bit.json | 2 +- 102 files changed, 102 insertions(+), 102 deletions(-) diff --git a/unittests/InstructionCountCI/AFP/H0F3A.json b/unittests/InstructionCountCI/AFP/H0F3A.json index bd34f2ddf..dff87a3c7 100644 --- a/unittests/InstructionCountCI/AFP/H0F3A.json +++ b/unittests/InstructionCountCI/AFP/H0F3A.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "roundss xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json index a37f43b00..0f0728235 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "cvtpi2ps xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json index 52b2ae6e3..c2fcf8a8a 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REP.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "RPRES" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json index 1b3e7dd95..f4921f3c8 100644 --- a/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/SVE256/Secondary_REPNE.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "cvtsi2sd xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/Secondary.json b/unittests/InstructionCountCI/AFP/Secondary.json index 292819b02..7e95b21fc 100644 --- a/unittests/InstructionCountCI/AFP/Secondary.json +++ b/unittests/InstructionCountCI/AFP/Secondary.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "cvtpi2ps xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AFP/Secondary_REP.json b/unittests/InstructionCountCI/AFP/Secondary_REP.json index fe5c07dcd..fef2244c7 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REP.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REP.json @@ -9,7 +9,7 @@ "SVE256", "RPRES" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "cvtsi2ss xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json index 1dda36183..71e097fd5 100644 --- a/unittests/InstructionCountCI/AFP/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/AFP/Secondary_REPNE.json @@ -8,7 +8,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "cvtsi2sd xmm0, eax": { diff --git a/unittests/InstructionCountCI/AFP/VEX_map1.json b/unittests/InstructionCountCI/AFP/VEX_map1.json index c3d8bf981..d5c7bc6bd 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map1.json +++ b/unittests/InstructionCountCI/AFP/VEX_map1.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "RPRES" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vsqrtss xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AFP/VEX_map3.json b/unittests/InstructionCountCI/AFP/VEX_map3.json index 295970a7d..353d69429 100644 --- a/unittests/InstructionCountCI/AFP/VEX_map3.json +++ b/unittests/InstructionCountCI/AFP/VEX_map3.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vroundss xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/AVX128/FMA4.json b/unittests/InstructionCountCI/AVX128/FMA4.json index 4a4b0e8ac..51ff81b13 100644 --- a/unittests/InstructionCountCI/AVX128/FMA4.json +++ b/unittests/InstructionCountCI/AVX128/FMA4.json @@ -7,7 +7,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vfmaddsubps xmm0, xmm1, xmm2, xmm3": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index 46f9bf40b..c3562c8cf 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -13,7 +13,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vmovups xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json index fd32e9a83..e36d16522 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vaddsubpd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json index 8f9294ffc..80e23176c 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_SVE128.json @@ -10,7 +10,7 @@ "FLAGM2", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vmovntps [rax], xmm0": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json index 6e6f52f37..90c520a58 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1_flagm.json @@ -10,7 +10,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index 70152ab68..a0e2df6cc 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json index 5c021fc5e..7d9de81a4 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_AFP.json @@ -8,7 +8,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vfmadd132ss xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json index 90879d321..1a566de2a 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json @@ -10,7 +10,7 @@ "FLAGM2", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vmovntdqa xmm0, [rax]": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json index 12145dbd2..b32496d37 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_flagm.json @@ -11,7 +11,7 @@ "SVE256", "SVEBITPERM" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vtestps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json index ff4293805..367e80944 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json @@ -7,7 +7,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vpermq ymm0, ymm1, 1": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json index 1427c1b94..61c206a77 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3_SVE128.json @@ -8,7 +8,7 @@ "AFP", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vblendvps xmm0, xmm1, xmm2, xmm3": { diff --git a/unittests/InstructionCountCI/AVX128/VEX_map_group.json b/unittests/InstructionCountCI/AVX128/VEX_map_group.json index b6018049f..075cada5e 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map_group.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map_group.json @@ -9,7 +9,7 @@ "SVE256", "SVE128" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vpsrlw xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/Atomics.json b/unittests/InstructionCountCI/Atomics.json index 71e006f4b..dcc10a870 100644 --- a/unittests/InstructionCountCI/Atomics.json +++ b/unittests/InstructionCountCI/Atomics.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "lock add byte [rax], cl": { diff --git a/unittests/InstructionCountCI/Crypto/H0F38.json b/unittests/InstructionCountCI/Crypto/H0F38.json index 64f87944a..3640708ab 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38.json +++ b/unittests/InstructionCountCI/Crypto/H0F38.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "sha1nexte xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json index c5f923a27..12c389a95 100644 --- a/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json +++ b/unittests/InstructionCountCI/Crypto/H0F38_SVE128.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "sha1nexte xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index 8faef2e5a..0520e00e4 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "pclmulqdq xmm0, xmm1, 00000b": { diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json index a0199660a..9607166b8 100644 --- a/unittests/InstructionCountCI/DDD.json +++ b/unittests/InstructionCountCI/DDD.json @@ -10,7 +10,7 @@ "AFP", "RPRES" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "These 3DNow! instructions are optimal assuming that FEX doesn't SRA MMX registers", diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json index f98dbfdbc..d56501b39 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations.json @@ -8,7 +8,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "Instructions that explicitly push against the limits of ARM's loadstore instructions" diff --git a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json index ab9c9dd36..6f7da37f7 100644 --- a/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json +++ b/unittests/InstructionCountCI/FEXOpt/AddressingLimitations_32Bit.json @@ -8,7 +8,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "Instructions that explicitly push against the limits of ARM's loadstore instructions" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst.json b/unittests/InstructionCountCI/FEXOpt/MultiInst.json index 11f507850..665e8059d 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst.json @@ -13,7 +13,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json index 1bb94240f..184cd7a06 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_32bit.json @@ -11,7 +11,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json index d0fc59e59..fc5bf5d6d 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_AFP.json @@ -9,7 +9,7 @@ "SVE256", "RPRES" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json index df69e1e7f..ddf789428 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json @@ -14,7 +14,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json index d7b17be40..934d62811 100644 --- a/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json +++ b/unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json @@ -14,7 +14,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "These are instruction combinations that could be more optimal if FEX optimized for them" diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json index 4657e71c1..a93fcb34a 100644 --- a/unittests/InstructionCountCI/FEXOpt/libnss.json +++ b/unittests/InstructionCountCI/FEXOpt/libnss.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [], "Instructions": { diff --git a/unittests/InstructionCountCI/FlagM/Atomics.json b/unittests/InstructionCountCI/FlagM/Atomics.json index 32ca5e655..106e9bec0 100644 --- a/unittests/InstructionCountCI/FlagM/Atomics.json +++ b/unittests/InstructionCountCI/FlagM/Atomics.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "lock add byte [rax], cl": { diff --git a/unittests/InstructionCountCI/FlagM/FlagOpts.json b/unittests/InstructionCountCI/FlagM/FlagOpts.json index 5a13a44ef..1910f7718 100644 --- a/unittests/InstructionCountCI/FlagM/FlagOpts.json +++ b/unittests/InstructionCountCI/FlagM/FlagOpts.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Chained add": { diff --git a/unittests/InstructionCountCI/FlagM/H0F38.json b/unittests/InstructionCountCI/FlagM/H0F38.json index e885cfac8..ead3af55a 100644 --- a/unittests/InstructionCountCI/FlagM/H0F38.json +++ b/unittests/InstructionCountCI/FlagM/H0F38.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "ptest xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks.json b/unittests/InstructionCountCI/FlagM/HotBlocks.json index 56e5ce0b2..403fee434 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "The Witcher 3": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json index 5b629819c..2fd1757c9 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Sonic Mania movie player": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json index 7fb0896d8..dcf0eb5c7 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_AFP.json @@ -10,7 +10,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "FMOD scalar loop": { diff --git a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json index 37deb2032..1bc6b960c 100644 --- a/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "The Sims 1 hot block": { diff --git a/unittests/InstructionCountCI/FlagM/Primary.json b/unittests/InstructionCountCI/FlagM/Primary.json index 6baacce55..d2f70fa20 100644 --- a/unittests/InstructionCountCI/FlagM/Primary.json +++ b/unittests/InstructionCountCI/FlagM/Primary.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "add bl, cl": { diff --git a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json index 46172bf1f..5d8ef4cba 100644 --- a/unittests/InstructionCountCI/FlagM/PrimaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/PrimaryGroup.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "add al, 1": { diff --git a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json index 7262cced5..b39839294 100644 --- a/unittests/InstructionCountCI/FlagM/Primary_32Bit.json +++ b/unittests/InstructionCountCI/FlagM/Primary_32Bit.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "push es": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 9234efa77..6f936b040 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -11,7 +11,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "ucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json index 8b9ada413..d675d6ce3 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryGroup.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryGroup.json @@ -11,7 +11,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "sgdt [rax]": { diff --git a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json index fefcfb50a..6394458ef 100644 --- a/unittests/InstructionCountCI/FlagM/SecondaryModRM.json +++ b/unittests/InstructionCountCI/FlagM/SecondaryModRM.json @@ -11,7 +11,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "xgetbv": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index bb6e26ed7..3a65064d3 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -11,7 +11,7 @@ "AFP", "FCMA" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "ucomisd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP.json b/unittests/InstructionCountCI/FlagM/Secondary_REP.json index 8dd192431..d4baba203 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP.json @@ -12,7 +12,7 @@ "AFP", "CSSC" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "popcnt ax, bx": { diff --git a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json index 8fdaba4f3..1dba37f92 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_REP_CSSC.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "popcnt ax, bx": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index b78fd20ee..9c8d6ded6 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -12,7 +12,7 @@ "RPRES", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vucomiss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map2.json b/unittests/InstructionCountCI/FlagM/VEX_map2.json index 71d99f070..81a94abb9 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map2.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map2.json @@ -10,7 +10,7 @@ "AFP", "SVEBITPERM" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vtestps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/FlagM/VEX_map_group.json b/unittests/InstructionCountCI/FlagM/VEX_map_group.json index da91736d0..c6b2aad8e 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map_group.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map_group.json @@ -9,7 +9,7 @@ "DisabledHostFeatures": [ "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "blsr eax, ebx": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json index 7cfd13025..81c43c207 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index f91aa0479..e2908db97 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 9fba60a14..b3546be82 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index 66f2074cf..ec65634c8 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -10,7 +10,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 156507033..a55663ac9 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -11,7 +11,7 @@ "CSSC", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json index 3a82f80f4..2d54197f0 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Crysis2Max-fmodel.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json index 7f56b2eb4..01b022170 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-HalfLife.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json index 111d5f8ae..f05ba353b 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Oblivion.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json index 46e9ea7c8..3c5f0a78c 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64-Psychonauts.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Block1": { diff --git a/unittests/InstructionCountCI/FlagM/x87_f64.json b/unittests/InstructionCountCI/FlagM/x87_f64.json index 8d069ce56..bc05b2b7f 100644 --- a/unittests/InstructionCountCI/FlagM/x87_f64.json +++ b/unittests/InstructionCountCI/FlagM/x87_f64.json @@ -13,7 +13,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index 5dd3d0e64..cdac105dd 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -10,7 +10,7 @@ "FLAGM2", "CRYPTO" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "pshufb mm0, mm1": { diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index ea90b11af..10057a6c4 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -8,7 +8,7 @@ "AFP", "CRYPTO" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "SSE4.2 string instructions are skipped here.", diff --git a/unittests/InstructionCountCI/H0F3A_SVE128.json b/unittests/InstructionCountCI/H0F3A_SVE128.json index 55accf205..878b77bf6 100644 --- a/unittests/InstructionCountCI/H0F3A_SVE128.json +++ b/unittests/InstructionCountCI/H0F3A_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "dpps xmm0, xmm1, 00000000b": { diff --git a/unittests/InstructionCountCI/MOPS/Primary.json b/unittests/InstructionCountCI/MOPS/Primary.json index 58eefc894..1900db8ec 100644 --- a/unittests/InstructionCountCI/MOPS/Primary.json +++ b/unittests/InstructionCountCI/MOPS/Primary.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "rep movsb": { diff --git a/unittests/InstructionCountCI/Primary.json b/unittests/InstructionCountCI/Primary.json index 609685bba..de7c21257 100644 --- a/unittests/InstructionCountCI/Primary.json +++ b/unittests/InstructionCountCI/Primary.json @@ -10,7 +10,7 @@ "FLAGM2", "MOPS" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "add bl, cl": { diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index 054fea7c4..08f02e219 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "Instructions in this table that are marked optimal don't have their flag calculation part of this assumption", diff --git a/unittests/InstructionCountCI/Primary_32Bit.json b/unittests/InstructionCountCI/Primary_32Bit.json index 5150ff837..8b568de4d 100644 --- a/unittests/InstructionCountCI/Primary_32Bit.json +++ b/unittests/InstructionCountCI/Primary_32Bit.json @@ -9,7 +9,7 @@ "FlagM", "FlagM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "push es": { diff --git a/unittests/InstructionCountCI/RPRES/DDD.json b/unittests/InstructionCountCI/RPRES/DDD.json index 2c01a7dca..c6f7d8add 100644 --- a/unittests/InstructionCountCI/RPRES/DDD.json +++ b/unittests/InstructionCountCI/RPRES/DDD.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "pfrcpv mm0, mm1": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary.json b/unittests/InstructionCountCI/RPRES/Secondary.json index 55a145542..2f8c5122d 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary.json +++ b/unittests/InstructionCountCI/RPRES/Secondary.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "rsqrtps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json index 709d63355..b4271a28f 100644 --- a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json +++ b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json @@ -9,7 +9,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "rsqrtss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json index c0cd12210..66f01a93d 100644 --- a/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json +++ b/unittests/InstructionCountCI/RPRES/VEX_map1_AFP.json @@ -8,7 +8,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vrsqrtps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Repeat.json b/unittests/InstructionCountCI/Repeat.json index 21ecf74e8..d0fb80b18 100644 --- a/unittests/InstructionCountCI/Repeat.json +++ b/unittests/InstructionCountCI/Repeat.json @@ -6,7 +6,7 @@ "SVE128", "SVE256" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": {} } diff --git a/unittests/InstructionCountCI/SSE42_Strings.json b/unittests/InstructionCountCI/SSE42_Strings.json index 78727d55a..04c1fe332 100644 --- a/unittests/InstructionCountCI/SSE42_Strings.json +++ b/unittests/InstructionCountCI/SSE42_Strings.json @@ -33,7 +33,7 @@ " - 1b: ECX = MSB", "[7] - Reserved" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "pcmpestrm xmm0, xmm1, 0_0_00_00_00b": { diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index ff4e0dc6f..d9a8facca 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Comment": [ "MMX instructions are defined as optimal without SRA being used for these instructions.", diff --git a/unittests/InstructionCountCI/SecondaryGroup.json b/unittests/InstructionCountCI/SecondaryGroup.json index 58aec9701..f693242a1 100644 --- a/unittests/InstructionCountCI/SecondaryGroup.json +++ b/unittests/InstructionCountCI/SecondaryGroup.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "sgdt [rax]": { diff --git a/unittests/InstructionCountCI/SecondaryModRM.json b/unittests/InstructionCountCI/SecondaryModRM.json index 0f57ae274..e906b4680 100644 --- a/unittests/InstructionCountCI/SecondaryModRM.json +++ b/unittests/InstructionCountCI/SecondaryModRM.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "xgetbv": { diff --git a/unittests/InstructionCountCI/Secondary_32Bit.json b/unittests/InstructionCountCI/Secondary_32Bit.json index eedc3c9fe..6d70c3937 100644 --- a/unittests/InstructionCountCI/Secondary_32Bit.json +++ b/unittests/InstructionCountCI/Secondary_32Bit.json @@ -7,7 +7,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "push fs": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index d13dc64be..199a13032 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "movupd xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json index 608249ec8..192853f2d 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "addsubpd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json index f80570fe5..6c27181f9 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "psrlw xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json index fe4eca349..a90bb4a13 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json +++ b/unittests/InstructionCountCI/Secondary_OpSize_SVE256.json @@ -7,7 +7,7 @@ "AFP" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "pmulhuw xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 3a1845e17..60549234c 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -12,7 +12,7 @@ "FRINTTS", "CSSC" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "movss xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 6dd4d31c9..d15eb7b98 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -10,7 +10,7 @@ "FCMA", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "movsd xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json index 0c7326975..ee6b8602a 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_FCMA.json @@ -9,7 +9,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "addsubps xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json index 99a297998..96fd592b6 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json @@ -10,7 +10,7 @@ "FCMA", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "cvtpd2dq xmm0, xmm1": { diff --git a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json index 7e14bbb75..e0d7d78ba 100644 --- a/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json +++ b/unittests/InstructionCountCI/Secondary_REP_FRINTTS.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "cvttss2si eax, xmm0": { diff --git a/unittests/InstructionCountCI/Secondary_SVE128.json b/unittests/InstructionCountCI/Secondary_SVE128.json index 7e53b0b66..3b507667d 100644 --- a/unittests/InstructionCountCI/Secondary_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_SVE128.json @@ -8,7 +8,7 @@ "SVE256", "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "movmskps eax, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index a32427da0..5f2377efe 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -13,7 +13,7 @@ "FLAGM2", "FRINTTS" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vmovups xmm0, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map1_FCMA.json b/unittests/InstructionCountCI/VEX_map1_FCMA.json index 55661b97f..3ad598a5b 100644 --- a/unittests/InstructionCountCI/VEX_map1_FCMA.json +++ b/unittests/InstructionCountCI/VEX_map1_FCMA.json @@ -8,7 +8,7 @@ "FCMA" ], "DisabledHostFeatures": [], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vaddsubpd xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json index 3a20de988..8a766e343 100644 --- a/unittests/InstructionCountCI/VEX_map1_FRINTTS.json +++ b/unittests/InstructionCountCI/VEX_map1_FRINTTS.json @@ -13,7 +13,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vcvttss2si eax, xmm0": { diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index 7cc63fcb5..7e3d7685e 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -11,7 +11,7 @@ "FLAGM2", "SVEBITPERM" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vpshufb xmm0, xmm1, xmm2": { diff --git a/unittests/InstructionCountCI/VEX_map2_svebitperm.json b/unittests/InstructionCountCI/VEX_map2_svebitperm.json index ebe8b4023..4ca642f2e 100644 --- a/unittests/InstructionCountCI/VEX_map2_svebitperm.json +++ b/unittests/InstructionCountCI/VEX_map2_svebitperm.json @@ -11,7 +11,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "pext eax, ebx, ecx": { diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 7bea2dbc1..273c095a8 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -8,7 +8,7 @@ "DisabledHostFeatures": [ "AFP" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vpermq ymm0, ymm1, 1": { diff --git a/unittests/InstructionCountCI/VEX_map_group.json b/unittests/InstructionCountCI/VEX_map_group.json index 87954025b..fabb47a11 100644 --- a/unittests/InstructionCountCI/VEX_map_group.json +++ b/unittests/InstructionCountCI/VEX_map_group.json @@ -9,7 +9,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "vpsrlw xmm0, xmm1, 0": { diff --git a/unittests/InstructionCountCI/X87ldst-SVE.json b/unittests/InstructionCountCI/X87ldst-SVE.json index 7f0083c9e..5eaa84a41 100644 --- a/unittests/InstructionCountCI/X87ldst-SVE.json +++ b/unittests/InstructionCountCI/X87ldst-SVE.json @@ -11,7 +11,7 @@ "FLAGM2", "RPRES" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "fstp tword [rax]": { diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 43d8499d0..df3a30fb4 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -10,7 +10,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/x87_32Bit.json b/unittests/InstructionCountCI/x87_32Bit.json index 5a7088503..7fea92cfc 100644 --- a/unittests/InstructionCountCI/x87_32Bit.json +++ b/unittests/InstructionCountCI/x87_32Bit.json @@ -10,7 +10,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "Multiple fld/fst": { diff --git a/unittests/InstructionCountCI/x87_f64.json b/unittests/InstructionCountCI/x87_f64.json index c29a09a63..be94bc871 100644 --- a/unittests/InstructionCountCI/x87_f64.json +++ b/unittests/InstructionCountCI/x87_f64.json @@ -12,7 +12,7 @@ "FLAGM", "FLAGM2" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "fadd dword [rax]": { diff --git a/unittests/InstructionCountCI/x87_f64_32Bit.json b/unittests/InstructionCountCI/x87_f64_32Bit.json index 7d17a074a..e8dfcad7b 100644 --- a/unittests/InstructionCountCI/x87_f64_32Bit.json +++ b/unittests/InstructionCountCI/x87_f64_32Bit.json @@ -15,7 +15,7 @@ "SVE256", "CSSC" ], - "BinaryCacheVersion": 17 + "BinaryCacheVersion": 18 }, "Instructions": { "fstp dword [ebx*4+0x204a20]": {